JPH064306A - How to divide interrupt processing - Google Patents

Abstract

(57) [Abstract] [Purpose] The interrupt response is improved, and the interrupt processing can be divided with less overhead, thereby improving the performance of the computer system. [Structure] The interrupt processing is divided into a high-priority primary processing and a low-priority secondary processing, and a secondary interrupt is generated during execution of the primary processing of the primary processing unit 11 generated by an interrupt from the peripheral device 13. After requesting and ending the primary processing, the secondary processing of the secondary processing unit 12 corresponding to the secondary interrupt from the secondary interrupt generation device 14 is activated, and the primary interrupt is issued from the peripheral device 13 during the execution of the secondary processing. When occurs, the secondary processing unit 12 interrupts the secondary processing that is being executed, and activates the primary processing of the primary processing unit 11 corresponding to the primary interrupt,
After the completion of the primary processing, the suspended secondary processing is restarted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of dividing interrupt processing in a computer system.

[0002]

2. Description of the Related Art Conventionally, in this type of interrupt processing, an interrupt generation instruction prepared by a processing unit (CPU) is used in the primary processing executed by a primary processing unit in response to a primary interrupt, "Software interrupt") is generated and the secondary processing unit is activated by this software interrupt.

Further, in a computer system in which an operating system (hereinafter referred to as "multitask OS") capable of realizing a plurality of execution units (tasks) is mounted, interrupt processing is performed by a primary interrupt that is activated by a primary interrupt. It is divided into a processing unit and a secondary processing unit that operates as a task controlled on the multi-task OS, and a start of a task (hereinafter, referred to as an “interrupt task”) that executes a secondary treatment in the primary processing is multi-tasked. Ask the task OS,
There was a method of dividing the interrupt processing by operating the interrupt task.

[0004]

However, when the secondary processing is operated by a software interrupt, the priority of the secondary processing section becomes higher than that of the primary processing section, and the primary interrupt of the secondary processing section is executed at the time of execution of the secondary processing section. There was a problem that we could not accept. Further, when the secondary processing is operated as a task, the processing that stops the task that was operating before the primary interrupt occurs and passes control to the interrupt task (hereinafter referred to as “task switch processing”) is performed. However, there is a problem in that the load on the computer system is increased.

The present invention has been made in view of the above problems, and provides an interrupt processing dividing method capable of improving interrupt response and executing interrupt processing with less overhead, thereby improving the performance of a computer system. The purpose is to provide.

[0006]

In order to achieve the above object, the present invention divides a process generated by an external interrupt into a high-priority primary process and a low-priority secondary process, The processing device issues a secondary interrupt during the execution of the primary processing, activates the secondary processing corresponding to the secondary interrupt after the completion of the primary processing, and executes the primary processing from the outside while executing the secondary processing. When an interrupt is issued, there is a method of dividing interrupt processing in which the secondary processing being executed is interrupted, the primary processing corresponding to the primary interrupt is activated, and the secondary processing is restarted after the completion of the primary processing. Provided.

[0007]

The interrupt process is divided into the primary process and the secondary process, and the secondary process is operated with a lower priority than the primary process.
Therefore, the response to the primary interrupt can be improved, and the interrupt processing can be divided without overhead such as task switch.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings of FIGS. FIG. 1 is a diagram showing the configuration of a computer system for explaining a method of dividing interrupt processing according to the present invention. In the figure, as is well known, a CPU 10 interprets each instruction of a program and controls the various circuits so as to operate a specific function, as is well known.
It is composed of a storage unit that stores data and programs in a series of locations, a calculation unit that performs logical operations, and an internal bus that connects these units, and the internal bus is connected via an input / output interface (not shown). The peripheral device 13 and the secondary interrupt generation device 14 are connected to each other.

In the CPU 10, the arithmetic unit performs a logical operation on the operand read from the storage unit under the control of the control unit, and executes an interrupt process corresponding to the interrupt from the peripheral device 13 and the secondary interrupt generation device 14. To do. CPU for interrupt in this embodiment
The processing function of 10 is a primary processing unit 1 having a function of being activated by a high-priority primary interrupt generated from the peripheral device 13.
1 and a secondary processing unit 1 having a function of being activated by a secondary interrupt of low priority generated from the secondary interrupt generation device 14.
2 and.

In the CPU 10 according to the present embodiment, in the primary processing of the primary processing unit 11 which is activated by the primary interrupt of high priority, the secondary interrupt generation for generating the secondary interrupt of lower priority than the primary interrupt is generated. The device 14 is requested to generate the secondary interrupt, and the secondary processing unit 12 is activated. At this time, the time when the secondary processing unit 12 is actually activated is the time when all the primary processing corresponding to the primary interrupt with high priority is completed, and the secondary processing unit 12 activated by the secondary interrupt. If a primary interrupt occurs during the secondary processing of, the secondary processing is interrupted, the primary processing is immediately started, and the interrupted secondary processing is restarted when the primary processing ends. It Further, in the present embodiment, it is also possible to request the secondary interrupt generation device 14 to generate a secondary interrupt during the secondary processing of the secondary processing unit 12.

Next, the operation of interrupt processing will be described with reference to the flowchart of FIG. First, when the primary interrupt A is generated from the peripheral device 13, the CPU 10 activates the primary processing unit 11 to execute the primary processing corresponding to the primary interrupt A. In the primary processing, the primary processing unit 11 requests the secondary interrupt generation device 14 to generate a secondary interrupt, and activates the secondary processing unit 12.

The secondary interrupt generation device 14 can generate the secondary interrupt B in response to the request when all the primary processing of the primary processing unit 11 is completed. When the secondary interrupt B is generated from the secondary interrupt generator 14, C
In the PU 10, the secondary processing unit 12 is activated to execute the secondary processing corresponding to the secondary interrupt B. When the primary interrupt C is generated from the peripheral device 13 in this secondary processing, in the CPU 10, the secondary processing unit 12 interrupts the secondary processing being executed, and the primary processing unit 11 responds to the primary interrupt C. Executes primary processing. In the primary processing, the primary processing unit 11 requests the secondary interrupt generation device 14 to generate a secondary interrupt in the same manner as described above.

The secondary processing unit 12 determines when all the primary processing corresponding to the primary interrupt C of the primary processing unit 11 is completed,
The secondary processing corresponding to the secondary interrupt B is restarted. The secondary interrupt generation device 14 generates a secondary interrupt D in response to a request from the primary processing unit 11 when all the secondary processing corresponding to the secondary interrupt B of the secondary processing unit 12 is completed. You can

When the secondary interrupt D is generated from the secondary interrupt generator 14, the CPU 10 activates the secondary processing unit 12 to execute the secondary processing corresponding to the secondary interrupt D. In the secondary processing, the secondary processing unit 12 requests the secondary interrupt generation device 14 to generate a secondary interrupt. The secondary interrupt generation device 14 generates a secondary interrupt E in response to a request from the secondary processing unit 12 when all the secondary processing corresponding to the secondary interrupt D of the secondary processing unit 12 is completed. be able to.

Therefore, in the present embodiment, the interrupt process is divided, the secondary interrupt of low priority is issued during the execution of the primary process of high priority, and the secondary interrupt is dealt with after the completion of the primary process. Since the secondary processing can be activated, the response to the primary interrupt can be improved. Further, in this embodiment, since the interrupt processing is divided according to the priority level, it is possible to realize the interrupt processing division without overhead such as task switch.

[0016]

As described above, according to the present invention, the processing generated by the external interrupt is divided into the primary processing with high priority and the secondary processing with low priority, and the processing device A secondary interrupt is issued during execution of a process, a secondary process corresponding to the secondary interrupt is started after the completion of the primary process, and a primary interrupt is issued from the outside during execution of the secondary process. And, the secondary processing being executed is interrupted, the primary processing corresponding to the primary interrupt is activated, and the secondary processing is restarted after the completion of the primary processing, so that the response of the interrupt is improved and the overhead is increased. Can divide interrupt processing with less
This can improve the performance of the computer system.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a computer system for explaining an interrupt processing dividing method according to the present invention.

FIG. 2 is a flowchart for explaining an operation of interrupt processing of the CPU shown in FIG.

[Explanation of symbols]

 10 CPU 11 Primary Processing Unit 12 Secondary Processing Unit 13 Peripheral Device 14 Secondary Interrupt Generation Device

Claims (1)

[Claims] 1. A process generated by an external interrupt is divided into a high-priority primary process and a low-priority secondary process, and a processing device issues a secondary interrupt during execution of the primary process. Then, after the completion of the primary processing, the secondary processing corresponding to the secondary interrupt is activated, and during the execution of the secondary processing,
When a primary interrupt is issued from the outside, the secondary processing being executed is interrupted, the primary processing corresponding to the primary interrupt is activated, and the secondary processing is restarted after the completion of the primary processing. Characteristic interrupt processing division method.