JPH0640666B2 - Output signal reproduction circuit of solid-state imaging device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a solid-state imaging device for obtaining a high-resolution image using a solid-state imaging device having a limited number of pixels, which has a plurality of photosensitive parts arranged on a semiconductor substrate. Of the output signal reproducing circuit.

[Technical background of the invention and its problems]

The solid-state image sensor such as CCD has the features of small size, light weight and high reliability as compared with the conventional image pickup tube, and has many advantages in terms of characteristics such as no graphic distortion, a small afterimage and no image sticking. ing. Therefore, its applications are widespread, such as industrial television cameras, home video cameras, and electronic cameras that do not use silver halide film, and are expected to be further expanded in the future.

FIG. 11 shows a schematic structure of a typical interline transfer CCD image pickup device. Pij (i = 1, 2, ...,
M, j = 1, 2, ..., N) is a two-dimensionally arranged photosensitive portion,
Ci is a vertical read register and H is a horizontal read register. When such a solid-state imaging device is applied to a wide range of application fields as described above, how to achieve high resolution with a limited number of pixels becomes a big problem.

Therefore, the inventors previously proposed in Japanese Patent Application No. 56-209381 a device for achieving high resolution by using a solid-state image sensor having a limited number of pixels. This device has a chip substrate 1 for a solid-state image pickup device, as shown in the principle diagram of FIG.
The - (horizontal rows shown only), in the horizontal direction (X direction), is relatively vibrating with respect to the incident optical image with P _H / 2 of the amplitude is 1/2 equivalent of the horizontal pixel pitch P _H. Here, as shown in the figure, the time change of the vibration is as follows:
The (A) field and the second (B) field are trapezoidal in synchronism with the imaging operation for one frame period. As a result, the aperture of the pixel shown in the figure is at the position of the solid line 2 in the A field and at the position of the broken line 3 in the B field. Then, the drive timing is shifted so as to form an image corresponding to the positions of the A and B fields, or by signal processing, and the A and B fields are added on the reproduced image, so that the solid-state imaging device itself has The horizontal resolution can be doubled. Further, since the ineffective portion of the solid-state image pickup element with respect to the incident optical image is reduced, the moire characteristic of the solid-state image pickup element is improved.

The operation and signal processing of this device will be described in more detail with reference to FIG. In the operation for obtaining high resolution, first, the A and B fields represented by the vertical synchronizing pulse shown in FIG. 13 are set as one frame period, and a trapezoidal vibration pulse is obtained in synchronization with this frame period. Then, this vibration pulse is applied to the chip substrate of the solid-state imaging device. The amplitude of the vibration pulse is set to an amount capable of obtaining 1/2 of the horizontal pixel pitch P _H. Then, in order to obtain a signal corresponding to the input optical image of the A and B fields, here, the timing of the drive clock of the horizontal read register of the solid-state image pickup device is shifted in synchronization with the A and B fields. The output signal of the solid-state image sensor is synchronized with the clock pulse applied to the horizontal read register. Thus obtained by shifting half a phase of the clock pulses applied to the horizontal reading register in the phase of the output signal of the solid-state imaging device shifted P _H / 2 equivalent.

The output signal obtained by these series of operations is the thirteenth
The waveform is as shown in the figure. This waveform usually contains a reset noise component near 500V and a DC offset component of 5V to 10V. Therefore, the signal processing of this device needs to remove the reset noise component and the DC offset component without degrading the rectangular signal waveform. A linear detection circuit is suitable for this removal, but in the case of a 400H × 500V pixel interline transfer type CCD designed and prototyped by the inventors, the frequency cp of the clock pulse of the horizontal read register is 7.16 MHz. . In this case, in order to process the rectangular wave component of the signal component without deterioration, the frequency band of the linear detection circuit is required to be 20 MHz or more in the case of passing up to the third harmonic contained in the signal. This is very difficult in terms of circuit fabrication. Further, in such a wideband circuit, the phase characteristic is usually deteriorated. Therefore, there is a problem that the difference in the amplitude of the output signal between the A and B fields appears, and flicker is likely to occur.

As a method of removing the reset noise component, there is a method of using a low pass filter (LPF). This uses an LPF whose output signal band of CCD is a clock pulse frequency cp / 2 of a horizontal read register. The signal obtained by this is an averaged signal as the waveform shown in FIG. In this case, the moire improvement effect can be obtained, but the horizontal resolution cannot be improved.

[Object of the Invention]

The present invention has been made in view of the above points, and in a solid-state imaging device of a system in which a chip substrate of a solid-state imaging device is vibrated in synchronism with A and B fields, an output signal thereof is once horizontally generated by a signal processing circuit. An object of the present invention is to provide an output signal reproducing circuit capable of realizing a signal waveform necessary for obtaining a high resolution image by re-sampling the averaged waveform.

[Outline of Invention]

The present invention is, for example, an interline transfer type CCD as shown in FIG. 11, in which the signal charges accumulated in the photosensitive portion are simultaneously moved to the vertical read register in the vertical blanking period, and are transferred during the effective period of the next field. The chip substrate of the solid-state image pickup device having the image pickup operation of reading out is synchronized with the A and B fields by an image pickup method in which one frame period is provided in the A and B fields, and the chip substrate is relative to the input optical image. The object is a solid-state imaging device that is vibrated mechanically to achieve high resolution. That is, according to the present invention, in such a system, an output signal reproducing circuit for reproducing an output signal averaged in the horizontal direction by signal processing into a signal preferable for high resolution is provided. This output signal reproducing circuit has a frequency equal to the horizontal read-out frequency of the solid-state image sensor, and has a phase in which the peak position or its vicinity is aligned with the spatial sampling point of the incident light image (thus, the phase shifts by 180 degrees in the A and B fields). A circuit that generates a carrier signal having a phase) is provided, and a modulation circuit that amplitude-modulates this carrier signal by an averaged output signal of the solid-state image sensor is provided, and the obtained amplitude-modulated signal and the averaged output of the solid-state image sensor are provided. It is characterized in that a means for synthesizing with a signal is provided.

〔The invention's effect〕

By using the output reproducing circuit as in the present invention, a wide band linear detection circuit as in the conventional signal processing is unnecessary,
In the signal processing that is normally performed, flicker does not occur, an image with high stability and high resolution and less moire can be obtained.
Further, in the present invention, an image signal with less distortion can be obtained by using a sine wave as the carrier signal. This means that the deterioration degree of the image signal can be made smaller than the case where the conventional linear detection circuit is used even if the phase distortion deterioration and the frequency characteristic deterioration of the transmission line system of this signal are performed. Further, according to the present invention, even if the frequency characteristic of the signal transmission line or the signal processing circuit of the monitor is deteriorated, the contrast ratio on the reproduced image is not significantly decreased. The reason is as described in detail later,
This is because the averaged output signal component, which is a low-frequency component effective for contrast, is large in the present invention. Further, according to the present invention, an image signal having a good S / N can be obtained. This can be achieved by cutting off the carrier signal applied to a level equal to or lower than the predetermined level of the averaged output signal or reducing the signal amount. Further, in the present invention, since a sine wave is used for the carrier signal, overlapping with adjacent pixels occurs, so that a reproduced image that is easy to see can be obtained.

Example of Invention

FIG. 1 is a block diagram of an embodiment of the present invention. The incident optical image passes through the imaging lens 10 and is formed on the solid-state imaging device chip 11. The solid-state image pickup device chip 11 is, for example, an interline transfer CCD image pickup device as shown in FIG. 11, and is fixed on the vibrating table 12. First to shake table 12
The vibration pulse described in FIGS. 2 and 13 is applied from the vibration pulse generator 13. The vibration pulse is synchronized with the A and B fields. The timing generation circuit 14 generates a pulse required for driving the solid-state image pickup element chip 11 and a pulse required for signal processing according to a standard method. P _H /
The 2 delay circuit 15 delays the clock pulse of the horizontal read register by an amount corresponding to ½ of the horizontal pixel pitch P _H. The clock driver 16 is a driver for clock pulses applied to each electrode of the solid-state image sensor chip 11. The output signal of the solid-state image pickup device chip 11 obtained by these operations is subjected to reset noise removal, blanking process, white clipper, gamma correction, etc. included in the output signal of the solid-state image pickup device in the normal signal processing circuit 17. To do. The signal obtained by this processing is a horizontally averaged waveform. The output signal reproducing circuit 18 outputs the averaged waveform.
High resolution can be obtained by passing through.

The output signal reproducing circuit 18 is a DC reproducing circuit 19 for reproducing the input image signal into a signal containing a DC component, an amplitude modulating circuit 20 for amplitude modulating the carrier signal from the carrier signal generating circuit 25 by the output signal, and an amplitude modulated circuit. It is configured by a carrier clamp circuit 21 that clamps the negative peak position of the signal at the carrier cycle. The carrier signal generation circuit 25 inputs a pulse having the same frequency as the clock pulse of the horizontal read register or a frequency which is an integral multiple of this to the phase matching circuit 22 and the output waveform of the phase matching circuit 22 by 18 times.
A 180 ° shift circuit 23 that shifts by 0 ° and a switching circuit 24 that switches between a waveform shifted by 180 ° and a waveform that is not shifted in synchronization with the A and B field periods. The clamp pulse circuit 26 forms a waveform whose phase coincides with that of the carrier signal, here, a waveform obtained from the output signal of the switching circuit 24, into a rectangular wave pulse required for clamping the carrier period. Then, a clamp pulse is applied to the clamp input terminal of the carrier clamp circuit 21. The clamp voltage generation circuit 27 is a circuit for converting the averaged image signal into a waveform suitable for the amount of the image signal level in the carrier clamp circuit,
Here, a clamp voltage is generated using the output signal of the direct current regeneration circuit 19 and is input to the carrier clamp circuit 21.
The output of the carrier clamp circuit is input to a display device such as a monitor and reproduced.

Next, the operation of the signal reproducing circuit 18 will be described with reference to the signal waveforms of the respective parts shown in FIG. As shown in FIG. 2, the spatial sampling point in the solid-state imaging device in the case of imaging a subject whose light amount changes stepwise from the left side to the right side of the screen is the position indicated by the black dot in the image information waveform. This sampling point is displaced by ½ of the horizontal pixel pitch P _H between the A field and the B field with reference to the starting point of the horizontal image signal. 13th centering around this sampling point
By adding the A and B fields as the rectangular wave output signal shown in the figure on the reproduced image, the horizontal resolution can be improved to twice the value of the solid-state image pickup device itself. However, when the normal signal processing circuit 17 is used, the image signal obtained at its output has a signal waveform averaged in the horizontal direction as shown in FIG. Even if this signal waveform is added as it is on the reproduced image, high resolution cannot be expected. Therefore, in this embodiment, first, the averaged image signal is converted into an image signal containing a direct current component by the direct current reproduction circuit 19, and the amplitude modulation circuit 20 uses this to generate the same carrier as the horizontal read frequency cp. Modulate. The important thing here is the amplitude modulation circuit 2
It is the phase of the carrier added to 0. The carrier phase is
Amplitude modulation is performed so that the peak point in one carrier cycle matches the spatial sampling point shown by the black dot in FIG.

The generation of such carriers is generated by the timing generation circuit 14
The horizontal read clock (frequency cp) from the signal is phase-matched by the phase-matching circuit 22 so as to match the spatial sampling point, and the signal passed through the 180-degree shift circuit 23 is a field pulse synchronized with the A and B fields. It is obtained by switching in the switching circuit 24 using. This carrier frequency is 7.16 MHz when a horizontal 400 pixel CCD is used.

The amplitude-modulated wave thus obtained is the carrier clamp circuit 2
At 1, the clamp pulse is clamped at the negative peak point 31 within one cycle of the carrier included in the modulated wave, that is, at the intermediate position of each sampling point in the time axis direction of the spatial sampling point indicated by the black dot in FIG. The voltage to be clamped is a waveform obtained by DC-reproducing a signal obtained by averaging the CCD output signals. As a result, the signal level of the output of the carrier clamp circuit 21 can be clamped to the clamp voltage 32 obtained by the averaging signal on the negative side of the modulated wave as shown in the figure. Then, by adding the signals of the A and B fields on the reproduced image, the waveform shown in FIG. 2 is obtained. This addition signal is shown by the solid line for the A field signal and is shown by the dotted line for the B field signal. As a result, the sampling point in the horizontal direction on the reproduced image is at position 33 in the A field and at position 34 in the B field, which is twice the value of the solid-state image sensor itself. Therefore, double the resolution can be obtained on the reproduced image. The high-resolution image signal obtained by this method has extremely low distortion because the high-resolution signal component, that is, the carrier component, is a sine wave. Since the signal is clamped every pixel period, noise included in the signal is suppressed and S / N is improved. Further, the signal frequency components included in the output waveform are the average signal and the high resolution signal.
Therefore, the problem of the contrast reduction on the reproduced image due to only the high resolution signal seen in the output waveform of the conventional linear detection circuit does not occur, and a normal contrast image and a high resolution signal can be obtained. .

Next, a specific configuration example of the circuit 28 including the carrier clamp circuit 21 and the clamp voltage generation circuit 27 shown in FIG. 1 will be described. FIG. 3 shows an example of the specific circuit configuration. This circuit consists of transtars TR ₁ , TR ₂ , TR ₃ , T
Is composed of R _4, the transistor TR ₁ and the resistor R ₁ is an emitter follower circuit which acts as an input buffer, the transistors TR ₄ and the resistor R ₄ is an emitter follower circuit which ho action of the output buffer. The transistor TR ₂ and the resistor R ₂ are clamp circuits that clamp each pixel (each carrier cycle),
The capacitor C ₂ and the transistor TR ₃ are circuits that obtain a clamp voltage from the averaged signal. This circuit has a power supply voltage V _A
And V _B. The amplitude-modulated signal is input to the base of Transitus TR ₁ . And the transistor T
Connecting Lower the emitter of R ₁ to impedance can be clamped by the resistor R ₁ to the collector of the transistor TR ₂ of the clamp through the capacitor C _1. On the other hand, the clamp pulse passes through the capacitor C ₂ and the resistor R ₂
Clamp transistor TR biased by
Supplied on base of ₂ . Further, the averaged output signal of the solid-state image pickup device is applied as a clamp voltage to the emitter of the clamp transistor TR ₂ . To this, an averaged output signal is input to the base of the transistor TR ₃ , a resistor R ₃ is connected to this emitter to reduce the impedance, and then applied to the emitter of the clamping transistor TR ₂ . As a result, the amplitude modulation signal is clamp pulse ON, O
It is clamped to the voltage of the output signal averaged according to FF, and is output through the output buffer circuit composed of the output transistor TR ₄ and the resistor R ₄ .

Next, the effect of preventing the deterioration of the image signal due to the deterioration of the frequency characteristics of the transmission line system and the signal processing circuit of the monitor, which is one of the effects of the embodiment, will be described in detail. FIG. 4 is a diagram showing the relationship of the response with respect to the frequency of the image signal of the embodiment. In the present embodiment, the frequency response has a value indicated by hatching in the lower right of the figure for the averaging signal, and a value shown by hatching in the lower left of the figure for the carrier modulation signal corresponding to the high resolution signal. As is apparent from this figure, in the present embodiment, the low frequency component of the image signal is obtained from the averaged output signal. Therefore, even if the frequency characteristics of the signal processing circuit of the transmission line system and the monitor are deteriorated, there is almost no loss of low-frequency components, and a good image signal can be obtained.
For example, the frequency characteristic of 40 in FIG. 4 is a case where there is no deterioration, whereas the frequency characteristic of 41 has a slight decrease in the carrier modulation signal component. However, since the averaged signal does not decrease, the image signal is such that the degree of modulation of the high resolution component is slightly reduced, and there is almost no problem on the reproduced image. Further, when the frequency characteristic has a value of 42, the carrier modulation signal component is considerably reduced, but the averaged signal is hardly reduced even with this. Therefore, it is possible to transmit or reproduce while obtaining a sufficient level as an image signal.
In the case of No. 42, the resolution is slightly lowered, but the degree of decrease is slight as compared with the case of using the conventional high frequency detection circuit.

FIG. 5 and FIG. 6 show another embodiment for simply implementing the present invention. In this case, noise reduction, which is one of the effects of the present invention, cannot be expected so much, but all the other effects can be obtained, and the circuit configuration becomes simple, so its practicality is sufficient. Fifth
The figure shows a configuration diagram, and FIG. 6 shows a waveform diagram of each part thereof. C
Since the operation of the CD is the same as that of the embodiment shown in FIG. 1, its explanation is omitted here. The output signal of the CCD is a signal processing circuit 51.
At, the reset noise and the like are removed, and the LPF having a band of 1/2 the frequency of the horizontal clock pulse is averaged. Then, the carrier signal generating circuit 25 obtains a carrier signal whose phase matches the spatial sampling point of the CCD by the frequency of the horizontal clock pulse of 7.16 MHz and the field pulse. This carrier signal is amplitude-modulated by the signal averaged by the amplitude modulation circuit 52. Then, by adding the signal amplitude-modulated by the adder circuit 53 and the averaged signal which is the output of the signal processing circuit 51, the output of the adder circuit 53 is composed of the averaged signal and the high resolution component as shown in FIG. It becomes a signal obtained by adding a certain carrier modulation signal. It can be easily understood that this signal is the same as that of the first embodiment described with reference to FIG. Then, if this signal is added to the A and B fields on the monitor, the sampling points in the horizontal pixel array direction are doubled to obtain a high resolution image.

FIG. 7 (a) shows a low level S / N in the fifth embodiment.
An example in which the above is improved will be described. The signal processing circuit 51, the amplitude modulation circuit 52, the addition circuit 53, and the carrier signal generation circuit 25 are the same as those in FIG. In this embodiment, a level detection circuit 54 is provided at the output of the signal processing circuit 51, and a gain control circuit 55 is provided between the amplitude modulation circuit 52 and the addition circuit 53. The gain control circuit 55 is controlled by the output of the level detection circuit 54. FIG. 7B shows an example of a gain control circuit. When the gain control circuit is below a predetermined level, the switch S ₁ is opened and S ₂ is opened.
Gain control is performed by closing and passing through an attenuator. FIG. 7 (c) shows another example of the gain control circuit, which is a method of opening the switch S ₃ to cut off the modulation signal when the level is below a predetermined level. FIG. 8 is an operation waveform diagram of each part of FIG. 7 (a) when the gain control circuit of FIG. 7 (b) is used. An amplitude modulation circuit 52 amplitude-modulates the carrier signal obtained by the carrier signal generation circuit 25 with the averaged signal of the signal processing circuit 51. On the other hand, the output of the signal processing circuit 51 is the level detection circuit 5
4 to obtain a signal that reduces the gain below a predetermined level (point P). When the gain of the output signal of the amplitude modulation circuit 52 is controlled by this signal, a modulated waveform in which the carrier component is reduced below a predetermined level (point Q) determined by the level detection circuit 54 is obtained. By adding this signal to the signal averaged by the adder circuit 53, a waveform having a low frequency component and a high frequency component is obtained. When the A and B fields are added on the monitor, the sampling points are different between the A and B fields. It becomes an image, and a high-resolution reproduced image can be obtained. In the case of this embodiment, the high resolution signal component is reduced at a low level of the image signal and the high resolution signal is cut off at a lower level, so that a high resolution image cannot be obtained. But generally in low light, you don't need much resolution,
Rather, sensitivity is required. For this reason, it is preferable to reduce the noise in the signal portion of the reproduced signal in a dark place where the level is low. Therefore, the present embodiment can reproduce the signal suitable for such a case. In an example that the inventor has conducted an experiment, it is confirmed that there is no image unnaturalness even if the carrier signal is reduced from around a signal level of 30%. Although the above description is for the gain control method in FIG. 7 (b), the same effect can be obtained when the method shown in FIG. 7 (c) is used.

9 and 10 show a gamma correction circuit which is used in a signal processing circuit which is normally used without using the level detection circuit 54 and the gain control circuit 55 in order to obtain the effect of the embodiment shown in FIG. 60 is used. The gamma correction circuit is provided to match the relationship between the signal output with respect to the optical input of the CCD and the light emission with respect to the signal input of the monitor. Normal CCD
The input / output gamma value is 1, and the monitor gamma value is
It is 2.2. Therefore, the gamma correction circuit requires 1 / 2.2 processing. The input / output relationship of this circuit is such that the gain is large at a low signal level and the gain is low at a high signal level. In this embodiment, this relationship is devised and used. FIG. 9 is a configuration diagram thereof, and FIG. 10 is a waveform of each part. The carrier signal generation circuit 25, the amplitude modulation circuit 52, and the addition circuit 53 are the same as in the case of FIG. 1 and FIG. In this embodiment, a signal before gamma correction is used as the averaging signal for amplitude-modulating the carrier signal. The gamma-corrected signal is used as the averaged signal added by the adder circuit 53. As a result, as shown in FIG. 10, the obtained output signal has a small carrier signal in a portion having a small input signal and a large carrier signal in a portion having a large input signal. Therefore, the S / N is good on the low level side, and the carrier signal increases on the high level side, and the sharpness of the high resolution signal becomes good.

In the example described above, the case has been described in which the normal NTSC system in which one frame is composed of two fields including the first and second fields is adapted, but the present invention is not limited to this, and the resolution is further improved. For example, it can be applied to an imaging method in which one frame is composed of the first, second, third, and fourth fields. In this case, if the spatial sampling points in the first to fourth fields are set to different positions and the phase of the carrier signal in the reproducing circuit is adjusted to the first to fourth fields, respectively, the resolution can be improved. can get.

Further, although the embodiment described above is for a monochrome camera, the present invention is not limited to this and can be applied to a color camera. For example, it can be applied to a single-plate color camera using one solid-state imaging device, a three-plate color camera using three solid-state imaging devices, or the like.

Further, the present invention can be applied to an electronic camera. In this case, a shutter for turning on and off the light is provided in the input optical path to take an image. An electronic camera employs a method of once recording an image pickup signal, for example, magnetically recording it and reproducing it when necessary. In this case, the signal to be magnetically recorded can use the averaged signal described in FIG. In this equation, the signal reproducing circuit of the present invention may be provided on the reproducing side. As a result, the frequency band to be recorded can be lowered.

In addition to the interline transfer type CCD, the present invention is applicable to signal processing of a frame transfer type CCD, a two-story sensor in which a photoconductive film is superposed on the CCD, a sensor in which photodiodes of the photosensitive section are arranged in a zigzag pattern in the vertical direction. It can be applied to obtain high resolution images.

Further, in the above embodiments, the high-resolution image pickup device in which the CCD is vibrated to increase the spatial sampling points has been described. However, for example, the input optical path may be changed to increase the spatial sampling points, or the pixel of the CCD may be increased. It is also possible to change the combination for each field. The present invention can be applied to these signal processings to form signals necessary for obtaining high resolution pixels.

Further, the application of the present invention is not limited to video cameras and electronic cameras conforming to the standard television system, but is also applicable to other devices having means for capturing an incident optical image such as OCR, facsimile, and copy, and the same. The effect can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation thereof, FIG. 3 is a diagram of a concrete circuit configuration example of the carrier clamp circuit of FIG. 1, and FIG. 4 is the first
5 is a diagram for explaining the effect of the embodiment of the present invention, FIG. 5 is a configuration diagram of another embodiment of the present invention, FIG. 6 is a signal waveform diagram for explaining the operation thereof, and FIG. 7 is for FIG. FIG. 8 is a configuration diagram of an improved embodiment, FIG. 8 is a signal waveform diagram for explaining the operation, and FIG. 9 is a configuration diagram of still another embodiment of the present invention.
FIG. 0 is a signal waveform diagram for explaining the operation, FIG. 11 is a diagram showing a schematic structure of an interline transfer type CCD, and FIG. 12 is a solid-state image pickup device for obtaining high resolution previously proposed by the inventors. The principle diagram and FIG. 13 are signal waveform diagrams for explaining the operation. 11 ... Solid-state image sensor chip, 12 ... Shaking table, 13 ...
… Signal pulse generator, 14 …… Timing generator,
15 ...... P _H / 2 delay circuit, 16 ...... Clock driver, 17 ...... signal processing circuit, 18 ...... output signal reproducing circuit, 19 ...... DC restoration circuit, 20 ...... amplitude modulation circuit, 2
1 ... Carrier clamp circuit, 22 ... Phase matching circuit, 23 ... 180 ° shift circuit, 24 ... Switching circuit,
25 ... Carrier signal generation circuit, 26 ... Clamp pulse generation circuit, 27 ... Clamp voltage generation circuit, 53 ...
Addition circuit, 54 ... Level detection circuit, 55 ... Gain control circuit.

Claims (4)

[Claims] 1. A solid-state image sensor having a photosensitive portion arranged one-dimensionally or two-dimensionally on a semiconductor substrate, and at least a first field and a second field constitute one frame. A circuit for reproducing an output signal of a solid-state image pickup device in which a spatial sampling point of a photosensitive portion of the solid-state image pickup device moves in synchronization with an incident optical image in a field of 2 and a horizontal read frequency of the solid-state image pickup device. A carrier generating circuit for generating a sine wave carrier signal having a synchronized frequency and a phase whose peak position is aligned with the spatial sampling point of the incident optical image, and the carrier signal obtained by this circuit, the solid-state imaging device A modulation circuit that performs amplitude modulation by the averaged output signal of the above, and a method of synthesizing the amplitude modulation signal obtained by this circuit and the averaged output signal of the solid-state imaging device. Output signal reproduction circuit of the solid-state imaging apparatus characterized by comprising and. 2. A carrier clamp for synthesizing the amplitude-modulated signal and an averaged output signal of a solid-state image pickup device, wherein the carrier clamp clamps a peak position of the amplitude-modulated signal in a direction opposite to a peak position of the spatial sampling point. The output signal reproducing circuit of the solid-state imaging device according to claim 1, wherein the output signal voltage is a circuit, and the averaged output signal voltage is used as a clamp voltage thereof. 3. A means for synthesizing the amplitude-modulated signal and an averaged output signal of the solid-state image pickup device, a circuit for detecting the level of the averaged output signal of the solid-state image pickup device, and the averaging by the output of this circuit. Circuit for controlling so that the amplitude of the amplitude-modulated signal is reduced or cut off when the output signal becomes equal to or lower than a predetermined level, the amplitude-modulated signal controlled by this circuit, and the averaged output. The output signal reproducing circuit of the solid-state imaging device according to claim 1, which is configured by a circuit for adding a signal. 4. A signal input to the amplitude modulation circuit is a signal before gamma correction processing, and a circuit for synthesizing the amplitude modulation signal and an averaged output signal of the solid-state imaging device is an addition circuit, The output signal reproducing circuit of the solid-state imaging device according to claim 1, wherein an input signal of the adding circuit is an output signal of the amplitude modulating circuit and an averaged signal after gamma correction processing.