JPH0638500B2 - Conductivity modulation vertical MOSFET - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a structure of a vertical MOSFET which utilizes a bipolar operation by adding a region of a conductivity type opposite to that of a source on a drain side.

[Prior art and its problems]

An element called an insulated gate bipolar transistor or IGT, COMFET, which is one type of vertical MOSFET, has characteristics such as high speed of power MOSFET and easy power control, and bipolar transistor and thyristor. Such a bipolar element is attracting attention as a semiconductor element having properties such as a low ON voltage.

However, in spite of such excellent properties, the latch-up phenomenon is likely to occur due to the parasitic thyristor formed in the structure of this device, which limits the maximum current value of the device. It is a drawback.

FIG. 2 is a sectional view showing the main part of a normal conductivity modulation type vertical MOSFET in order to explain its structure and operation. Second
Although the figure shows the case of the N-channel element, the P-channel element is an inversion of all the N-type and P-type of FIG.

In FIG. 2, this device has a P ⁺ anode region for injecting holes 1, a thin N ⁺ buffer region 2, an N ⁻ drain region 3, a low resistance P ⁺ region 4, a P substrate region 5, and an N ⁺ source region 6. , A vertical type MOS composed of a gate oxide film 7, a gate electrode 8, a cathode electrode 9 and an anode electrode 10.
It is a FET and has a structure in which a P ⁺ anode region 1 is added to a normal vertical MOSFET. The N ⁺ buffer region 2 is provided to prevent punch-through at the time of OFF and to control the injection amount of holes. Low resistance P ⁺ area 4
Is for preventing latch-up. The P ⁺ region 4 and the N ⁺ source region 6 are short-circuited by the cathode electrode 9, and the P ⁺ anode region 1, the N ⁻ drain region 3, the P ⁺ region 4, the P substrate region 5, and the N ⁺ source region 6 make the emitter. It has the same structure as a short-circuit type thyristor, and when this thyristor latches up, the maximum current is limited.

Next, the operation of this element will be described. MOS when forward blocking
Since the FET is not conducting, the PN junctions of the low resistance P ⁺ region 4, P substrate region 5, and N ⁻ drain region 3 are reverse biased, and no current flows. At this time, the gate electrode 8
When a positive voltage equal to or higher than the threshold is applied to N, an N-type inversion layer is formed on the surface of the P substrate region 5, and the MOSFET is turned on.
^- electrons are injected into the drain region 3. Therefore N ^- is the hole injection into the drain region 3 from N ⁺ P ⁺ anode region 1 via the buffer area 2, N ^- electron and hole density of the drain region 3 is very higher so-called conductivity modulation than the thermal equilibrium state The generated on-resistance has a very low value.
Then upon removal of a positive voltage of the gate electrode 8, N ^- injection of electrons into the drain region 3 is stopped, N ^- even injection of holes from the P ⁺ anode region 1 with the electron density of the drain region 3 is reduced The number of elements decreases and the element is turned off again.

FIG. 3 is a partial schematic view for explaining the mechanism of causing latch-up of this element, and the same parts as those in FIG. 2 are represented by the same symbols. Solid arrow 11 in FIG.
Is a flow of electrons from the N ⁺ source region 6 through the inversion layer on the surface of the P substrate region 5 to the N ⁻ drain region 3, and the dotted arrow 12 passes a path as close as possible to the electron flow 11 due to the attractive force of the electrons. The flow of holes is shown. Holes are dotted arrows 12
As shown in the figure, the gate electrode 8
Positive flow below the electron flow 11 for the potential of, the existing portion of the N ⁺ source region 6 and flows into the N ⁺ source region for built-potentiator dial between the N ⁺ source region 6 and the P base region However, it cannot pass through the P base region 5 and the low resistance P ⁺ region 4 and flows into the cathode electrode 9. 13
Is the resistance of the region where the holes flow,
When the current increases, the resistance 13 increases the potential on the P substrate region side at the boundary between the N ⁺ source region 6 and the P substrate region 5 on the channel side of the MOSFET. On the other hand, electrons flow in the N ⁺ source region 6 and the P substrate region 5 by the solid arrow 11.
Although the potential at the boundary between and increases, the N ⁺ source region 6
Its resistance is low, so its value is small. If the difference between these potentials approach the built-in potential between the N ⁺ source region 6 and the P base region 5, electrons are injected from the N ⁺ source region 6 in the P base region 5, P ⁺ anode region 1, N ^- drain The parasitic thyristor composed of the region 3, the P substrate region 5, and the N ⁺ source region 6 latches up. Therefore, the current can no longer be controlled by the MOS gate. The low resistance P ⁺ region 4 lowers the resistance 13 of the P base region 5 and the low resistance P ⁺ region 4 and increases the current value that causes the latch-up, so that a large current can be controlled by the MOS gate voltage. It is a thing.

This latch-up phenomenon is more likely to occur when the element is turned off. FIG. 4 is an equivalent circuit diagram of an element for explaining this, which is composed of a MOS transistor 14, a PNP transistor 15 and a parasitic NPN transistor 16, and 13 is a resistance against the hole current described in FIG. Represents the junction capacitance of the parasitic NPN transistor 16. The PNP transistor 15 is composed of the P substrate region 5 and N shown in FIG.
^- is formed in the drain region 3, ^{P +} anode region 1, N
The PN transistor 16 is formed by the N ⁺ source region 6, the P substrate region 5, and the N ⁻ drain region 3.

In FIG. 4, when the element is turned off, the MOS transistor 14 is turned off first, so that the potential of the base of the PNP transistor 15, that is, the collector of the parasitic NPN transistor 16 rises, passes through the junction capacitance 17 and is indicated by the arrow to the resistor 13. Charging current 18 flows. Since this current is added to the hole current 12 shown by the dotted arrow flowing before it is turned off, the base potential of the parasitic NPN transistor 16 rises and latch-up easily occurs.

Further, there is a problem that the latch-up phenomenon does not occur uniformly in such an element, but is likely to occur at a specific place such as near the gate pad portion or near the guard ring. FIG. 5 shows a partial cross-sectional view in the vicinity of the gate electrode pad in a normal device, and the same parts as those in FIG. 2 are represented by the same symbols. In FIG. 5, 20 is a cell portion, 21 is a gate pad portion, 23 is a cell at the peripheral edge portion adjacent to the gate pad portion 21, and 22 is another cell. 6a is an N ⁺ source region of the cell 23, and 4a is a P ⁺ region. Fig. 5 3 of the part which is shaded and separated by the alternate long and short dash line
Reference numerals a and 3b are regions where a large number of holes and electrons are present due to conductivity modulation in the ON state of the device.

At the time of turn-off, a depletion layer grows mainly in the direction of the low impurity concentration N ⁻ region 3 from the junction between the P ⁺ region 4 and the P region 5 and the N ⁻ region 3, and holes existing in the regions 3a and 3b are generated. It flows into the P ⁺ region 4 and the P region 5 by the electric field of the depletion layer. At this time, the region 3a has spread to the vicinity of the carrier diffusion length due to carrier diffusion, and the gate pad portion
The amount of holes flowing into the cell 23 adjacent to 21 is larger than the amount of holes flowing into other ordinary cells such as 22. This is because, for example, in the cell 22 other than the cell 23, only the holes in the region 3b flow in, whereas in the cell 23, the holes in the wider region 3a flow. Therefore, latch-up is more likely to occur in the cell 23 at the peripheral edge portion adjacent to the gate pad portion 21 than in the other cells. Moreover, when the temperature rises due to such current concentration, latch-up is more likely to occur and eventually the device is destroyed.

[Object of the Invention]

The present invention has been made in view of the above-mentioned points, and an object thereof is to add a region of a conductivity type opposite to that of a source to a drain side, and to provide a gate pad at a peripheral end portion of a vertical MOSFET using a bipolar operation. An object of the present invention is to provide a device structure which does not cause latch-up even when a current is concentrated on a specific cell adjacent to the cell.

[Main points of the invention]

According to the present invention, the length of the source region in the width direction is made shorter than the length of the source region at other normal positions with respect to the cell located at a specific position such as the cell at the peripheral edge adjacent to the gate pad or the like. Therefore, even if current concentration occurs in this portion, latch-up does not occur.

Example of Invention

 The present invention will be described below based on examples.

FIG. 1 is a partial cross-sectional view of the device structure of the present invention in the vicinity of the gate pad portion, which is compared with FIG.
The same parts as those in FIG. 5 of FIG. 1 are designated by the same reference numerals. The difference between FIG. 1 and FIG. 5 is that the N formed in the channel region of the cell 23 at the peripheral edge portion adjacent to the gate pad portion 21.
That is, the length of the ⁺ source region 6a is short.

In this way, the effect of short-circuiting the emitter in the parasitic thyristor is large, that is, the resistance 13 shown in the equivalent circuit of FIG. 4 is small, and latch-up does not easily occur even if current concentrates on this portion.

However, if this structure is applied to all the cells other than the cell 23, the contact area between the cathode terminal 9 and the N ⁺ source region 6 becomes small, which may cause poor contact or increase in contact resistance. The decrease in the amount increases the on-voltage of the device. On the other hand, in the present invention, the N ⁺ source region is slightly changed only in the cells at the peripheral edge near the gate pad, and the latch-up caused by the current concentration can be achieved without increasing the ON voltage of the device. It is possible to prevent the phenomenon from occurring.

〔The invention's effect〕

Vertical type M that causes conductivity modulation by bipolar action
On the other hand, the OSFET has a risk of causing latch-up due to a parasitic thyristor capable of taking a large current and destroying the element, but in the present invention, as described in the embodiments, many of the channels form a channel portion. Among the cells, for example, the cells at the peripheral end located near the gate pad section have a large possibility of latch-up because the amount of carriers flowing from the conductivity modulation region is larger than that of other cells at the time of turn-off. Therefore, in particular, by making the length of the source region of the cell located at the peripheral edge portion shorter than that of the other cells, the resistance directly below the source region is reduced and the occurrence of latch-up due to current concentration is prevented. .
Moreover, since the cells for shortening the length of the source region need only be located at the peripheral end, the present invention has an advantage that the ON voltage of the device is not increased.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a gate pad portion in the device structure of the present invention, FIG. 2 is a cross-sectional view of a main portion of a normal vertical MOSFET using a bipolar operation, and FIG. 3 is a view for explaining a latch-up mechanism. 2 is a partial model view, and FIG. 4 is a third model.
FIG. 5 is an equivalent circuit diagram of the drawing, and FIG. 5 is a partial cross-sectional view in the vicinity of a gate pad portion in a normal device. 1 ... P ⁺ anode region, 2 ... N ⁺ buffer region, 3
... N ^- drain region, 3a, 3b ... conductivity modulation region, 4, 4a ... P ⁺ region, 5 ... P base region, 6, 6
a ... N ⁺ source region, 7 ... Gate oxide film, 8 ... Gate electrode, 9 ... Cathode electrode, 10 ... Anode electrode,
11 …… electron current, 12 …… hole current, 13 …… resistance, 14 ……
MOS transistor, 15 ... PNP transistor, 16 ...
… NPN transistor, 17… Junction capacitance, 18… Charging current, 20… Cell part, 21… Gate pad part, 22… Cell, 23… Peripheral end cell.

Claims (1)

[Claims] 1. A reverse-conductivity type anode region is added to the back surface side of the one-conductivity type drain region, and a gate electrode and a reverse-conductivity type base region via an oxide film are provided on the front surface side. In a conductivity modulation type vertical MOSFET in which a plurality of cells each having a source region of one conductivity type forming a channel and a cathode electrode are arranged, a width of the source region is provided at a peripheral end of the plurality of cells. A conductivity-modulated vertical MOSFET, characterized in that cells having a shorter length in the direction than the others are provided.