JPH06332700A - Information processing equipment - Google Patents

Abstract

(57) [Summary] [Purpose] By sharing part of a register file in a processor with multiple register files,
An object of the present invention is to provide an information processing device which can reduce the amount of hardware and cost and has a high-speed communication function and high performance. [Structure] A plurality of decoding units 11 and 13, a load / store unit 20 for executing a plurality of operations, an integer operation unit
21, a floating point unit 22, a register file 25, 26 that can be accessed corresponding to each instruction stream, and a register 27 that can be accessed from any instruction stream, when the instruction is decoded by the decoding unit 11, 13, Depending on the register number, it is determined whether to access the register 25, 26 unique to the instruction stream or the shared register 27, and the data corresponding to the arithmetic unit is output accordingly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for efficiently using a plurality of arithmetic units by issuing instructions of a plurality of instruction streams in parallel.

[0002]

2. Description of the Related Art As an example of a conventional information processing apparatus, there is a multi-thread processor which processes a plurality of instruction streams simultaneously in one processor. For this method,
"A Multi-Threaded Processor Architecture With Simultaneous Instructions
Issuing "(" A Multithreaded Processor Arch
itecture with Simultaneous Instruction Issuing, "I
n Proc. of ISS'91: International Symposium on Super
computing, Fukuoka, Japan, pp.87-96, November 1991
) Is described in detail.

The structure of this conventional information processing apparatus is shown in FIG. In FIG. 3, 200 is an instruction cache, 201 is an instruction fetch unit, 202 is a decoding unit, and 203.
Is a standby station, 204 is an instruction scheduling unit, 205 is a functional unit, and 206 is a register set. The operation of the conventional information processing apparatus configured as described above will be described.

First, the instruction fetch unit 201 reads in instructions of different instruction streams from the instruction cache 200. The decoding unit 202 decodes the instructions of each instruction stream and stores the instructions in a standby station 203 connected to a functional unit 205 capable of processing.
The instruction scheduling unit 204 selects an appropriate instruction from the standby station 203 and sends it to the functional unit 205. Functional unit 205 is register set 2
Run with 06. The feature of this processor is that it executes a plurality of instruction streams by sharing an arithmetic unit.

Since the existing superscalar processing type processor has multiple (multiple) functional units only, only one instruction stream can be processed at the same time, and pipeline interlock frequently occurs due to dependency between instructions. To do.
As a result, it has been difficult to improve the use efficiency of the functional unit and improve the performance. In the processor of the conventional example, the instruction level parallelism is increased by executing the instructions of a plurality of instruction streams in parallel, and the use efficiency of each functional unit is increased.
Performance improvement can be realized.

[0006]

However, the above conventional structure has the following problems. First of all, since the register files corresponding to the respective instruction streams exist independently, the amount of hardware is large and the area of the processor becomes huge. As a result, the yield at the time of manufacturing the LSI is lowered and the cost of the processor is increased. For example, in image generation, when a screen is divided into a plurality of areas and they are to be generated at the same time, the same image generation program can be run in the instruction stream of this processor, and data can be assigned to the divided screen data. . At this time, if each register has common data in each instruction stream, it is useless to store the same data in common in the registers corresponding to each instruction stream.

Secondly, it is impossible to perform high-speed communication between each instruction stream. Of course, when an external memory is used, this is possible, but the overhead associated with memory access will occur.

In view of the above problems, the present invention reduces the amount of hardware and the cost in a processor having a plurality of register files in order to execute a plurality of instruction streams simultaneously or to speed up context switching. It is an object of the present invention to provide an information processing apparatus having a high-speed communication function between instruction streams and realizing high performance.

[0009]

[Means for Solving the Problems] To achieve the above object,
The information processing apparatus of the first invention is characterized by sharing a part of a plurality of register files having independent contexts.

The information processing apparatus of the second invention comprises a plurality of register files that share a part and an operand switch for connecting the arithmetic unit and the plurality of register files. The operand switch receives data from the register file. At the time of reading, it is characterized by determining whether or not it is a shared portion by the register number and connecting the arithmetic unit and the register file accordingly.

An information processing apparatus according to a third aspect of the present invention comprises a plurality of register files that share a part and an operand switch that connects an arithmetic unit and a plurality of register files. The operand switch receives data from the register file. At the time of writing, it is characterized by judging whether or not it is a shared portion by the register number and connecting the arithmetic unit and the register file accordingly.

An information processing apparatus according to a fourth aspect of the present invention includes a plurality of register files that share a part, an operand switch that connects an arithmetic unit and a plurality of register files,
It has a register read arbiter, and when reading data from a register file, the register read arbiter determines whether or not it is a part shared by register numbers, and if there are read requests more than the number of ports of shared registers, It is characterized by controlling instruction issuance so that it can be executed within the range of the number of ports and connecting the arithmetic unit and the register file to the operand switch.

An information processing apparatus according to a fifth aspect of the present invention includes a plurality of register files that share a part, an operand switch that connects an arithmetic unit and a plurality of register files,
It has a register write arbiter, and when writing data from the arithmetic unit to the register file, the register write arbiter judges whether or not it is a shared part by the register number, and if there is a write request more than the number of ports of the shared register. In this configuration, the arithmetic unit is controlled so that it can be executed within the range of the number of ports, and the arithmetic unit and the register file are connected to the operand switch.

[0014]

In the information processing apparatus according to the first, second and third aspects of the present invention, by sharing a part of the registers, the amount of hardware can be reduced and the cost can be reduced, and the same register can be used for each instruction stream. By having access to, it is possible to realize high performance with a high-speed communication function.

In the information processing apparatus according to the fourth and fifth aspects of the present invention, by providing the write / read arbiter for the register, the number of ports of the common register can be reduced and the hardware amount can be further reduced. Further, it becomes possible to freely use the case where the register is shared and the case where the register is not used, and it is possible to improve the performance.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an information processing apparatus according to the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an information processing apparatus according to the first embodiment of the present invention.

In FIG. 1, 10 is an instruction fetch controller for calculating and managing addresses of fetched instructions, 11 and 13 are decoding units for decoding instructions, and 12 and 14 are corresponding to decoding units 11 and 13. A decoding program counter (hereinafter referred to as decoding PC) for storing the address of the instruction being decoded. Numerals 20, 21 and 22 are arithmetic units forming an arithmetic unit. The function of the arithmetic unit is not particularly limited, but in order to simplify the description and considering a general configuration, 20 is a load / store unit for processing a memory access instruction,
1 is an integer arithmetic unit that processes integer arithmetic, 22 is
It is a floating point unit that performs the four rules of floating point and the conversion between integer and floating point. The arithmetic unit is an instruction flow I
It also holds the D number.

Reference numeral 23 is an operation switch for connecting an operation resulting from the decoding of the instruction and an immediate value to the arithmetic unit to be processed. Reference numeral 24 is a register file 2.
The operand switches, 25, 26 and 27, which connect the operands output from 5, 26 and 27 to the arithmetic units 20, 21 and 22, are register files. Register file A25 corresponds to decryption unit A11 and register file B26 corresponds to decryption unit B13. Shared register 27 corresponds to both decryption unit A11 and decryption unit B13.

Reference numeral 28 is a write switch for connecting the operation result to the corresponding register, 29 is a data dependence check unit for checking whether or not data dependence has occurred depending on the state of the scoreboard 30 and the instruction, and 30 is executing the instruction. It is a scoreboard showing the numbers of registers whose data has not been finalized.

For the sake of clarity, mechanisms having the same function (such as an instruction buffer and a decoding unit) will be distinguished by adding an appropriate alphabet to the end of the name as shown in FIG. Those to which the same alphabet is added may be considered to handle the same instruction stream. The instruction decoding units 11 and 13 are respectively replaced by the decoding unit A1.
1. Decoding unit B13. Register file 25
Register files A2 and
5, register file B26.

First, before explaining the operation, preconditions regarding data (including instructions) and configuration will be described. There are two instruction streams (threads), which are instruction stream A and instruction stream B for the sake of easy understanding. The corresponding decoding unit is called decoding unit A, decoding unit B, and the corresponding register files are register file A and register file B. Therefore, the number of instruction streams that can be executed simultaneously is 2
It is an individual. Each instruction stream has 32 registers (R0-
16) (R16 to R31), and 16 shared registers (R0 to R15) common to the instruction stream.

Although the arithmetic unit is pipelined, the detailed configuration including the number of pipeline stages is not specified because it is not directly related to the present invention. Further, the instruction decoding unit decodes one instruction for each instruction stream and can issue only one instruction at a time. The load / store unit 20 and the instruction fetch control unit 10 are connected to the memory.

In the arithmetic unit, instruction stream A or instruction stream B
Is being executed and there is no instruction to process, it is in the idle state. In the scoreboard 30, register numbers whose results have not been determined due to execution are managed for each instruction stream. However, the shared register 27 shared by the threads is also shared by the scoreboard 30 and can be set / reset by both the instruction stream A and the instruction stream B. Regarding the detailed contents, the function will be described in the operation of the embodiment.

In the information processing apparatus of the present embodiment having the above-mentioned configuration, the operation of the case where the register A and the register B are used will be described below with reference to FIG. The instruction fetch control unit 10 uses the instruction stream A and the instruction stream B.
Is fetched and transferred to the decoding unit A11 and the decoding unit B13. In this instruction fetch, each instruction stream is alternately taken and buffered. This function, the buffer, and the like have no particular relation to the present invention, and are omitted. Further, when a branch occurs, there are operations such as address calculation of a branch target instruction and fetch of a branch target instruction, but since they are not particularly related to the present invention, they are omitted.

Decoding unit A11 and decoding unit B
In order to make the operation easier to understand, the operation of the stages starting from 13 will be described from the instructions of the instruction stream A and the instruction stream B. The decoding unit A11 receives a LOAD instruction (load instruction from memory to register: ME
M (R19) → R20) is taken out, and the decoding unit B13 takes out the ADD instruction (register-to-register addition instruction: R20 + R21 → R22) from the instruction fetch control unit 10, decodes each and creates an operation, and processes the operation. Decide which arithmetic unit should be used.

At the same time, it is checked whether or not a data dependency is generated within the same instruction stream. The dependency check is performed by the scoreboard 30 and the data dependency check unit 29. Specifically, the register number for which the register value is not fixed because it is currently being executed is registered in the scoreboard, and is compared with the register number to be read from the decoding unit. return. This is to prevent an instruction to be executed hereafter from using a register value that does not reflect the result. The register number is registered when the decoding units 11 and 13 issue the instruction to the arithmetic unit, and the register number is released when the arithmetic units 20, 21 and 22 finish the instruction execution. Regarding the data dependency
SY-90-54 ('90 .7) "Improvement policy of superscalar processor based on SIMP (single instruction stream / multiple instruction pipeline) method" is described in detail.

When the data dependence has occurred, the issuance of the instruction is stopped until the dependence is released, and when it does not occur, the decoding unit issues the operation to the arithmetic unit and at the same time to the register file. Make a read request. Instruction stream A corresponds to register file A,
Since the read register numbers are R16 to R31, the decoding unit A11 sends the register numbers to the register file A25. Since the instruction stream B corresponds to the register file B26 and the register numbers are R16 to R31, the decoding unit B13 sends it to the register file B26.

The operand switch 24 connects the register file A25 and the load / store unit 25, and the register file B26 and the integer operation unit 21. The operation switch 23 connects the decoding unit and the arithmetic unit according to the decoding result. In the case of the present embodiment, the LOAD instruction is sent from the decoding unit A11 to the decoding unit B13.
Since the ADD command is issued by the operation switch 23, the operation switch 23 connects the decoding unit A11 and the load / store unit 20, and the decoding unit B13 and the integer operation unit 21.

The load / store unit 20 stores the operand value read from the register file A25, and the integer operation unit 21 stores the operand value read from the register file B26. And decoding unit A11
Load store unit 20
Then, the operation issued by the decoding unit B24 is stored in the integer arithmetic unit 21, respectively.

Hereinafter, each arithmetic unit executes using an operation or an operand and stores the result in a register, a memory or the like. In the load / store unit 20, the LOAD instruction of the instruction stream A is executed. Since the instruction stream A corresponds to the register file A25 and the register numbers of the write destination are R16 to R31, the data is fetched from the memory at the calculated memory address and stored in the register R20 in the register file A25. In the integer arithmetic unit 21, the ADD instruction is executed.

Since the instruction stream B corresponds to the register file B26 and the register numbers of the write destinations are R16 to R31, the addition result is the register in the register file B26.
Store in R22. A write switch 28 for connecting the load / store unit 20 and the register file A25, and connecting the integer arithmetic unit 21 and the register file B26.
Is controlled. Each arithmetic unit clears the register number registered in the scoreboard 30 when the arithmetic operation is completed and the writing to the register is completed.

Further, when the operation issued from the instruction decoding unit uses the same arithmetic unit, the structure of the present embodiment requires a mechanism for holding either one of the operations, but this is not directly related to the present invention. Since it does not matter, the mechanism is omitted. If the configuration of the arithmetic unit changes, the waiting mechanism may become unnecessary. Similarly, when two instructions of the same instruction stream are simultaneously processed, it is necessary to wait for writing to the register, or to provide a plurality of register file write ports. Since it does not matter, its explanation is omitted.

Next, the operation when the shared register 27 is used will be described. The part for reading an instruction from the instruction fetch control unit 10 has been described above, and will be omitted. The decoding unit A11 receives a LOAD instruction from the instruction fetch control unit 10 (memory-to-register load instruction: MEM (R19) → R).
5), the decoding unit B13 uses the instruction fetch controller 10
To ADD instruction (register addition instruction: R6 + R21 → R
22), and each of them is decrypted to create an operation, and the arithmetic unit to process the operation is determined. At the same time, it is checked whether a data dependency has occurred in the same instruction stream.

The check of the dependency relationship is performed by the scoreboard 30.
And the data dependence check unit 29. Specifically, a register number whose register value is not fixed because it is currently being executed is registered in the scoreboard 30, and is compared with the register number to be read from the decoding unit. Return to. This is to prevent an instruction to be executed hereafter from using a register value that does not reflect the result. The register number is registered when the decoding units 11 and 13 issue an instruction to the arithmetic unit, and the register number is released by each arithmetic unit 2.
0, 21 and 22 are executed at the end of instruction execution.

If data dependence has occurred, the instruction issuance is stopped until the dependence is released, and if not, the decoding unit issues an operation to the arithmetic unit and at the same time writes to the register file. Make a read request. Since the instruction stream A corresponds to the register file A25 and the register numbers to be read are R16 to R31, the decoding unit A11 sends the register numbers to the register file A25. The instruction stream B corresponds to the register file B26, and one register number is R0 to R15,
Since the other register number is R16 to R31, the decoding unit B13 stores the register number R6 in the shared register 27.
Is sent to the register file B26.

The operand switch 24 connects the register file A25 and the load / store unit 20, and the integer arithmetic unit 21 connects both the register file B26 and the common register 27. Operation switch 23
Connects the decoding unit and the arithmetic unit from the decoding result. In the case of this embodiment, the decoding unit A11 to LOA
Since the AD command is issued from the decoding unit B13 as the D command, the operation switch 23 includes the decoding unit A11, the load / store unit 20, and the decoding unit B.
13 and the integer arithmetic unit 21 are connected.

The load / store unit 20 stores the operand value read from the register file A25, and the integer operation unit 21 stores the operand value read from the register file B26 and the shared register 27. The operation issued by the decoding unit A11 is stored in the load / store unit 20, and the operation issued by the decoding unit B24 is stored in the integer arithmetic unit 21.

Hereinafter, each arithmetic unit executes using an operation or an operand, and stores the result in a register, a memory or the like. In the load / store unit 20, the LOAD instruction of the instruction stream A is executed. Since the register numbers of the instruction write destination are R0 to R15, the data is fetched from the memory at the calculated memory address and stored in the register R5 in the shared register 27. The ADD instruction is executed in the integer arithmetic unit 21. Since the instruction stream B corresponds to the register file B26 and the register numbers of the write destinations are R16 to R31, the addition result is stored in the register R22 in the register file B26. Load store unit 20 and shared register 27
The write switch 28 is controlled so as to connect the integer arithmetic unit 21 and the register file B26. Each arithmetic unit clears the register number registered in the scoreboard 30 when the arithmetic operation is completed and the writing to the register is completed.

Next, another embodiment of the information processing apparatus according to the present invention will be described with reference to the drawings. FIG. 2 shows a configuration diagram of a register file of an information processing apparatus according to another embodiment of the present invention.

In FIG. 2, reference numerals 40 and 41 are decoding units for decoding instructions. Reference numerals 50, 51 and 52 are arithmetic units. The function of the arithmetic unit does not need to be particularly limited, and therefore detailed description will not be given. Reference numeral 57 is an operand switch for connecting the operands output from the register files 53, 54 and 55 to the arithmetic units 50, 51 and 52, and 53, 54 and 55 are register files of 3 ports of read 2 write 1. The register A53 of the register file is the decoding unit A40.
, And register B54 corresponds to decryption unit B41.

Shared register 55 corresponds to both decryption unit A40 and decryption unit B41. 50 is a write switch for connecting the operation result to the corresponding register, 58 is a read arbiter for deciding which data in the register file to read, and 59 is for deciding which of the results of the operation unit is written in the register. Write arbiter. The other parts of the configuration and the connection relationship are shown in FIG.

The operation of the information processing apparatus of the present embodiment constructed as above will be described below with reference to FIG. It should be noted that the same parts as those of the above-described operation will be omitted, and only different parts will be described.

First, regarding reading the register,
The decoding unit A40 sends a LOAD instruction (memory-to-register load instruction: MEM (R0 + R1) → R18), and the decoding unit B41 sends an ADD instruction (register-to-register addition instruction: R2).
+ R3 → R22) will be decoded. Since the read register numbers are all R0 to R15, it is necessary to prepare all data from the shared register 55.
However, since the shared register 55 has only two read ports, it cannot read all.

Therefore, the read arbiter 58 receives the register numbers to be read from the instruction decoding units 40 and 41, and if there is a read request for more than three types of registers from the shared register 55, the reading unit can be limited to two types. And the corresponding register is read from the shared register 55. At the same time, the read arbiter 58 controls the operand switch 57 so that the contents read from the shared register can be output to the corresponding arithmetic unit.

On the contrary, when writing to the register,
The decoding unit A40 issues a LOAD instruction (memory-to-register load instruction: MEM (R0 + R17) → R0), and the decoding unit B41 gives an ADD instruction (register-to-register addition instruction: R2).
+ R18 → R1) will be decoded. Since all the register numbers of the write registers are R0 to R15, it is necessary to write all the data in the shared register 55. However, since the shared register 55 has only one write port, it cannot write all.

Therefore, the write arbiter 59 receives the register number to be read from the arithmetic unit, and if there is a write request from the shared register 55 to two or more types of registers, it can be executed by the arithmetic unit so that the number can be limited to one. And the corresponding register in the shared register 55 is written. At the same time, the write arbiter 59 controls the write switch 56 so that the arithmetic unit can write to the shared register.

In this embodiment, two sets of register files have been described, but three or more register files may be used. Further, although the present embodiment has been described using a processor in which a plurality of instruction streams are executed in parallel at the same time, a single instruction stream is executed at the same time, but a processor having a plurality of register files may be used.

Further, in the present embodiment, the number of register files is 32, but there is no particular limitation, and there is no limitation on the number of shared registers. Further, it is not necessary to have a shared register as a general-purpose register.

[0049]

INDUSTRIAL APPLICABILITY As described above, the present invention can exert the following excellent effects. (1) By sharing a part of the register, the amount of hardware can be reduced and the cost can be reduced. (2) Since the same register can be accessed in each instruction stream, it has a high-speed communication function and high performance can be realized. (3) By providing the write and read arbiters for the registers, in addition to the effects of (1) and (2) above, the number of ports of the common register can be reduced and the hardware amount can be further reduced. (4) It is possible to freely use the case where the register is shared and the case where the register is not used, and it is possible to improve the performance.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an information processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a register in another embodiment of the present invention.

FIG. 3 is a block diagram of a conventional information processing apparatus

[Explanation of symbols]

 10 instruction fetch control unit 11, 13 decoding unit 12, 14 program counter (PC) 20 load store unit 21 integer arithmetic unit 22 floating point unit 23 operation switch 24 operand switch 25 register file A 26 register file B 27 shared register 28 Write switch 29 Data dependency check unit 30 Scoreboard

Claims (5)

[Claims] 1. An information processing apparatus having a plurality of register files, a part of which is shared. 2. A plurality of arithmetic units, a plurality of register files sharing a part thereof, and an operand switch for connecting the arithmetic units and the plurality of register files, wherein the operand switch is a data file from the register file. An information processing apparatus, which determines whether or not it is a shared portion according to a register number when reading out, and connects the arithmetic unit and the register file accordingly. 3. A plurality of arithmetic units, a plurality of register files sharing a part thereof, and an operand switch for connecting the arithmetic units and the plurality of register files, wherein the operand switch is a data file from the register file. An information processing apparatus, which determines whether or not it is a shared portion according to a register number when writing, and connects the arithmetic unit and the register file according to the determination. 4. A plurality of arithmetic units, a plurality of register files sharing a part thereof, an operand switch connecting the arithmetic units and the plurality of register files, and a register read arbiter, wherein the register read arbiter is When reading data from the register file, determine whether it is a shared part by register number, and if there is a read request more than the number of ports of the shared register, an instruction to execute within the range of the number of ports An information processing apparatus which controls issuing and connects the arithmetic unit and the register file to the operand switch. 5. A plurality of arithmetic units, a plurality of register files sharing a part thereof, an operand switch for connecting the arithmetic units and a plurality of register files, and a register write arbiter, wherein the register write arbiter comprises: When writing data from the arithmetic unit to the register file, it is judged whether or not it is a shared part by the register number, and if there is a write request more than the number of ports of the shared register, execute within the range of the number of ports. An information processing apparatus which controls the arithmetic unit so that the arithmetic unit and the register file can be connected to the operand switch.