JPH06338879A - Diversity receiver - Google Patents

Abstract

(57) [Abstract] [Purpose] In the diversity reception system, the signal determination circuit is integrated into a circuit and the power consumption is reduced. [Structure] The signal judgment is performed by detecting the amount of jitter contained in the signal before or after detection without using a reception level detector having a complicated circuit structure in the signal judgment circuit. [Effect] The hardware configuration can be downsized and the power consumption can be reduced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is used in digital communications. In particular, the present invention relates to a received signal quality determination technique in the diversity reception system.

[0002]

2. Description of the Related Art A conventional example will be described with reference to FIGS. FIG. 16 is a diagram showing a circuit for performing two-branch spatial diversity reception using a plurality of conventional double super-heterodyne demodulation circuits. FIG. 17 is a diagram showing a circuit for performing two-branch space diversity reception using a plurality of conventional direct conversion demodulation circuits. FIG. 18 is a diagram showing a circuit for performing time diversity reception using a conventional double super-heterodyne demodulation circuit. FIG. 19 is a diagram showing a circuit for performing time diversity reception using a conventional direct conversion demodulation circuit.

As shown in FIG. 16, in a reception demodulator 2 ₁ , a reception signal received by an antenna 1 ₁ is amplified by a high frequency amplifier 3, and two local oscillators 4 and 7, mixers 5 and 8 and a band pass filter are provided. Filters 6 and 9
After being converted into an intermediate frequency signal by, the signal is amplified by the intermediate frequency amplifier 10 and becomes an intermediate frequency signal 11. Further, the intermediate frequency signal 11 is detected by the detection circuit 12 to obtain the demodulator output 13 ₁ . This signal 13 ₁ is input to the spatial diversity reception processor 16. The reception signal received by the antenna 1 ₁ is also input to the reception level detector 15 to obtain the level output 14 ₁ . The level output 14 ₁ is input to the spatial diversity reception processor 16.
On the other hand, in the receiver demodulator 2 _2, the reception signal received by the antenna 1 ₂ performs the same operation as receiver demodulator 2 ₁ above, after obtaining the demodulator output 13 _2, and the level output 14 _2,
This signal is input to the spatial diversity reception processor 16. The spatial diversity reception processor 16 performs diversity reception processing using the demodulator outputs 13 ₁ and 13 ₂ and the level outputs 14 ₁ and 14 ₂ , and outputs a diversity output 17. Here, in the case of performing the selective combining process in the spatial diversity reception processor 16, the diversity reception process is performed using the two level outputs 14 ₁ and 14 ₂ , and the diversity output 17 is output. Here, in the case of performing selective combining processing in the spatial diversity reception processor 16, the two level outputs 14 ₁ and 14 ₂ are compared, and the demodulator outputs 13 ₁ and 13 ₂ corresponding to the demodulation corresponding to the higher level are demodulated. Diversity output 17 is obtained by selecting the unit output. Further, the clock reproduction circuit 18 reproduces the clock from the diversity output 17,
The code determiner 19 obtains the received data output 20 from the recovered clock and the diversity output.

As shown in FIG. 17, in the reception demodulator 21 ₁ , the reception signal received by the antenna 1 ₁ is amplified by the high frequency amplifier 3 and divided into an "I" channel signal and a "Q" channel signal. Mixers 23 ₁ and 23 ₂
Entered in. In this mixer, the local signal 22
And the "I" channel signal, the signal having a 90 ° phase difference from this local signal, and the "Q" channel signal are multiplied and then input to the channel filters 24 ₁ and 24 ₂ and the limiter amplifiers 25 ₁ and 25 ₂ . Further, the limiter amplifier outputs 26 ₁ and 26 ₂ output from the limiter amplifiers 25 ₁ and 25 ₂ are input to the detection circuit 27 and the demodulator output 2
Get 8 ₁ . The reception signal received by the antenna 1 ₁ is also input to the reception level detector 15, the level output 1
You get 4 ₁ . On the other hand, in the reception demodulator 21 ₂ , the antenna 1
_The received signal received at ₂ is operated in the same manner as the above reception demodulator 21 _1, and demodulator output 28 ₂ and level output 1
Get 4 ₂ . The spatial diversity reception processor 29 includes demodulator outputs 28 ₁ and 28 ₂ and level outputs 14 ₁ and 14 2.
₂ is used to perform diversity reception processing and output diversity output 30. Here, in the case of performing selective combining processing in the spatial diversity reception processor 29, the two level outputs 14 ₁ and 14 ₂ are compared, and the demodulator outputs 28 ₁ and 28 ₂ corresponding to the demodulator having the higher level are demodulated. Diversity output 30 is obtained by selecting the unit output. further,
This diversity output 3 in the clock recovery circuit 18
The clock is regenerated from 0, and the received data output 20 is obtained from the regenerated clock and the diversity output in the code decision unit 19.

As shown in FIG. 18, the reception level detector 15
The reception demodulator 2 ₁ having the same as that shown in FIG. The operation on the transmitting side is to transmit the same signal a plurality of times. The operation similar to that described with reference to FIG.
Obtain demodulated output 13 ₁ and the level output 14 _{1 1.} In the clock recovery circuit 18, this demodulator output 13
_The clock is regenerated from ₁ , and the code deciding unit 19 inputs the regenerated clock and the code deciding unit output signal obtained from the demodulator output to the time diversity reception processing unit 31. Further, the level output 14 ₁ is input to the time diversity reception processor 31. The time diversity reception processor 31 performs diversity reception processing using the code determination unit output signal and the level output 14 ₁ received this time and those received up to the previous time, and outputs the reception data output 20. Here, when the time diversity reception processing unit 31 performs selective combining processing, the level output received this time and the level outputs received up to the previous time stored in the memory in this time diversity reception processing unit Compared to the correspondence, performs the time diversity reception process of selecting the code decision unit output signal corresponding to the higher level output, further, after the end of this time diversity reception process,
This level output and this code determination device output signal are stored in the memory, and this code determination device output signal is output as the reception data output 20. By repeating the above operation, high quality signal transmission can be realized in the mobile communication transmission line with fading.

As shown in FIG. 19, the reception level detector 15
The reception demodulation circuit 2 ₁ having the same as that shown in FIG. In order to perform time diversity reception, the sender side
The same signal is transmitted multiple times. By the same operation as described with reference to FIG. 17, the reception demodulator 21 ₁ outputs the demodulator output 2
8 ₁ and level output 14 ₁ . The clock recovery circuit 18 recovers the clock from the demodulator output 28 ₁ , and the code determiner 19 inputs the recovered clock and the code determiner output signal obtained from the demodulator output to the time diversity reception processor 31. Also, level output 1
4 ₁ is input to the time diversity reception processor 31. The time diversity reception processing unit 31 performs diversity reception processing using the code decision unit output signal and the level output 14 ₁ received this time and those received up to the previous time,
The received data output 20 is output. Here, when the time diversity reception processor 31 performs the selective combining process, the same operation as that described with reference to FIG. 18 is performed.

[0007]

However, as described above, in order to perform space or time diversity reception capable of realizing high-quality signal transmission, a reception level detector is required, which complicates the circuit. Power consumption increases.

The present invention has been made in view of such a background, and in a space or time diversity reception circuit, space or time diversity reception in which the circuit complexity due to the reception level detector and the increase in power consumption are removed is eliminated. The purpose is to provide a machine.

[0009]

The present invention provides means for receiving a plurality of signals containing the same information, means for judging the quality of the plurality of received signals, and the reception according to the judgment result of the judging means. And a means for generating one reception output from the received signal.

Here, the feature of the present invention is that the judging means includes means for detecting the amount of jitter of the received signal, and means for giving priority to the one having a small amount of detected jitter. There is a place. The input of the detecting means may be an intermediate frequency signal or a demodulated baseband signal.

[0011]

By using the fact that jitter occurs in the intermediate frequency signal in the receiving demodulator and the output signal of the receiving demodulator due to fading or thermal noise, the diversity receiving circuit uses the intermediate frequency signal or receiving demodulation in the receiving demodulator. The quality of a plurality of diversity-received signals is judged by using the jitter of the output signal of the receiver. That is, the reception level is lowered to cause interference due to noise, which causes disturbances such as amplitude, pulse width, pulse position, and pulse interval, which are detected as jitter.

The jitter measuring device used for this purpose can be composed of a digital circuit. This facilitates integration into an integrated circuit and lowers power consumption.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of the first embodiment of the present invention.

According to the present invention, the reception demodulators 2 ₁ and 2 ₂ are provided as means for receiving two systems of signals containing the same information, and the signal determination circuit 50 is provided as means for determining the quality of the signals received by the two systems. The diversity receiver is provided with a spatial diversity reception processor 34 as means for generating one reception output from the received signal according to the judgment result of the signal judgment circuit 50.

Here, a feature of the present invention is that the signal determination circuit 50 includes means for detecting the amount of jitter of the received signal, and one having a small amount of detected jitter is superior. is there.

In the reception demodulator 2 ₁ which is a double superheterodyne demodulation circuit, the intermediate frequency signal 11 amplified by the intermediate frequency amplifier 10 is input to the detection circuit 12 to obtain the demodulator output 13 ₁ and the jitter detector 32. A jitter output 33 ₁ is obtained as input. On the other hand, the reception demodulator 2
_{In 2} as well, the same operation as that of the reception demodulator 2 ₁ is performed, and a demodulator output 13 ₂ and a jitter output 33 ₂ are obtained.
The demodulator outputs 13 ₁ and 13 ₂ and the jitter output 3
3 ₁ and 33 ₂ are input to the spatial diversity reception processing unit 34, diversity reception processing is performed, and diversity output 1
7 is output. Here, in the case of performing selective combining processing in the spatial diversity reception processor 34, the jitter amounts of the two jitter outputs 33 ₁ and 33 ₂ are compared, and the _one having the smaller jitter amount from the demodulator outputs 13 ₁ and 13 ₂ is compared. The demodulator output corresponding to is selected to obtain the diversity output 17. Further, the clock recovery circuit 18 recovers the clock from the diversity output 17, and the code judging unit 19 obtains the received data output 20 from the recovered clock and the diversity output.

Next, the operation of the jitter detector 32 will be described with reference to FIGS. FIG. 2 is a block diagram of the jitter detector 32. FIG. 3 is a diagram showing the intermediate frequency signal 11 and the detector input signal 53. FIG. 4 is a diagram showing the relationship between the jitter amount and shift register outputs 38 and 39.
FIG. 5 is a diagram showing the relationship between the shift register outputs 38 and 39, the outputs Q and Q ⁻ of the flip-flops 40 and 41, and the jitter output 43. FIG. 6 shows the jitter detector 32.
It is a figure which shows the simple structural example of.

FIG. 2 shows a digital circuit configuration of the above-mentioned jitter detector 32. Detector input signal 53 is delayed by clock source 55 and shift register 57 to obtain shift register outputs 38 and 39. The detector input signal 53 is the intermediate frequency signal 11 via the level determiner 56. The waveform shape at this time is shown in FIG. In the first embodiment of the present invention, as shown in FIG.
Intermediate frequency signal of ± αkHz centered on 5 kHz 11
Are input to the jitter detector 32. This is input to the level determiner 56 to obtain the detector input signal 53 as shown in FIG. The clock source 55 is a PLL (Phase L
ocked Loop) circuit, 455 ×
Generating a 10 kHz clock. This clock is 4
It can be arbitrarily set as 55 × nkHz (n is an integer: n ≧ 2), but n = 10 in the first embodiment of the present invention.

As shown in FIG. 4, the detector input signal 53
Is the shift register 5 according to the clock of the clock source 55.
Shift within 7. When there is no influence of the jitter, the shift register outputs 38 and 39 at the clock timing of the measuring instrument input signal 54 output from the frequency divider 58.
The state of 1 remains the same and does not change, but changes when it is affected by jitter. This shift register output 3
8 and 39 are flip-flops 40 and 4 respectively
1 to the D terminal and the measuring instrument input signal 54 to T
The jitter output 43 is obtained by inputting it to the terminal and inputting the respective outputs of the flip-flops 40 and 41 to the NAND circuit 42.

FIG. 5 shows the relationship between the shift register outputs 38 and 39, the outputs Q and Q ⁻ of the flip-flops 40 and 41, and the jitter output 43 at this time. here,
When the threshold value of the jitter value is θ _th , this flip-flop 40 detects a jitter amount of θ _th or more, and this flip-flop 41 detects a jitter amount of −θ _th or less. As a result, when the jitter amount is θ _th or more or −θ _th or less (when the jitter amount is large), the jitter output 43 is at the H level, and the jitter amount is θ _th or less and −θ _th.
In the above cases (when the amount of jitter is small), the jitter output 4
It can be seen that 3 becomes the L level. Further, as a result, the jitter amount can be measured by integrating the time when the jitter output 43 is at the H level.

The jitter detector 32 may have a simple structure shown in FIG. At this time, the detector input signal 5
Jitter output 43 is obtained by determining shift register outputs 38 and 39 for each input timing of 3. Jitter can be determined by determining the preceding signal at the rising timing of the next signal.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram of the second embodiment of the present invention. Figure 7 is a circuit that performs time diversity reception for illustrating the present invention the second embodiment in the receiver demodulator 2 ₁ is a double super heterodyne demodulation circuit. The reception demodulator 2 ₁ is similar to the reception demodulator 2 ₁ having the jitter detector 32 shown in FIG. Further, the operation on the transmitting side is to transmit the same signal, which has been conventionally used in the time diversity method, a plurality of times. The demodulator output 13 ₁ and the jitter output 33 ₁ are obtained by the operation already described in FIG. The clock recovery circuit 18 recovers the clock from the demodulator output 13 ₁ , and the code decision unit 1
9 this recovered clock and this demodulator output 13
_The code decision unit output signal obtained from ₁ is input to the time diversity reception processing unit 35. Also, this jitter output 33
₁ is input to the time diversity reception processor 35. The time diversity reception processing unit 35 performs diversity reception processing using the code determination unit output signal and the jitter output 33 ₁ received this time and those received up to the previous time, and outputs the reception data output 20. Here, when the time diversity reception processing unit 35 performs selective combining processing, the jitter output received this time and the jitter outputs received up to the previous time stored in the memory in the time diversity reception processing unit 35 are used. The time diversity reception process is performed to compare the bit correspondences and select the code determiner output signal corresponding to the one with the smaller jitter amount. Further, after the end of the time diversity reception process, the jitter amount and the code judging device output signal are stored in the memory, and the code judging device output signal is output as the reception data output 20.
High-quality signal transmission can be realized by repeating the above operation.

Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a block diagram of the third embodiment of the present invention. FIG. 9 shows the signals 26 ₁ and 26 ₂ and the demodulator output 28 ₁ . FIG. 8 is a circuit for performing a two-branch spatial diversity reception for explaining the third embodiment of the present invention in the direct conversion demodulation circuit.
In receiver demodulator 21 _1, the limiter amplifier output 26 ₁ of the "I" channel signal, obtained with the inputted obtain demodulated output 28 ₁ to the detection circuit 27 is inputted to the jitter detector 32 jitter output 33 _1. As shown in FIG. 9, a signal 26 ₁ (α is a binary FSK) that is an input to the jitter detector 32.
Frequency deviation of α ≧ 0) is a baseband signal. At this time, the clock of the clock source 55 is (n / α). In the third embodiment of the present invention, n = 10. On the other hand, the reception demodulator 21 ₂ also performs the same operation as that of the reception demodulator 21 _1, and the demodulator output 28 ₂ and the jitter output 33
_{Get 2} The demodulator outputs 28 ₁ and 28 ₂ and the jitter outputs 33 ₁ and 33 ₂ are supplied to the spatial diversity reception processor 36.
To perform diversity reception processing and output a diversity output 30. Here, in the case of performing selective combining processing in the spatial diversity reception processor 36, the jitter amounts of the two jitter outputs 33 ₁ and 33 ₂ are compared,
From the demodulator outputs 28 ₁ and 28 ₂ , the demodulator output 28 ₁ or 28 ₂ corresponding to the one having the smaller amount of jitter is selected to obtain the diversity output 30. Further, the clock recovery circuit 18 recovers the clock from the diversity output 30, and the code judging unit 19 obtains the received data output 20 from the recovered clock and the diversity output 30. Also, by using the limiter amplifier output 26 ₂ of the “Q” channel signal, it is possible to obtain the reception data output 20 similar to that described above.

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 10 is a block diagram of the fourth embodiment of the present invention. FIG. 10 shows a circuit for performing time diversity reception for explaining the fourth embodiment of the present invention in the direct conversion demodulation circuit. The reception demodulator 21 ₁ is similar to the reception demodulator 21 ₁ having the jitter detector 32 shown in FIG. Further, the operation on the transmitting side is to transmit the same signal a plurality of times, which has been conventionally used in the time diversity receiving system.

A demodulator output 28 ₁ and a jitter output 33 ₁ are obtained by the same operation as described with reference to FIG. The clock recovery circuit 18 recovers the clock from the demodulator output 28 ₁ , and the code determiner 19 inputs the recovered clock and the code determiner output signal obtained from the demodulator output to the time diversity reception processor 37. The jitter output 33 ₁ is also input to the time diversity reception processor 37. In this time diversity reception processor 37,
Code decision device output signal and jitter output 33 received this time
₁ and the data received up to the previous time are used for diversity reception processing, and the reception data output 20 is output. Here, when the time diversity reception processing unit 37 performs selective combining processing, the jitter output received this time,
This time diversity reception is performed by comparing the jitter outputs 33 ₁ received up to the previous time stored in the memory of the time diversity reception processing unit 37 in a bit-corresponding manner and selecting the code decision unit output signal corresponding to the one having the smaller jitter amount. Perform processing. Further, after the end of the time diversity reception process, the jitter amount and the code judging device output signal are stored in the memory, and the code judging device output signal is output as the reception data output 20. High-quality signal transmission can be realized by repeating the above operation. Also, by using the limiter amplifier output 26 ₂ of the “Q” channel signal, it is possible to obtain the reception data output 20 similar to that described above.

Next, a fifth embodiment of the present invention will be described with reference to FIGS. 11 and 12. FIG. 11 is a block diagram of the fifth embodiment of the present invention. FIG. 12 is a diagram showing a detector input signal 53 of the jitter detector 32 in the fifth embodiment of the present invention. FIG. 11 is a circuit for performing two-branch space diversity reception for explaining the fifth embodiment of the present invention in the double super heterodyne demodulation circuit. In the fifth embodiment of the present invention, the demodulator output 13 ₁ , which is the demodulated baseband signal, is used as the input of the jitter detector 32. The waveform at this time is shown in FIG. At the zero crossing point of the demodulator output 13 ₁ , the level determiner 56 produces the detector input signal 53. At this time, the clock of the clock source 55 is (n / bit rate). In the fifth embodiment of the present invention, n = 10. Here, jitter detection can be performed when "1" and "0" are alternately consecutive. This control is performed by the spatial diversity reception processor 34.

In the reception demodulator 2 ₁ , the demodulator output 13 ₁ output from the detection circuit 12 is input to the spatial diversity reception processor 34 and the jitter detector 32.
To obtain the jitter output 33 ₁ . On the other hand, the reception demodulator 2 ₂ also performs the same operation as the reception demodulator 2 ₁ to obtain the jitter output 33 ₂ . Next, this demodulator output 1
The diversity outputs 3 ₁ and 13 ₂ and the jitter outputs 33 ₁ and 33 ₂ are input to the spatial diversity reception processor 34, and the diversity reception processing is performed to obtain the diversity output 17. Here, the space diversity reception processor 34 operates similarly to the first embodiment of the present invention. Further, the clock recovery circuit 18 recovers the clock from the diversity output 17, and the code determiner 19 obtains the received data output 20 from the recovered clock and the diversity output 17.

Next, a sixth embodiment of the present invention will be described with reference to FIG. FIG. 13 is a block diagram of the sixth embodiment of the present invention. FIG. 13 is a circuit for performing time diversity reception in the double super-heterodyne demodulation circuit for explaining the sixth embodiment of the present invention. This reception demodulator 2
₁ is the same as the reception demodulator 2 ₁ having the jitter detector 32 shown in FIG. Further, the operation on the transmitting side is to transmit the same signal a plurality of times, which is the same as that used in the conventional time diversity receiving system. By the same operation as described in FIG. 11, the demodulator output 13 ₁ and the jitter output 3
You get 3 ₁ . The clock recovery circuit 18 recovers the clock from the demodulator output 13 ₁ , and the code determiner 19 inputs the recovered clock and the code determiner output signal obtained from the demodulator output 13 ₁ to the time diversity reception processor 35. . Here, the time diversity reception processor 35 performs the same operation as that described in the second embodiment of the present invention to obtain the reception data output 20. High-quality signal transmission can be realized by repeating the above operation.

Next, a seventh embodiment of the present invention will be described with reference to FIG. FIG. 14 is a block diagram of the seventh embodiment of the present invention. FIG. 14 is a circuit for performing two-branch spatial diversity reception for explaining the seventh embodiment of the present invention in the direct conversion demodulation circuit.

In the reception demodulator 21 ₁ , the detection circuit 27
The demodulator output 28 ₁ output from the above is input to the spatial diversity reception processor 36, and is input to the jitter detector 32 to obtain the jitter output 33 ₁ . Returning to FIG. 9, the demodulator output 28 ₁ is as shown in FIG. Therefore, the level determiner 56 detects the detector input signal 53 at the bit change point.
To occur. The clock of the clock source 55 at this time is (n / bit rate). In the seventh embodiment of the present invention, n
= 10. Here, jitter detection can be performed when "1" and "0" are alternately consecutive. This control is performed by the spatial diversity reception processor 36. On the other hand, the reception demodulator 21 ₂ also performs the same operation as the reception demodulator 21 ₁ to obtain the jitter output 33 ₂ . Next, the demodulator outputs 28 ₁ and 28 ₂ and the jitter outputs 33 ₁ and 33 ₂ are input to the spatial diversity reception processing unit 36, and diversity reception processing is performed to obtain the diversity output 30. The space diversity reception processor 36 performs the same operation as that of the third embodiment of the present invention. Furthermore, the clock recovery circuit 18
At, the clock is regenerated from the diversity output 30, and at the code decision unit 19, the received data output 20 is obtained from the regenerated clock and the diversity output.

Next, an eighth embodiment of the present invention will be described with reference to FIG. FIG. 15 is a block diagram of the eighth embodiment of the present invention. FIG. 15 shows a circuit for performing time diversity reception in the direct conversion demodulation circuit for explaining the eighth embodiment of the present invention. The reception demodulator 21 ₁ is the same as the reception demodulator 21 ₁ having the jitter detector 32 shown in FIG. In addition, the operation on the transmitting side is to transmit the same signal a plurality of times, which is the same as that used in the time diversity receiving system in the related art.

The demodulator output 28 ₁ and the jitter output 33 ₁ are obtained by the same operation as described with reference to FIG. The clock recovery circuit 18 recovers the clock from the demodulator output 28 ₁ , and the code determiner 19 inputs the recovered clock and the code determiner output signal obtained from the demodulator output 28 ₁ to the time diversity reception processor 37. . Here, the time diversity reception processor 35 performs the same operation as that described in the fourth embodiment of the present invention to obtain the reception data output 20. By repeating the above operation,
High quality signal transmission can be realized.

In the first to eighth embodiments of the present invention, the case of the receiver performing the space diversity or the time diversity reception has been described as an example, but other diversity reception such as frequency diversity, polarization diversity, angle diversity or the like is performed. The same can be implemented in the receiver.

[0034]

As described above, according to the present invention,
In a space or time diversity receiver, the quality of the signal is judged by detecting the amount of jitter of the signal without using the reception level detector, and the jitter detector used for this is a circuit like a reception level detector. Without complexity,
Since it is composed of a digital circuit, it can be easily integrated into an IC and low power consumption can be achieved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a jitter detector.

FIG. 3 is a diagram showing an intermediate frequency signal and a detector input signal.

FIG. 4 is a diagram showing a relationship between a jitter amount and a shift register output.

FIG. 5 is a diagram showing a relationship among a shift register output, a flip-flop output, and a jitter output.

FIG. 6 is a diagram showing a simple configuration example of a jitter detector.

FIG. 7 is a block diagram of a second embodiment of the present invention.

FIG. 8 is a block diagram of the third embodiment of the present invention.

FIG. 9 shows I-channel and Q-channel signals and demodulator output.

FIG. 10 is a block diagram of a fourth embodiment of the present invention.

FIG. 11 is a block diagram of the fifth embodiment of the present invention.

FIG. 12 is a diagram showing a detector input signal of a jitter detector in the fifth embodiment of the present invention.

FIG. 13 is a block diagram of a sixth embodiment of the present invention.

FIG. 14 is a block diagram of a seventh embodiment of the present invention.

FIG. 15 is a block diagram of an eighth embodiment of the present invention.

FIG. 16 is a diagram showing a circuit for performing two-branch spatial diversity reception using a plurality of double super-heterodyne demodulation circuits of a conventional example.

FIG. 17 is a diagram showing a circuit for performing two-branch spatial diversity reception using a plurality of direct conversion demodulation circuits of a conventional example.

FIG. 18 is a diagram showing a circuit for performing time diversity reception using a conventional double super-heterodyne demodulation circuit.

FIG. 19 is a diagram showing a circuit for performing time diversity reception using a conventional direct conversion demodulation circuit.

[Explanation of symbols]

1 ₁ 1 ₂ Antenna 2 ₁ 2 ₂ Reception demodulator 3 High frequency amplifier 4 7 Local oscillator 5 8 Mixer 6 9 Band pass filter 10 Intermediate frequency amplifier 11 Intermediate frequency signal 12 27 Detection circuit 13 ₁ 13 ₂ Demodulator output 14 ₁ , 14 ₂ Level output 15 Reception level detector 16, 29, 34, 36 Spatial diversity reception processor 17 Diversity output 18 Clock recovery circuit 19 Code judger 20 Received data output 21 ₁ , 21 ₂ Reception demodulator 22 Local Signal 23 ₁ , 23 ₂ Mixer 24 ₁ , 24 ₂ Channel Filter 25 ₁ , 25 ₂ Limiter Amplifier 26 ₁ , 26 ₂ Limiter Amplifier Output 28 ₁ , 28 ₂ Demodulator Output 30 Diversity Output 31, 35, 37 Time Diversity Reception Processor 32 Jitter detector 33 ₁ , 33 ₂ , 43 Jitter output 38, 39 system Shift register output 40, 41 Flip-flop 42 NAND circuit 43 Jitter output 50 Signal determination circuit 53 Detector input signal 54 Measuring instrument input signal 55 Clock source 56 Level determiner 57 Shift register 58 Divider

Claims (3)

[Claims] 1. A means for receiving a plurality of signals containing the same information, and a means for judging the quality of the plurality of received signals,
In a diversity receiver having means for generating one reception output from the received signal according to the judgment result of the judging means, the judging means detects the jitter amount of the received signal. A diversity receiver characterized in that it is a means for predominantly having a small amount of detected jitter. 2. A diversity receiver according to claim 1, wherein the input of the detecting means is an intermediate frequency signal. 3. The diversity receiver according to claim 1, wherein the input of the detecting means is a demodulated baseband signal.