JPH06334168A - Semiconductor element - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide an optical semiconductor device which can be monolithically integrated with a Si electronic device by epitaxially growing a III-V mixed crystal semiconductor on a Si substrate. [Structure] A Si-MOS-FET is integrated on a Si substrate crystal with a cladding layer lattice-matched GaNP, an active layer laser diode consisting of a GaNP / GaNAs stress-compensated superlattice. In addition, a pin photodiode having a GaNP / GaNAs stress compensation type superlattice light absorption layer and a Si-MOS-FET are also integrated on the crystal of the same substrate. These optical semiconductor elements are connected by an optical waveguide provided in a Si substrate crystal. According to the present invention, a III-V mixed crystal semiconductor can be epitaxially grown on a Si substrate without causing misfit dislocations, and a semiconductor device that can be monolithically integrated with a Si electronic device is provided. Can do OEIC
Can be applied to.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an optical semiconductor device which can be integrated with a Si electronic device.

[0002]

2. Description of the Related Art Semiconductor technology has been developed to the present day centering on Si. Transistor to IC (Integrated Circui
t) and VLSI (Very Large Scale Integrated-circuit), the scale of integration is increasing, and it is expected that the scale of integration will continue to increase. However, with the increase in the scale of integration, there is a concern that the operation speed is limited due to the wiring delay of electric signals. As a countermeasure against this, attention has been paid to signal connection by light, and monolithic integration of Si electronic devices and III-V compound semiconductor optical devices is positioned as an important basic technology for realizing this.

The following two means are mainly studied as means for forming a III-V group compound semiconductor optical device on a Si substrate. One is the so-called super-heteroepitaxy method in which a III-V group compound semiconductor such as GaAs or InP having a different lattice constant is epitaxially grown on a Si substrate and an AlGaAs-based or InGaAsP-based optical semiconductor device is formed thereon. . (For example, Ed.HCChoi, R.Hull, H.Ishikawa and RJNemani
ch, "Heteroepitaxy on Silicon: Fundamentals, Struc
ture and Devices ", Mater. Res. Soc. Pro. Vol.116 (M
ater. Res. Soc., Pittsburgh, 1988)) The other is G
This is a direct bonding method in which an optical semiconductor element previously created on an aAs or InP substrate is bonded onto a Si substrate. (YHLo, R.Bha
t, DMHwang, C. Chua and C.-H. Lin, Appl. Phys. Le
tt. Vol. 62 pp.1038-1040, 1993) Until today, as materials for III-V compound semiconductor optical devices,
For example, HCCssey, Jr. and MB Panish, "Heterostr
ucture Lasers PartB "(Academic Press, New York, 197
8) As described in pp.8-9, group III atoms are Al, Ga, I
Binary compound semiconductors in which n, V group atoms are composed of P, As, Sb and mixed crystal semiconductors composed of them have been used for a long time.
In recent years, GaNP (J.
N.Baillargeon, KYCheng, GEHofler, PJ Pearch,
and KCHsieh, Appl. Phys. Lett. Vol. 60 pp.2540-
2542, 1992) and GaNAs (M. Weyers, M. Sao and H. Ando,
Jpn.J. Appl. Phys. Vol. 31 pp. L853-L855, 1992)
Now that N-based mixed crystal semiconductors can be created, the range of material selection has expanded. An example of epitaxially growing an N-based mixed crystal semiconductor on a Si substrate is disclosed in Japanese Patent Application Laid-Open No. 1-211912. When actually applying N-based mixed crystal semiconductors to semiconductor elements such as laser diodes, it is necessary to calculate the band gap size and the amount of lattice strain to design and create a multilayer structure. Due to the extremely large electronegativity of N in a mixed crystal semiconductor, a very large bowing occurs in the bandgap, and special considerations that are not found in conventional mixed crystal semiconductors are necessary when designing a bandgap of a multilayer structure.
However, in the growth example of the N-based mixed crystal semiconductor described above, only a single epitaxial layer is formed on the substrate crystal, and there is no example in which a multilayer structure is formed and applied to a semiconductor element.

[0004]

In both the superheteroepitaxy method and the direct junction method, the lattice constant of the material forming the optical semiconductor element is larger than that of Si (4).
% Or more), there is a problem that misfit dislocations occur in the crystal near the interface between Si and the III-V compound semiconductor. Further, there is a problem that dislocations generated during the cooling process after the high temperature process of epitaxial growth or bonding move and multiply due to the difference in thermal expansion coefficient between Si and the III-V group compound semiconductor. Therefore, there is a problem in the characteristics and device life of the created optical semiconductor device.
Monolithic integration of group IV compound semiconductor optical devices has not yet been put to practical use.

An object of the present invention is to provide an optical semiconductor device which can be monolithically integrated with a Si electronic device by epitaxially growing a III-V mixed crystal semiconductor on a Si substrate.

[0006]

The above object is achieved by keeping the lattice strain of each semiconductor layer constituting an optical semiconductor element within a critical strain amount at which misfit dislocations occur in the entire temperature region of the fabrication process. . When the total thickness of the strained layer exceeds the critical thickness, stress compensation is performed, and the material for the layer with tensile strain is N-based mixed crystal semiconductor AlGaInNPAsSb.
Should be used. The film thickness of the AlGaInNPAsSb strained layer is preferably 2 nm or more due to difficulty in fabrication, and the lattice mismatch is preferably within ± 4% due to the critical film thickness. For example GaN (x) As (1-x)
In the case of, the range of the mixed crystal composition x is 0.02 <x <0.36.

In the following, optoelectronic integrated circuits (Optoelectronic
This section describes how to create the components that make up the Integrated Circuit (OEIC).

The light emitting element is a laser diode.
e: LD), the active layer has a direct transition type N-based mixed crystal semiconductor A.
A strained layer of lGaInNPAsSb is used. When the total thickness of the strained layer is grown to exceed the critical thickness, the layer having tensile strain is laminated on the layer having compressive strain, or the layer having compressive strain has compressive strain. Layers are laminated to compensate for stress. In order to improve the carrier injection efficiency, Al (a) Ga (1-a) N (x) P (1-x) (0 ≦ a ≦ 1, 0 ≦ x ≦ 1) or Si is used in the active layer.
It suffices that the guide layers made of, etc. When the oscillation wavelength is longer than the band gap of Si, Si can be used as the material for the cladding layer and the guide layer. Further, when the laser diode is a surface-emitting type, GaP, AlP, GaNP, Al as shown in FIG.
A II-VI group semiconductor such as NP, Si, or ZnS is used.

The light receiving element is a photodiode (Photo-Diod
e: PD), the N-type mixed crystal semiconductor AlGaInNPAsSb is used as the material of the light absorption layer in order to reduce the band gap and widen the light receiving wavelength region.
Should be used. When the photodiode is an avalanche photodiode, Si, which has a large difference in ionization coefficient between electrons and holes, may be used as the material of the multiplication layer.

The electrode contact layer has a narrow bandgap of 0.5 eV or less or a semimetal N-based mixed crystal semiconductor AlGaInNPAsSb.
A high-quality ohmic electrode can be produced by using. still,
The N-based mixed crystal semiconductor electrode contact layer is widely applied not only to optical devices but also to electronic devices. Si is also used for the electrode contact layer regardless of the form of single crystal or polycrystal. When the wavelength of light used in the optical semiconductor element is transparent to Si, Si becomes a transparent electrode.

These N-based mixed crystal semiconductors AlGaInNPAsSb are
High quality crystals can be obtained by epitaxial growth without activated misfit dislocations using activated nitrogen as a source of N in a high vacuum of 0 ^ -2 Torr or less. AlGa
As a p-type impurity of InNPAsSb, C.Be, and as an n-type impurity
Si and Sn are used.

When the wavelength of light used in an optical semiconductor element used in an optoelectronic integrated circuit is transparent to Si, Si
Can be used to create optical circuits, even in Si substrates.
The optical circuit can be formed in a layered structure, and when a signal is sent to multiple points like a clock signal, it is not necessary to form a waveguide in the plane of the layered structure.

[0013]

[Function] The problem that dislocations occur due to the fact that the lattice constant of the material of the optical semiconductor element is greatly different from the lattice constant of Si is a critical film in which the film thickness of the semiconductor layer forming the optical semiconductor element is misfit It will be solved by suppressing within the thickness. Figure 3 shows the relationship between the lattice mismatch and the critical thickness calculated by Matthews' theory. From the figure, it is seen that the layer having a lattice mismatch of 1% has a thickness of 10 nm, and the layer having a lattice mismatch of 4% has a thickness of 2 nm.
It can be seen that the critical film thickness is m. For example, GaAs has about 4
Since there is a lattice mismatch of%, the critical film thickness is 2 nm, and it is not possible to grow a thick layer of 2 nm or more without generating dislocations. In addition, the conventional group III atom is Al, Ga, In, V group atom is P,
GaAs (0.5) P (0.5) is the mixed crystal semiconductor composed of As and Sb that has the direct transition type and the lattice constant closest to that of Si.
It can be seen that the lattice mismatch degree is 2% and the critical film thickness is 4 nm. When the total thickness of the strained layer is grown to exceed the critical thickness, if a layer having tensile strain is laminated on a layer having compressive strain to compensate the stress and keep the total strain within the critical strain. Known to be good. However, conventional mixed crystal semiconductors in which the group III atoms are Al, Ga, In, and the group V atoms are P, As, and Sb all have a larger lattice constant than Si, so that a layer having tensile strain cannot be formed. Since the N-based mixed crystal semiconductor AlGaInNPAsSb that can be produced in recent years has a lattice constant smaller than that of Si by selecting the mixed crystal composition, stress compensation can be performed by using this as a tensile strain layer. The superlattice layer in which the stress is compensated and the total strain is 0 is substantially lattice-matched with the Si substrate, so that no misfit dislocations occur.

In the N-based mixed crystal semiconductor, a large bowing occurs in the band gap due to the extremely large electronegativity of N. For example, when N is added to GaAs and GaP, their band gap does not increase toward 3.4 eV of GaN as in a conventional mixed crystal semiconductor, but rather decreases. Si
GaN (0.19) As (0.81) that is lattice-matched with
Next becomes semimetal. Figure 4 shows the relationship between the lattice mismatch of GaNAs, GaNP, AlNAs, AlNP and GaPAS with the Si substrate and the band gap. For example, GaP (0.
25) As (0.75) and AlN (0.05) P with 5 nm lattice mismatch of -0.6%
When (0.95) is laminated alternately to form a superlattice layer, the total strain becomes 0 and the band gap becomes effectively 2.0 eV. GaN (0.1) As (0.9) with a lattice mismatch of + 2% at 3 nm
And a superlattice layer of 3 nm with a lattice mismatch of -2% and GaN (0.14) P (0.86) alternately laminated to give a total strain of 0.5e is effectively 0.5e
Has a bandgap of V. As described above, by selecting the type of semiconductor that constitutes the superlattice, the bandgap can be freely designed within the range of 2 to 0 eV while keeping the total strain at 0. Although Si is used for the substrate crystal in the above description, a GaP or AlP substrate crystal having a lattice constant substantially equal to that of Si can be used to similarly create a superlattice layer in which the stress is compensated and the total strain is zero.

Next, the difference in thermal expansion coefficient between Si and the III-V compound semiconductor will be considered. The coefficient of thermal expansion of Si is 2.6 × 10 ^
-6 / ℃, GaAs has a thermal expansion coefficient of 6.0 × 10 ^ -6 / ℃, so 630 ℃
When it is cooled from the high temperature process to room temperature of 30 ℃, 0.2% of thermal strain occurs. From FIG. 3, the critical film thickness is estimated to be 80 nm. Matthe
Although the theory of ws tends to underestimate the critical film thickness when the degree of lattice mismatch is small, this thermal strain still poses a problem in producing a device having a thickness of several μm. When growing a layer having a film thickness of 0.1 μm or more, dislocation hardly occurs if the lattice mismatch degree is kept within ± 0.1%. For that purpose, as shown in FIG. 5, the composition of the layer may be selected so that it can be lattice-matched with Si, and the temperature for lattice-matching may be set between the room temperature and the high temperature process. The layer having a film thickness of 0.1 μm or more as used herein may be either a layer having a single composition or a superlattice layer in which the stress is compensated and the total strain is 0.

[0016]

Embodiments (Embodiment 1) In this embodiment, a MOS-FET (Metal-
Si such as Oxide-Semiconductor Field-Effect-Transistor)
10,000 electronic devices, 100 surface-emitting laser diodes of III-V mixed crystal semiconductors, 100 devices of pin photodiodes of III-V mixed crystal semiconductors are integrated on the same Si substrate to create an optoelectronic integrated circuit OEIC. Created. Figure 1 shows the structural cross section of the OEIC. FIG. 1 (a) shows a surface emitting laser diode integrated with a MOS-FET, and FIG. 1 (b) shows a pin photodiode integrated with a MOS-FET and RESISTOR. In this OEIC, the electric circuit is formed on the surface of the Si substrate and the optical circuit is formed in the Si substrate, and the electric circuit and the optical circuit are spatially separated. Since the electric circuit and the optical circuit are spatially separated, the electric wiring and the optical wiring can be independently performed, so that the degree of freedom of wiring is large.

Here, a method for producing this OEIC will be described. First, a method of making an optical circuit will be described. In Figure 1, 1
Reference numeral 1 is an n-type (111) Si substrate, on which an n-type Si layer 12 (n = 1 × 10 ^ 18cm ^ -3, d = 1 μm) which will be a clad layer of a waveguide, and an n-type which will be a core layer The Si layer 13 (n = 1 × 10 ^ 15 cm ^ -3, d = 1 μm) is epitaxially grown. In order to create a waveguide in the plane of the core layer, P is ion-implanted so that n = 1 × 10 ^ 18 cm ^ -3 on both sides of the core region to form the cladding. After forming the in-plane waveguide, the n-type Si layer 13 (n = 1 × 10 ^ 18cm ^-
(3, d = 3 μm) is regrown to form a three-dimensional waveguide.
When a signal is sent to multiple points like a clock signal, it is not necessary to form a waveguide in the core layer surface. Further, in the present embodiment, the core layer has one stage, but it can be multi-staged and the optical circuit can be freely prepared.

Next, as a preparation for forming an electronic element, ion implantation is performed on the Si substrate on which the waveguide is formed. As shown in Fig. 1, B is implanted for isolation to create a high-resistivity p-type region, and P is ion-implanted to contact the n-type III-V optical semiconductor device contact layer, MOS-FET. Source and drain electrodes, resistors, etc. are formed.

Next, a group III-V optical semiconductor element portion is formed by selective growth. First, the surface emitting laser diode will be described. The surface emitting laser diode has a diameter of 5 μm. In FIG. 1 (a), 15 is an n-type GaN (0.03) P (0.97) buffer layer (n = 1 × 10 ^ 18cm ^ -3, d = 0.1 μm), 16 is an n-type semiconductor multilayer mirror (n = 1 × 10 ^ 18cm ^ -3), 17 is n-type GaN (0.03) P
(0.97) clad layer (n = 1 × 10 ^ 18cm ^ -3), 18 is an undoped active layer, 19 is a p-type GaN (0.03) P (0.97) clad layer (p = 1 ×
10 ^ 18cm ^ -3), 20 is a p-type semiconductor multilayer mirror (p = 1 × 10 ^ 1
9 cm ^ -3) and 21 are semi-metal GaN (0.19) As (0.81) contact layers (d = 0.1 μm). A stress-compensated strained superlattice layer whose bandgap can be freely set in the range of 2 to 0 eV is used for the active layer, but since the material of the optical circuit, Si (Eg = 1.1 eV), must be transparent, Effectively 0.8e in the example
GaN (0.07) P (0.93) with a 2nm lattice mismatch of -1% and a 1nm lattice mismatch with a bandgap of V (wavelength: 1.55μm)
A stress-compensated superlattice layer was used in which + 2% GaN (0.10) As (0.90) was alternately laminated. The thickness was set to d = 100 nm by stacking 33 cycles so that the thickness was about 1/4 wavelength in the semiconductor. Also, in order to realize a one-wavelength resonator, the thickness of the clad layer so that the wavelength between the mirrors is one wavelength is 3/8 wavelength in the semiconductor on both sides. The semiconductor multilayer mirror is a high-refractive-index GaN layer with a thickness of 1/4 wavelength
(0.03) P (0.97) layer and 1/4 wavelength thick low refractive index Al in semiconductor
It is configured by alternately stacking N (0.04) P (0.96) layers. The number of laminations of the mirror layer was 20 in order to make the reflectance 99% or more. The high refractive index layer and the low refractive index layer may be alternately laminated as the mirror layer, and therefore, for example, the material shown in FIG. 2 may be used. The p-type mirror layer has p = 1 × to reduce the resistivity.
Doped with high concentration of 10 ^ 19cm ^ -3. Then pi
The n photodiode will be described. The diameter of the pin photodiode is 5 μm. In FIG. 1 (b), 22 is n-type GaN
(0.03) P (0.97) layer (n = 2 × 10 ^ 18cm ^ -3, d = 1.0μm), 23 is a 2nm GaN with a lattice mismatch of -2% with an effective bandgap of 0.5eV. (0.14) P (0.86) and 2nm lattice mismatch degree is + 2%
Non-doped stress-compensated superlattice layers (n = 1 × 10 ^ 15cm ^ -3, d = 0.5μm) with alternating layers of GaN (0.10) As (0.90), 24 for p
Type GaN (0.03) P (0.97) layer (p = 2 × 10 ^ 18cm ^ -3, d = 1.0μ
m) and 25 are semi-metal Al (0.50) Ga (0.50) N (0.19) As (0.81) contact layers (d = 0.1 μm). The layers composing the light emitting laser diode and the pin photodiode are 1 × 10 ^ -6 Torr continuously by using the gas source molecular beam epitaxy device.
The crystals were grown in a high vacuum. In the growth of Si, polycrystalline Si was used as a raw material and Sb was used as a raw material for the n-type dopant. In the growth of the III-V semiconductor layer, a metal was used as a Group III source, phosphine and arsine were used as P and As sources, and N, which was a nitrogen molecule activated by rf plasma, was used as a N source. . The raw materials for the n-type dopant and p-type dopant are
Si and C (neopentane) were used. The growth temperature is 500 ° C, and all stress-compensated superlattice layers and layers of single composition
It is designed to lattice match with Si at 300 ° C. As a result, the lattice matching with Si can be kept within 0.1% in the whole temperature range of the fabrication process.

In this way, the S
i-wafer, surface protection of III-V optical semiconductor devices and MOS-FE
A SiO2 oxide film for the gate of T is formed. Next, multilayer wiring is performed using Al and SiO 2 on the created optical semiconductor element and electronic element to create an electric circuit.

Finally, in order to form a mirror in the optical circuit, a groove is formed from a 45 ° direction with a halogen-based reactive ion beam to complete the OEIC. This groove may be formed from the direction easy to form from the front surface or the back surface of the substrate.

Next, the operating principle of this OEIC will be described. When voltage is applied to the gate electrode of the laser diode driving MOS-FET, current is injected into the surface emitting laser diode,
Laser oscillation. Laser light is radiated into the Si substrate and 45 °
It is totally reflected by the mirror and guided to the waveguide. The guided laser light is totally reflected again by the 45 ° mirror and guided to the photodiode. The detected laser light is converted into a current by the photodiode, this current is converted into a voltage by RESISTOR, and this voltage is amplified by the MOS-FET, and finally output to the source electrode.

(Embodiment 2) FIG. 6 shows an OEIC to which the present invention is applied.
The structural sectional view of is shown. Light emitting part in which Si-MOS FET and edge emitting laser diode are integrated Figure 6 (a) and Si-MOS FET and RES
Light-receiving part in which ISTOR and avalanche photodiode are integrated FIG. 6 (b) is formed on a different substrate crystal.
Connected by optical fiber and used for signal transmission between IC chips. First, the creation method will be described. Ion implantation is performed on a p-type (511) Si substrate in preparation for forming an electronic element. As shown in Fig. 6, P is injected for isolation to create a high resistivity n-type region, and B is ion-implanted to contact the contact layer of a P-type III-V optical semiconductor device, MOS-FET.
Source and drain electrodes, resistors, etc. are formed. next,
A III-V group optical semiconductor element portion is formed by selective growth. First, the structure of the edge emitting laser diode will be described. In FIG. 6 (a), 41 is a p-type GaN (0.03) P (0.97) buffer layer (p = 1 × 10 ^ 18 cm ^ -3, d = 0.1 μm), and 42 and 46 are p-type and n-type, respectively. AlN (0.04) P (0.96) clad layer (p, n = 1 × 1
0 ^ 18cm ^ -3, d = 1.0 μm), 43 and 45 are p-type and n-type, respectively.
-Type AlGaNP guide layer (p, n = 5 × 10 ^ 17cm ^ -3, d = 0.03μm)
The so-called GRIN (Graded-Refractive-Index) in which the bandgap is changed parabolically by changing the Al composition at
Structure 44 is GaN with 0% lattice mismatch of 10 nm
(0.03) P (0.97) barrier layer and G with a lattice mismatch of + 2% at 1.5 nm
A stress-compensated non-doped strained quantum well active layer in which aN (0.10) As (0.90) well layers are alternately stacked for 2.5 periods (wavelength: 1.
24 μm), 47 is Si contact layer (n = 1 × 10 ^ 19 cm ^ -3, d = 0.1
μm). In order to form a resonator, etching is performed from the vertical direction with a halogen-based reactive ion beam to form a mirror, and a laser diode is completed. Resonator length is 30
It was set to 0 μm. Next, the structure of the avalanche photodiode will be described. The diameter of the avalanche photodiode is 10 μm. In FIG. 6 (b), 48 is p-type Ga
P buffer layer (p = 2 × 10 ^ 18, d = 0.01 μm), 49 is p-type GaN (0.
03) P (0.97) buffer layer (p = 2 × 10 ^ 18cm ^ -3, d = 1.0μm),
50 has an effective lattice mismatch of 2 nm with a bandgap of 0.8 eV and GaN (0.07) P (0.93) of -1% and a lattice mismatch of 1 nm.
N-type stress-compensated superlattice light absorption layer (p = 1 × 10 ^ 15cm ^ -3, d = 0.3μm) in which + 2% GaN (0.10) As (0.90) is laminated alternately, 51 is
n-type Si electrolytic relaxation layer (n = 2 × 10 ^ 17cm ^ -3, d = 0.05μm), 52
n-type Si multiplication layer (n = 2 × 10 ^ 15cm ^ -3, d = 0.1μm), 53 is n-type Si
Cap layer (n = 2 × 10 ^ 18cm ^ -3, d = 1.0μm), 54 is n-type Si
It is a contact layer (n = 2 × 10 ^ 19 cm ^ -3, d = 0.1 μm).

The layers constituting the laser diode and p-photodiode are 1 × 1 by using an actinic ray epitaxy apparatus.
Crystals were grown in a high vacuum of 0 ^ -5 Torr. In the growth of Si, polycrystalline Si was used as a raw material, and Sb and B were used as raw materials for the n-type dopant and p-type dopant, respectively. In the growth of the III-V semiconductor layer, the group III raw material is an ethyl-based organic metal, P and As.
The source of phosphine and arsine, and the source of N are ammonia molecules activated by ECR plasma.
Was used. Sn and Be were used as materials for the n-type dopant and p-type dopant, respectively. The growth temperature is 400 ° C, and the stress-compensated superlattice layer and the layers of single composition are all 300 ° C.
Was designed to lattice match with Si. In this way, on the Si wafer on which the III-V group optical semiconductor element is formed, a SiO2 oxide film for protecting the surface of the III-V group optical semiconductor element and for the gate of the MOS-FET is formed. Next, in the created optical semiconductor element and electronic element
Multi-layer wiring is performed using Al and SiO2 to create an electric circuit.

Next, the operating principle of this OEIC will be described. When voltage is applied to the gate electrode of the laser diode driving MOS-FET, current is injected into the surface emitting laser diode,
Laser oscillation. The laser light is introduced into the optical fiber, and the guided laser light is introduced into the photodiode. The detected laser light is converted into a current by a photodiode,
This current is converted to a voltage by RESISTOR and this voltage is
It is amplified by MOS-FET and finally output to the source electrode.

In the present embodiment, the light emitting portion and the light receiving portion were formed on different substrate crystals and used for signal transmission between IC chips. However, as in the first embodiment, an optical waveguide or an optical fiber is used for the IC chip. It may be used for internal signal transmission.

Example 3 In this example, a single surface emitting laser diode was formed on a Si substrate. Figure 7 shows a structural cross-section. The surface emitting laser diode has a diameter of 10 μm. In FIG. 7, 61 is an n-type (100) Si substrate (n = 1 × 10 ^ 18
cm ^ -3, d = 200μm), 62 is an n-type GaP buffer layer (n = 1 × 10 ^ 18)
cm ^ -3, d = 0.01 μm), 63 is an n-type GaN (0.03) P (0.97) buffer layer (n = 1 × 10 ^ 18 cm ^ -3, d = 0.5 μm), 64 is an n-type semiconductor multilayer film Mirror (n = 1 × 10 ^ 18cm ^ -3), 65 n-type Si cladding layer (n = 1 × 10 ^ 18cm ^ -3), 66 non-doped active layer, 67 p-type
Si clad layer (p = 1 × 10 ^ 18cm ^ -3), 68 is a dielectric multilayer mirror, 69 is a p-type electrode, and 70 is an n-type electrode. Effectively has a bandgap of 0.8 eV (wavelength: 1.55 μm) in the active layer
A stress-compensated superlattice layer in which GaN (0.07) P (0.93) with a lattice mismatch of -1% at 2 nm and GaN (0.10) As (0.90) with a lattice mismatch of + 2% at 1 nm are alternately stacked. Using. Its thickness is about the same in semiconductors.
Thirty-three cycles were stacked so that the wavelength was 1/4, and d = 100 nm. A three-wavelength resonator was prepared with the thickness of the n-type cladding layer being 3/8 wavelength in the semiconductor and the thickness of the p-type cladding layer being 2 + 3/8 wavelength in the semiconductor. p-type clad layer is p = 2 × 10 ^ 18c to reduce resistivity
Highly doped with m ^ -3. The semiconductor multilayer mirror has a high refractive index GaN (0.03) P (0.
Low refractive index AlN (0.04) P (0.9
6) It was created by alternately stacking layers. The number of laminations of the mirror layer was 20 in order to make the reflectance 99% or more. A dielectric multilayer mirror is constructed by alternately stacking a 1/4 wavelength thick high-refractive-index amorphous Si layer in the dielectric and a 1/4 wavelength thick low-refractive-index SiO2 layer in the dielectric. . The number of laminations of the mirror layer was set to 5 in order to make the reflectance 99% or more. The dielectric multilayer mirror only needs to have high-refractive index layers and low-refractive index layers alternately stacked, so SiN and SiO2, amorphous Si and SiN, or Ti
O2 and SiO2 may be used. The semiconductor layers 62-67 are continuously formed at 1 × 10 ^ -7To using a gas source molecular beam epitaxy apparatus.
Crystals were grown in a high vacuum of rr. In the growth of Si, polycrystalline Si was used as a raw material, and Sb and B were used as raw materials for the n-type dopant and p-type dopant, respectively. In the growth of the III-V semiconductor layer,
A metal was used as a group III source, phosphine and arsine were used as P and As sources, and N in which nitrogen molecules were activated by rf plasma was used as a N source. n-type dopant, p
Raw materials for type dopants are Si and C (neopentane), respectively.
Was used. The growth temperature is 600 ° C, and the stress-compensating superlattice layer and the single-composition layer are all designed to be lattice-matched to Si at 300 ° C. As a result, the lattice matching with Si can be kept within 0.1% in the whole temperature range of the fabrication process. A dielectric multilayer film is deposited on the wafer after crystal growth. Next, the element is separated as shown in FIG. 7 by performing vertical etching with a halogen-based reactive ion beam. The element diameter was 10 μm. Finally, p-type and n-type electrodes are formed to complete the surface emitting laser diode. This laser diode has a characteristic that the device life is long because misfit dislocations do not occur.

(Embodiment 4) In this embodiment, from (100) to [11]
A single avalanche photodiode was formed on a Si substrate tilted by 5 degrees in the [0] direction. In this device, detection light enters from the back surface of the substrate crystal. FIG. 8 shows a structural sectional view. Figure 8
, 71 is an n-type Si substrate (n = 1 × 10 ^ 18cm ^ -3, d = 200μ
m), 72 is an n-type Si buffer layer (n = 1 × 10 ^ 18cm ^ -3, d = 0.5μ
m), 73 is a p-type Si multiplication layer (p = 2 × 10 ^ 15 cm ^ -3, d = 0.2 μm),
74 is a p-type Si electrolytic relaxation layer (p = 2 × 10 ^ 17cm ^ -3, d = 0.1μm), 7
5 is GaN (0.1) As (0.9) with a + 2% lattice mismatch of 3 nm and a 3 nm lattice mismatch of -0.5 eV.
Non-doped stress-compensated superlattice optical absorption layer (p = 2 × 10 ^ 15cm ^ -3, d = 0.3μm) with 2% GaN (0.14) P (0.86) stacked alternately,
76 is a p-type GaN (0.03) P (0.97) cap layer (p = 2 × 10 ^ 18cm ^-
3, d = 1.0 μm), 77 is a p-type Si contact layer (p = 2 × 10 ^ 19 cm ^
-3, d = 0.1 μm), 78 is a polyimide insulating protective film, 79 is a p-type electrode, 80 is an n-type electrode, and 81 is a non-reflective film. Semiconductor layer 72-77
Was continuously grown in a high vacuum of 1 × 10 ^ -7 Torr using a gas source molecular beam epitaxy system. In the growth of Si, polycrystalline Si was used as a raw material, and Sb and B were used as raw materials for the n-type dopant and p-type dopant, respectively. In the growth of the III-V semiconductor layer, a metal was used as a Group III source, phosphine and arsine were used as P and As sources, and N, which was a nitrogen molecule activated by rf plasma, was used as a N source. . Si and C (neopentane) were used as the raw materials for the n-type dopant and the p-type dopant, respectively. The growth temperature is 600 ° C, and the stress-compensated superlattice layer and the single-composition layer are all 300 ° C.
It is designed to be lattice matched to i. As a result, the lattice matching with Si is 0.1% over the entire temperature range of the fabrication process.
Can be kept within. Wafer after crystal growth has a diameter of 50 μm
The element is separated as shown in FIG. 8 by performing wet etching in order to form the light receiving part and the n-type electrode forming part. Next, an insulating protective film is formed with polyimide, and an n-type electrode and a p-type electrode are vapor-deposited. Finally, the non-reflective film 81 is coated on the back surface of the substrate crystal using SiN. Since this avalanche photodiode has a bandgap of 0.5 eV in the light absorption layer, it can detect long-wavelength light with a wavelength of about 2.5 μm, and Si has a large difference in ionization coefficient between electrons and holes. Since it is used for, high multiplication is possible. In addition, since misfit dislocations do not occur, the device life is long.

(Embodiment 5) FIG. 9 is a structural sectional view of a semiconductor laser to which the present invention is applied. In FIG. 9, 91 is an n-type
(110) Si substrate, 92 is an n-type GaP clad layer (1 μm), 93 is a non-doped GaN (0.1) As (0.9) active layer (50 nm), and 94 is a p-type GaP clad layer (1 μm). The layers 92 to 94 were continuously grown on the Si substrate 91 in a high vacuum of 1 × 10 ^ -2 Torr using an actinic ray epitaxy apparatus. A metal was used as a group III source, phosphine and arsine were used as P and As sources, and activated nitrogen was used as a N source. The grown wafer is a current confinement layer 95, p made of a silicon nitride film.
A mold electrode 96 and an n-type electrode 97 were applied, and the chips were cleaved into 300 μm squares. When a current was injected into the semiconductor laser thus produced, near-infrared laser light was oscillated at room temperature. In this example, GaP was used as the cladding layer, but Al was added to increase the band gap difference with the active layer, and Al (a) Ga (1-a) P: (0 ≦ a ≦ 1) Is also good. Also, by adding N to this Al (a) Ga (1-a) P, Al (a) Ga (1-a) N (x) P (1-x):
It is even better if (0 ≦ a ≦ 1,0 <x <1) and it is perfectly lattice-matched with the substrate crystal.

(Embodiment 6) FIG. 10 is a structural sectional view of a light emitting diode to which the present invention is applied. In FIG. 10, 101 is n
Type (100) GaP substrate, 102 is n-type InN (0.4) P (0.6) layer (1μ
m) and 103 are p-type InN (0.4) P (0.6) layers (1 μm). 102
And 103 layers were 1 x 10 using an actinic radiation epitaxy system.
Crystals were continuously grown on the GaP substrate 101 in a high vacuum of ^ -3 Torr. Organometallics were used as Group III raw materials, phosphine and arsine as P and As raw materials, and activated nitrogen as N raw materials. The grown wafer was provided with a p-type transparent electrode 104 and an n-type electrode 105. When a current was injected into the diode thus produced, red emission could be observed at room temperature.

In the optical element of this embodiment, a laser diode,
Although the fabrication of the photodiode and the light emitting diode has been described, it goes without saying that the present invention can be applied to other optical semiconductor elements such as a light modulation element. MO for electronic devices
It goes without saying that it can be applied to electronic devices other than S-FETs, and it is also possible to apply the electric circuits that have been put to practical use in Si-IC. Further, it goes without saying that the optical elements shown in the first and second embodiments can operate as a single element without being integrated with the electronic element. Although Si is used as the substrate crystal in Examples 1 to 5, GaP or AlP having substantially the same lattice constant can also be used. As the material of the layer having tensile strain in the stress-compensated strained superlattice, N-based mixed crystal semiconductor AlGaInNPAsSb can be widely used in addition to GaNP and AlNP.

[0032]

According to the present invention, a group III-V mixed crystal semiconductor can be epitaxially grown on a Si substrate without generating misfit dislocations, and a semiconductor element that can be monolithically integrated with a Si electronic element can be provided. Can be provided,
It can be applied to OEIC.

[Brief description of drawings]

FIG. 1 is a sectional view of an OEIC according to a first embodiment of the present invention.

FIG. 2 Material of multilayer mirror.

FIG. 3 shows the relationship between the degree of lattice mismatch and the critical film thickness.

FIG. 4 shows the relationship between the lattice mismatch of GaNAs, GaNP, AlNAs, AlNP and GaPAS with the Si substrate and the band gap.

FIG. 5 shows the relation between lattice constant and temperature in Si and GaNP.

FIG. 6 is a sectional view of an OEIC according to a second embodiment of the present invention.

FIG. 7 is a sectional view of a surface emitting laser diode according to a third embodiment of the present invention.

FIG. 8 is a sectional view of an avalanche photodiode according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view of a surface emitting laser diode according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view of a light emitting diode according to a sixth embodiment of the present invention.

[Explanation of symbols]

11 ... n type Si substrate, 12 ... Si clad layer, 13 ... Si core layer, 14
… Si cladding layer, 15… n-type GaN (0.03) P (0.97) buffer layer, 16… n-type semiconductor multilayer mirror, 17… n-type GaN (0.03) P
(0.97) clad layer, 18 ... 2 nm GaN (0.07) P (0.93) and 1 nm
Stress-compensated superlattice active layer in which GaN (0.10) As (0.90) is alternately laminated, 19 ... p-type GaN (0.03) P (0.97) cladding layer, 20 ... p-type semiconductor multilayer mirror, 21 ... semi-metal GaN (0.19) As (0.81) contact layer, 22 ... n-type GaN (0.03) P (0.97) layer, 23 ... 2 nm Ga
Non-doped stress-compensated superlattice layer consisting of N (0.14) P (0.86) and 2nm GaN (0.10) As (0.90) stacked alternately, 24… p-type GaN (0.03)
P (0.97) layer, 25 ... Semi-metal GaN (0.19) As (0.81) contact layer, 41 ... p-type GaN (0.03) P (0.97) buffer layer, 42 ... p-type AlN
(0.04) P (0.96) clad layer, 43 ... p-type AlGaNP guide layer, 44
… 10 nm GaN (0.03) P (0.97) barrier layer and 1.5 nm GaN (0.10)
Stress-compensated non-doped strained quantum well active layer composed of 2.5 alternating As (0.90) well layers, 45… n-type AlGaNP
Guide layer, 46 ... n-type AlN (0.04) P (0.96) clad layer, 47 ... S
i contact layer, 48 ... p-type GaP buffer layer, 49 ... p-type GaN (0.
03) P (0.97) buffer layer, 50… 2nm GaN (0.07) P (0.93) and 1
nm type GaN (0.10) As (0.90) alternately laminated n-type stress compensation type superlattice light absorption layer, 51 ... n type Si electrolytic relaxation layer, 52 ... n type Si multiplication layer, 53 ... n type Si cap Layer, 54 ... n-type Si contact layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01S 3/18

Claims (24)

[Claims] 1. An N-based mixed crystal semiconductor Al (a) Ga (b) In (1-ab) N (x) P.
(y) As (z) Sb (1-xyz) (0≤a≤1, 0≤b≤1, 0 <x <1,0≤y
A semiconductor device using <1,0 ≦ z <1), wherein the lattice strain of a plurality of semiconductor layers forming the semiconductor device is within a critical strain amount at which misfit dislocations occur. 2. The semiconductor device according to claim 1, wherein the lattice strain of the semiconductor layer is within ± 4%. 3. An N-based mixed crystal semiconductor Al is used as a material for a layer having tensile strain in a semiconductor device using a layer in which a layer having compressive strain and a layer having tensile strain are laminated to compensate for stress.
(a) Ga (b) In (1-ab) N (x) P (y) As (z) Sb (1-xyz) (0 ≦ a ≦
A semiconductor device characterized by using 1,0 ≦ b ≦ 1, 0 <x <1,0 ≦ y <1,0 ≦ z <1). 4. The semiconductor device according to claim 1, wherein the semiconductor device is epitaxially grown on a Si crystal. 5. Si of a plurality of semiconductor layers constituting a semiconductor element
5. The semiconductor device according to claim 4, wherein the degree of lattice mismatch with is within the critical strain amount at which misfit dislocations occur in the entire temperature range of the fabrication process. 6. The semiconductor according to claim 4, wherein the degree of lattice mismatch with a plurality of semiconductor layers having a film thickness of 0.1 μm or more with Si is within ± 0.1% in the entire temperature range of the manufacturing process. element. 7. The semiconductor device according to claim 1, wherein the semiconductor element is epitaxially grown on a GaP or AlP crystal.
4. The semiconductor element according to any one of 3 to 3. 8. The semiconductor device according to claim 1, wherein the semiconductor device is a laser diode. 9. The semiconductor device according to claim 8, wherein a layer having a compressive strain and a layer having a tensile strain is laminated to compensate for stress, and the layer is used as an active layer of the laser diode. 10. The material of the cladding layer or guide layer of the laser diode is Al (a) Ga (1-a) N (x) P (1-x) (0 ≦ a ≦ 1, 0
9. The semiconductor device according to claim 8, wherein .ltoreq.x.ltoreq.1) is used. 11. The laser diode is a surface-emitting type, and the material of the multilayer mirror is GaP, AlP, GaNP, AlNP, Si,
9. The semiconductor device according to claim 8, wherein at least one of II-VI group semiconductors such as ZnS is used. 12. The semiconductor device according to claim 8, wherein Si is used as a material for the cladding layer or the guide layer of the laser diode. 13. The semiconductor device according to claim 1, wherein the semiconductor device is a photodiode. 14. The material of the light absorption layer of the photodiode is an N-based mixed crystal semiconductor Al (a) Ga (b) In (1-ab) N (x) P (y) As (z) Sb.
(1-xyz) (0≤a≤1,0≤b≤1, 0 <x <1,0≤y <1,0≤z <
14. The semiconductor device according to claim 13, wherein 1) is used. 15. A semiconductor device according to claim 13, wherein a layer having a compressive strain and a layer having a tensile strain is laminated to compensate for stress, and the layer is used as a light absorbing layer of the photodiode. 16. The semiconductor device according to claim 13, wherein the photodiode is an avalanche multiplication type and Si is used as a material for the multiplication layer. 17. The semiconductor device according to claim 5, wherein the semiconductor device is integrated with a Si electronic device. 18. The semiconductor device according to claim 17, wherein the semiconductor device is an optical semiconductor device. 19. The semiconductor device according to claim 18, wherein the wavelength of light used in the optical semiconductor device is transparent to Si. 20. An optical semiconductor element used in an optoelectronic integrated circuit, wherein the optical circuit is formed in a substrate. 21. A semiconductor device characterized in that a narrow bandgap of 0.5 eV or less or a semimetal N-based mixed crystal semiconductor is used as a material of an electrode contact layer. 22. A compound semiconductor optical semiconductor device formed on a Si, GaP, AlP substrate, wherein Si is used for an electrode contact layer. 23. N-based mixed crystal semiconductor Al (a) Ga (b) In (1-ab) N (x)
P (y) As (z) Sb (1-xyz) (0 ≦ a ≦ 1,0 ≦ b ≦ 1, 0 <x <1,0 ≦
In a semiconductor device using y <1,0 ≦ z <1), AlGaInNPA
sSb is 10 ^ -2 (^ represents superscript, 10 ^ -2 means 10 -2. The same applies below) Epitaxial growth was performed using activated nitrogen as a source of N in a high vacuum below Torr. A semiconductor device characterized by being present. 24. In a semiconductor device using an N-based mixed crystal semiconductor AlGaInNPAsSb, C, Be, Si, as impurities of AlGaInNPAsSb,
A semiconductor device characterized in that Sn is used.