JPH06324956A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the restart time of a program by evading the execution of wasteful initialization processing by providing a flag means set at a time when write processing is performed by an instruction execution means. CONSTITUTION:A flag means 4 is always set at a set state (FLG='1') while data are written on a RAM 2, and it is always set at a reset state(FLG='0') in a period other than that. Therefore, when system reset is applied to a CPU 1, the content of the flag means 4 is checked by making access by the CPU 1 when it is restored after wards, and when it shows FLG='1', the initialization processing is performed assuming that write data on memory is destroyed. While, when it shows FLG='0', the program can be rerun assuming that no destruction of the write data on the memory occurs. In such a way it is possible to shorten the restart time of the program by eliminating the wasteful initialization processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a reset when a power supply changes, a reset when a runaway occurs,
The present invention relates to a data processing device in which instruction execution is interrupted by various system resets such as reset by a reset switch or standby (temporary interruption of processing by an external signal) request.

[0002]

2. Description of the Related Art FIG. 6 is a conceptual flowchart of conventional data processing. When the process is started, the desired program is executed after the registers and memory are initialized, but if there is a system reset or standby request during the program execution, instruction execution will be executed to ensure the data reliability of the memory. Is interrupted and predetermined initialization processing is performed.

The reason for this is that if there is a system reset or a standby request during the data write operation to the memory, the write operation may not end normally (thus, the write data is destroyed. This is because a reliable processing result cannot be obtained even if the program is restarted as it is.

[0004]

However, in such a conventional data processing apparatus, when a system reset or a standby request is generated asynchronously with the operation in the microcontroller, the initialization processing is executed without exception. Therefore, there was a problem that, for example, although the write operation ended normally (the write data was not destroyed), the initialization process was performed wastefully and it took time to restart the program. . [Object] Therefore, according to the present invention, when instruction execution is interrupted by a system reset, a standby request, or the like, it is determined whether the write data to the memory is good or bad, and unnecessary initialization processing is not performed. The purpose is to shorten the resumption time of.

[0005]

In order to achieve the above object, the present invention provides a storage means capable of reading / writing data, and an instruction executing means for executing a program including a read / write process for the storage means. And flag means which is set when the write processing is being executed by the instruction executing means, and when the instruction execution by the instruction executing means is interrupted, the contents of the flag means are checked to perform the write processing. It is characterized in that it is configured to determine the presence or absence of interruption.

[0006]

In the present invention, since the flag executing means is set when the write processing is executed by the instruction executing means, only the contents of the flag executing means are inspected when a system reset or a standby request occurs. It is possible to judge whether the write data to the memory is good or not (presence or absence of data destruction), and the initialization processing can be executed only in the case of data destruction. Therefore, useless initialization processing can be avoided, and the program restart time can be shortened.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 5 are diagrams showing an embodiment of a data processing device according to the present invention. First, the processing flow of this embodiment will be described with reference to the conceptual flowchart of FIG. The flowchart shows the register and memory initialization processing (hereinafter simply referred to as “initialization processing”) executed immediately after the start,
An arbitrary program executed after this initialization processing (main body of various application programs other than the initialization processing: hereinafter simply referred to as "program").

The program includes various routines (for example, access to peripheral circuits such as I / O and memory) for realizing its function. In this embodiment, the write process (that is, memory access) of the memory access process is performed. It is referred to as a "first point" that a flag means (FLG) is placed in the set state during the period in which the data writing process is performed. Hereinafter, for convenience, the set state is "1" and the reset state is "0". Further, when a system reset or standby (hereinafter simply referred to as "system reset") is applied during the execution of the program, the content of the flag means (FLG) is inspected at the time of subsequent recovery, and FLG = "1". "(That is, the write process is interrupted by system reset), the initialization process is executed assuming that the write data to the memory is destroyed, while FLG =" 0 "indicates that the write data to the memory is The "second point" is to re-execute the program (in other words, pass the initialization process) assuming that the destruction has not occurred.

Therefore, in this embodiment, it is possible to know whether or not the write data to the memory is destroyed by only checking the contents of the flag means (FLG) when the system reset occurs, and it is limited to the case where the data is destroyed. Since it is possible to execute the initialization processing in this way, it is possible to avoid unnecessary execution of the initialization processing and shorten the program restart time.

FIG. 2 is a hardware configuration diagram of a one-chip microcontroller to which this embodiment is applied. 1 is a CPU (central processing unit) as an instruction executing means.
t), 2 is a memory such as a RAM (rando
m access memory), 3 is a peripheral circuit group such as I / O, 4 is a flag means, 5 is a data bus, 6 is an address bus, and these are contained in one chip. RAM2,
A unique address is assigned to each of the peripheral circuit 3 and the flag means 4, and the RAM 2, the peripheral circuit 3 or the flag means 4 having an address matching the address signal from the CPU 1 transmitted via the address bus 6, The data is accessed from the CPU 1 via the data bus 5. For example, when the address signal on the address bus 6 matches the assigned address of the RAM 2, the CPU 1 can read (when the read signal is active) or write (when the write signal is active) the RAM 2, or the address signal becomes When the assigned address of the flag means 4 matches, the CPU 1 can read the flag means 4 (when the read signal is active).

Here, the CPU 1 outputs a write cycle start pulse (hereinafter simply referred to as "start pulse") to the RAM 2 when starting the write operation, and a write cycle end pulse (hereinafter referred to as the "start pulse") when ending the write operation. , Simply called "end pulse"). The flag means 4 is set (FLG = "1") in response to the start pulse, and the flag means 4 is reset (FLG = "1" in response to the end pulse.
"0").

Therefore, according to the hardware configuration of FIG. 2, the flag means 4 is always in the set state (FLG = "1") while the data is being written in the RAM 2, and is otherwise in the reset state (FLG). = “0”), for example, when a system reset is applied to the CPU 1, the flag means 4 is accessed from the CPU 1 at the time of recovery thereafter, and the contents are inspected, and FLG =
If it is "1", the initialization process is executed assuming that the write data to the memory is destroyed, while FLG =
If it is "0", the program can be re-executed on the assumption that the write data in the memory has not been destroyed.

FIG. 3 is a concrete hardware configuration diagram. In this figure, 10 is a CPU, 11 is an address bus for upper address signals (A _{08 to} A ₁₅ ), 12 is an address bus for lower address signals (A _{00 to} A ₀₇ ), 13
Are lower address signals (A _{00 to} A ₀₇ ) and data signals (D
₀₀ to D ₀₇₎ and shared bus, 14 a data bus, 15a is latched, 15b are tristate transceiver 16
Is an address decoder. The latch 15a is the CPU 1
When the ALE (address latch enable) signal from 0 is at the H level, the lower address signals (A _{00 to} A ₀₇ ) on the dual-purpose bus 13 are taken in and the lower address bus 12
15b is a dual-purpose bus 13 and a data bus 1.
4, which controls the contention with the data bus No. 4 and can transfer the data on the data bus 14 to the dual-purpose bus 13 at least when the BUFC (buffer control) signal from the CPU is at the L level. 16 is an address match signal AC which becomes H level when the assigned address of the flag means (a flip-flop 22 described later) and the address signals on the address buses 11 and 12 match.
It outputs MP.

Further, 17 is a write signal generation circuit, 18 is an edge detection circuit, 19 is a reset signal generation circuit, 20 is a reset enable signal generation circuit, and 21 is a flip-flop as flag means (hereinafter referred to as "flag means"). , 22 are flag information output circuits. The write signal generation circuit 17 outputs an inverter gate 17a that outputs a signal CLKX that is the inverted CLK (clock) signal from the CPU 10 and a signal that is fixed at the H level when the WR signal from the CPU 10 is at the H level, while the WR signal is output. Is L
When it is at a level (write cycle), it is provided with a NOR gate 17b that outputs an inverted signal of CLKX (that is, a CLK signal) and an inverter gate 17c that inverts the output of the NOR gate 17b. Eventually, the write signal generation circuit 1
7 outputs a signal S ₁₇ that is fixed at the H level while the WR signal is at the H level, and has a phase opposite to that of the CLK signal while the WR signal is at the L level.

The edge detecting circuit 18 is a delay circuit composed of inverter gates 18a to 18c and an RC circuit 18d, and is a W circuit.
The R signal is slightly delayed, and the NOR gate 18e logically sums the delayed WR signal and the non-delayed WR signal,
A signal S ₁₈ having a minute pulse width that rises to the H level at the timing of the falling edge of the WR signal is output. Reset signal generating circuit 19 comprises a NAND gate 19a which resets the enable signal S ₂₀ and outputs a signal of the ALE signal and the opposite phase at the H level, and an inverter gate 19b which inverts the inverted signal, eventually The reset signal generation circuit 19 outputs the signal S ₁₉ in phase with the ALE signal when the reset enable signal S ₂₀ is at the H level.
1 to the reset terminal (R).

The reset enable signal generation circuit 20 includes
A negative logic system reset signal RST (or a standby signal) is applied to the reset input side of a set / reset flip-flop configured by connecting two NOR gates 20a and 20b to each other, and the NOR gate 20c of the set gate is connected to the set input side. Output, ie address match signal ACMP
And a logical sum signal of the negative-phase signal ACMPX and the signal S ₁₇ is given. When the initial state and the system reset (or standby) are applied, the output signal S ₂₀ (reset enable signal) becomes the L level (reset prohibition of the flag means 21), while when the address coincides and the CLK signal rises. The output signal S ₂₀ becomes H level (reset permission of the flag means 21).

The flag means 21 is connected to the reset terminal (R).
Input signal S₁₉Reset state (output
Q = H level) and the signal input to the set terminal (S)
Issue S ₁₈Is set at the rising edge of (output Q = L level
Le). The flag information output circuit 22
Outputs the inverted signal ACMPX of the dress match signal ACMP.
Inverter gate 22a and RD signal (read signal)
When the signal is active (L level)
Outputs the inverted signal (that is, address match signal ACMP)
NOR gate 22b and the address match signal ACMP
Flag on level (ie on address match)
Output Q of means 21 as data as flag (FLG) information
Provided with a buffer 22c for sending to any bit of the bus 14.
Get

Incidentally, 23 is an internal RAM, 24 is a timer,
25 is an input / output for inputting / outputting an interface with an external circuit
Port 26, an interface for accessing external RAM
Face circuit, P₁~ P₆Is a representative pad
It Next, the operation will be described. Figure 4 shows the operation tie of the above configuration.
It is a mingting chart. During the period “A”,
Output enable signal S₂₀Is H level, and flag means
21 resets are allowed. Therefore, the ALE
Signal having the same width as the H level period of the signal ₁₉Is generated
Then, the flag means 21 is reset and Q = L level,
That is, FLG = “0”. After that, the WR signal goes low.
When you fall to the bell, address signal A ₀₀~ A₀₇, A₀₈~
A₁₅Designated by, for example, RAM (RAM2 in FIG. 2
Data D)₀₀~ D₀₇Write operation starts
And the set signal created at the falling edge of this WR signal
S₁₈Flag means 21 is set in response to
Bell, that is, FLG = "1". FLG = "1"
The state of will remain until the ALE signal rises in the next period "B".
Then, after being reset at the rising edge of the ALE signal, the synchronization
It is set again when the WR signal falls between
It

Considering that the system reset signal RST changes to the L level at an arbitrary time point t _x during the L level period of the WR signal (in other words, during the data writing to the memory) in the period “B”, At this time t
_{At x} , since the reset enable signal S ₂₀ changes to the L level, the reset signal S ₁₉ is not generated in some periods including the reset sequence period, and the flag means 2
1 is the state (FLG =
"1") will be retained.

Therefore, for example, in the period "C" after the reset sequence, the flag means 21 is addressed,
Further, by setting the RD signal to the L level and the BUFC signal to the L level, the flag means 21 and the CPU 10 can be connected via the address bus 14, and CP
The state of the flag means 21 can be checked by U10. Now, the state of the flag means 21 is "1", which means that a system reset has occurred during the data writing to the RAM, which means that the possibility of data destruction is high. In this case, in terms of reliability, the system should be restarted by returning to the initialization process.

However, if the state of the flag means 21 is not "1", it indicates that a system reset has occurred except in the write cycle, and there is no fear of data destruction. Therefore, in this case, it is necessary to execute the initialization process. Instead, just restart the program. The restart time can be shortened by the time required for the initialization processing. The reset enable signal S ₂₀ returns to the H level at the rising timing of the CLK signal when the WR signal is at the L level in the period “d”.

FIG. 5 is another concrete hardware configuration diagram. The same components as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. In this configuration example, 1
The flip-flop 30a and the one latch 30b constitute the flag means 30, the ALE signal is directly applied to the reset terminal (R) of the flip-flop 30a, and the system reset in which the clock terminal of the latch 30b is inverted by the inverter gate 30c. A signal RST (or a standby signal) is given. When a system reset occurs, the state of the flip-flop 30a is captured by the latch 30b, and the content of the latch 30b is transferred to the CPU 10. Reset enable signal generation circuit 2 of the configuration example of FIG.
0 and the reset signal generation circuit 19 are unnecessary, and the circuit configuration can be simplified.

In the present invention, the peripheral circuit, CPU, flag, RAM, etc. do not necessarily have to be provided in one chip.

[0024]

According to the present invention, when instruction execution is interrupted due to a system reset, a standby request, or the like, it is possible to judge whether the write data to the memory is good or bad, and restart the program without performing unnecessary initialization processing. The time can be shortened.

[Brief description of drawings]

FIG. 1 is a conceptual flowchart of one embodiment.

FIG. 2 is a hardware configuration diagram of an embodiment.

FIG. 3 is a concrete hardware diagram of one embodiment.

FIG. 4 is an operation timing chart of FIG.

FIG. 5 is another concrete hardware configuration diagram of the embodiment.

FIG. 6 is a conceptual flowchart of conventional data processing.

[Explanation of symbols]

 2: RAM (storage means) 1, 10: CPU (command execution means) 4, 21, 30: flag means

Claims (3)

[Claims] 1. A storage means capable of reading / writing data, an instruction executing means for executing a program including a read / write processing for the storage means, and a write processing executed by the instruction executing means. Flag means to be set, and when the instruction execution by the instruction execution means is interrupted, the contents of the flag means are inspected to determine whether or not the write processing is interrupted. Data processing device. 2. The content of the flag means is fetched at the timing of interruption of instruction execution by the instruction executing means, and
2. The data according to claim 1, further comprising a register which can be arbitrarily read from the instruction executing means, and can determine whether or not the write processing is interrupted even if the flag means is cleared after the instruction execution is restarted. Processing equipment. 3. A flag clear permission unit that is set by a write process from the instruction execution unit and is cleared by a signal that interrupts the instruction execution, and the flag clear permission unit prohibits the flag unit from being cleared. Thus, the data processing apparatus according to claim 1, wherein it is possible to determine whether or not the write processing is interrupted until the flag clear permission unit is cleared even if instruction execution is restarted.