JPH06324939A - Memory circuit and control method for the same - Google Patents

Abstract

PURPOSE:To vary the ratio of cache memory command and area for data. CONSTITUTION:Over one write circuits and over one read circuits respectively corresponding to the memory areas for commands and data are provided, a memory cell array 11 are divided into blocks by dividing a data line, and divided data lines 18 and 19 are connected so as to be disconnected by switch means Tr 5 and Tr 6. Further, respective X address decoders 12 and 13 for instruction and data are divided into blocks corresponding to the division of the data line. A word line 20 of each block can be accessed by an output from both of the X address decoders for command and data. Since the respective blocks are arbitrarily combined under the control of the switch means, the respective blocks are programmed in either of the memory areas for command and data, and the dividing ratio of the memory areas for command and data is varied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit and a control method thereof, and more particularly, to a data bus and a command bus which are built in an integrated circuit and which can transmit information to each bus for command and data. The present invention relates to a memory circuit suitable for a cache memory circuit having a physical address area that can be divided into two cache memory areas, and a control method thereof.

[0002]

2. Description of the Related Art Recently, due to the progress of diffusion process technology, it has become possible to manufacture a cache memory at a low cost, and it is difficult to use a cache memory in a microprocessor because it is expensive in the past. It has come to be installed. In many cache memories, the physical access area is divided into two areas, an instruction memory area and a data memory area, in order to sufficiently exert the performance. These two areas are usually used as fixed memory areas. However, the area ratios of both areas for maximizing the performance of the cache memory differ for each application software.

Therefore, it is desired that the ratio of the area sizes of the instruction memory area and the data memory area can be changed each time if desired. In order to meet this demand, for example, two caches whose sizes are different from each other are adopted, and which of the instruction memory area and the data memory area is to be allocated can be set at the time of initialization or reset of the microprocessor. Some have done so. However, it is more preferable if the optimum ratio of the instruction and data cache areas can be set for each application software.

A conventional cache memory circuit having a variable area ratio will be described with reference to FIGS. 10 and 11 are diagrams showing the internal circuit and the entire circuit of the memory cell of the cache memory circuit, respectively. In FIG. 10, this memory cell has two read data terminals RDA and RDA inside one memory cell.
DB and two sets of write data terminals WDA and XWDA
(Indicates WDA with top bar. Same below), WDB
And XWDB, and two read address terminals RAA and RAB and write address terminals WAA and WAB, respectively. Further, in this cache memory, as shown in FIG. 11, first and second read address decoders 1XDR and 2XDR and first and second write address decoders 1XDW and 2XDW.
And two sets of write and read data lines for each memory cell.

With the above structure, in this conventional cache memory, two different memory cell arrays are provided.
Memory cells at one address can be accessed simultaneously and independently. Therefore, by defining the address range for the instruction and the data for each decoder by different logic, this memory cell array can be used for two cache memory areas for the instruction and the data, and The area ratio can be changed.

[0006]

In the above-mentioned conventional cache memory circuit in which the ratio of the instruction and data memory areas is variable, the number of elements in the memory cell is smaller than the number of ordinary memory cells, which is six. Since the number of wirings connected to each memory cell is larger than that of a normal cache memory circuit, the total area occupied by the memory cell array is several times larger than that of a normal memory cell array. It also had the drawback of becoming larger.

In view of the above-mentioned drawbacks of the conventional cache memory circuit, the present invention does not have a large number of memory cells and therefore does not have a large occupied area.
An object of the present invention is to provide a memory circuit suitable for a cache memory circuit having a variable ratio of instruction and data memory areas and a control method thereof.

[0008]

To achieve the above object, the memory circuit of the present invention can be divided into first and second areas for transmitting information to and from the first and second buses, respectively. In a memory circuit having a memory area, at least one memory read / write circuit corresponding to the first and second areas, respectively, and first and second address decoders corresponding to the first and second areas, respectively. The outputs of the circuit and the first and second address decoder circuits are commonly connected, and a plurality of word lines, one of which is independently selectable by the outputs of the two, and a plurality of divided data lines, respectively, are divided. A plurality of data lines, each one of the divided data lines being arranged to be connectable to the read and write circuits corresponding to the first and second regions, respectively; Each division Switch means disposed between the data lines and capable of connecting and disconnecting the divided data lines by being controlled to open / close by a first control signal, and outputs of the first and second decoders by a second control signal As a memory cell block corresponding to the word line and the divided data line, and a decoder control unit for controlling each block and a plurality of memory cells respectively connected to the divided data line through selection of the word line. A memory cell array configured, and the memory cell block is incorporated into either the first or second region according to selection of the first and second control signals.

The memory circuit control method of the present invention is
In a method of controlling a cache memory circuit having a memory area that can be divided into first and second areas for transmitting information to and from a first bus and a second bus, respectively, in the memory circuit,
At least one corresponding to each of the first and second regions
Two memory read / write circuits and first and second address decoder circuits corresponding to the first and second areas, respectively, are provided, and both the first and second address decoder circuits are provided for each word line. Each output is connected in common, each data line is divided into a plurality of divided data lines, the memory cell array is divided into memory cell blocks corresponding to the divided data lines, and the divided divided data lines are connected to each other. Connection is made possible in accordance with the first control signal, and the second control signal controls the first and second decoders for each decoder block corresponding to the division of the data line. Is selected, each memory cell block is incorporated into either the first region or the second region.

[0010]

According to the memory circuit and the control method thereof of the present invention, the word line can be selected by both the first and second address decoders, and the data line is divided into a plurality of divided data lines. With the configuration in which the memory cell array is divided into blocks corresponding to the division of the data line, the connection and disconnection of the data line corresponding to the first control signal and the output of the first or second address decoder corresponding to the second control signal. Depending on the selection, by connecting the memory cells corresponding to each word line and the divided data line to the read and write circuits corresponding to the first or second area, the memory cell block can be arranged in either the first or second area. Transfer to.

[0011]

The present invention will be described in more detail with reference to the drawings. 1 to 3 are views showing a cache memory circuit which constitutes a memory circuit according to an embodiment of the present invention, FIG. 1 shows the entire structure, and FIGS. 2 and 3 show partial detailed views thereof. This cache memory circuit includes a memory cell array 11 composed of four memory cell blocks 1A to 1D arranged in the center and configured as a set of a large number of memory cells, and one set of an X address decoder for instruction and one set of X address decoder for data. (X decoder) groups 12 and 13, and one sense amplifier and one write circuit SWR1I and one write circuit SWR1D for instruction and data,
One Y address decoder for each of instruction and data (Y
A decoder) and selectors YSEL1I and YSEL1D.

The X decoder group 12 for instructions, the Y decoder and selector YSEL1I, and the sense amplifier and write circuit SWR1I for instructions are respectively an I-cache address bus 14 and an I-cache data bus 15 for instructions.
The address information and the data information for the instruction cache memory area forming the first area are fetched from these. Further, the X decoder group 13 for data, Y
The address decoder YSEL1D and the data sense amplifier and write circuit SWR1D are respectively data D
It is connected to the cache address bus 16 and the D-cache data bus 17, and fetches address information and data information for the data cache memory area forming the second area from these.

Each X decoder group 1 for instruction and data
Reference numerals 2 and 13 denote a plurality of blocks, respectively, and four blocks IXD_A, IXD_B, IXD_C, and IXD_ in the drawing.
D, DXD_A, DXD_B, DXD_C, DXD_D
Is divided into The outputs of the X decoder groups 12 and 13 corresponding to each other are commonly connected to one word line 20. For example, the output of the clocked inverter G4 of the data address decoder block DXD_A,
The output of the clocked inverter G5 of the instruction address decoder block IXD_A is commonly connected to the same word line 20. With such a configuration, one common word line 20 can be accessed from both the X decoders 12 and 13 groups for instructions and data.

The divided data line pairs 18 and 19 of the memory cell blocks 1A to 1D are connected to the divided data line pairs 18 and 19 of the adjacent memory cell blocks and the data line connecting N-channel transistor Tr for forming a transfer gate.
5 and Tr6 (for example, used to mean Tr5 and Tr6. The same applies hereinafter) -are connected in a divisible manner by switch means. Opening / closing of each of the transistor switches Tr5 and Tr6 is controlled by a data line connection signal φp. In addition, each division data line 1
Precharging transistors Tr3 and T for every 8 and 19
r4 equivalent is provided between the low potential side power source (not shown). Each data line configured as a set of the divided data lines 18 and 19 is configured such that a pair is selected by each of the instruction and data Y decoders and the selectors YSEL1I and YSEL1D.

Each memory cell 21 is configured as a normal 6-transistor type memory cell, and corresponds to data holding inverters G1 and G2 and a transistor gate T.
It is composed of r1 and Tr2. Each memory cell 21
Receives the active signal of the corresponding word line 20 and the divided data line pair 18, 19 corresponding to the memory cell 21.
Connected to. Therefore, the memory cell array 11 is divided into blocks corresponding to the blocked X decoder groups 12 and 13 and the divided data line pairs 18 and 19.

FIG. 9 shows a command (and data) sense amplifier and write circuit SWR1I equivalent, and a command (and data) Y decoder and selector YSEL1I equivalent.
The circuit configuration for each bit is shown together with data lines 1AB and 1A corresponding to a set of divided data line pairs 18 and 19.
The Y decoder and selector have gate groups G21 and G51 corresponding to the pair of data lines.
1, G51 equivalent are provided by the number of logarithms corresponding to the data lines 1AB, 1A. When the output corresponding to one gate group G21, G51 of the Y decoder and selector becomes active, the data line pair 1AB, 1A equivalent including the divided data line pair 18, 19 is selected. Selected data line pair 1AB, 1A
Is equivalent to transfer gates Q43 and Q44,
It is connected to a write circuit or a sense circuit. The write circuit includes gates G41 and G42 and transistors Q45 and Q.
46 as a set, and is controlled by the write signal WR1 to write data signal DW1 from the data bus.
Is supplied to each memory cell via the data line pair 1AB and 1A.

Further, the sense circuit includes a transistor group Q4.
9 to Q58 and is controlled by the read signal RS1 to identify the data from the data line pair 1AB and 1A, and to output this data to the inverter 47 and the output control signal R.
It is output as the output O1 via the transistor Q61 controlled by S2. Precharge transistor Q
41 and Q42 receive the precharge signal PR1 and Y
The data line pair 1AB and 1A equivalent selected by the decoder are connected to the high potential side power supply during the precharge period, and the data line pair is precharged.

In the cache memory circuit shown in FIGS. 1 to 3 having the above-described structure, by appropriately combining the four blocks of the memory cell blocks 1A, 1B, 1C and 1D by the control signal, the cache memory area for data and The ratio of the instruction cache memory area can be selected. The method of selecting the area ratio is shown in the table of FIG.
In the same figure, I means for instructions, D means for data, and various cases of selecting the area ratio in the horizontal direction are taken. For each of these cases, the instruction area I and data for each block A to D The state of incorporation into the area D and the state of each control signal for obtaining this incorporation state are shown in the table. In addition,
In the table, V indicates an active signal and NV indicates a non-active signal as a code indicating a state corresponding to the control signal φ2IA.

In FIG. 7, for example, an instruction memory area I
The rightmost column in the drawing in which the area ratio of the memory area D for data is 4: 0 will be specifically described first. At this time, all the memory blocks A to D are incorporated into the instruction cache area I. In this case, all the outputs of the instruction X decoder group 12 are in the active state, and all the outputs of the data X decoder group 13 are in the inactive state. For this purpose, a control clock φ1I provided to the clocked inverter G5 equivalent in the instruction X decoder block
A, φ1IB, φ1IC, φ1ID become active signals, and a control clock φ1D provided to the clocked inverter G4 equivalent in the data X decoder block.
A, φ1DB, φ1DC, and φ1DD are non-active signals.

All the data line connecting transistors Tr5, Tr6 and the like arranged between the respective divided data line pairs are turned on, and each divided data line pair as a whole is a data line pair in the first region. Composed. For this purpose, data line connection signals φY1A, φY1B, φY1
All C's become active signals, and the corresponding segment data lines are electrically connected to each other. Further, a signal φS given to the Y decoder and selectors YSEL1I and YSEL1D
As shown in the figure, 1I and φSID are active signals for commands and non-active signals for data.

When the memory area ratio of 4: 0 is selected by selecting each control signal, the actual control of the cache memory is performed as follows. That is, first, the instruction X decoder blocks IXD_A, IXD_B, IDX_C, and I
By selecting the output of any one of the gates corresponding to the NAND gate G6 in DX_D, one word line 20 in the four memory cell blocks 1A to 1D is selected. When each memory cell connected to the word line 20 is connected to the corresponding segmented data line pair 18 and 19, 1 corresponding to one data line pair 1AB and 1A selected by the instruction Y decoder and selector YSEL1I is selected. One memory cell is actually selected and connected to the command sense amplifier and write circuit SWR1I, and reading or writing is performed on this memory cell. In this way, all memory cells can be used as the instruction cache memory.

Next, a case where the area ratio between the instruction area I and the data area D in FIG. 7 is 3: 1 will be described. At this time, three memory cell blocks A, B, and C are incorporated into the instruction cache memory region I, and one memory cell block D is incorporated into the data cache memory region D. For this purpose, the X decoder block for instructions IXD_
A, IXD_B, IXD_C clocked inverter G
Control clocks φ1IA, 1IB, 1IC given to 5
And a control clock φ1DD applied to the clocked inverter G4 equivalent of the data X decoder block DXD_D
Is an active signal.

On the other hand, the X decoder block for data DXD_
Clocked inverter G of A, DXD_B, DXD_C
4 control clocks φ1DA, φ1DB, φ1
Control clock φ1I given to DC and instruction X decoder block IDX_D corresponding to clocked inverter G5
Let D be a non-active signal. At this time, the data line connection signals φY1A and φY1B are active signals, φY
As a non-active signal, 1C electrically connects the memory cell blocks 1A, 1B, and 1C into the first region, and electrically disconnects the memory cell block 1D into the second region. Further, the Y decoder control signals φS1I and φS1D supplied to the Y decoder and the selector are both active signals.

When the area division structure as described above is adopted,
Instruction X decoder block IXD_A, IDX_B, I
Since the output corresponding to any one of the NAND gates G6 of DX_C and the output corresponding to the NAND gate G3 of the data X decoder DXD_D can be independently selected, the cache memory having the above area configuration exists in different areas.
The word line 20 of the book can be selected. The memory cell of the word line 20 selected by the instruction X decoder group 12 is read or written by the instruction sense amplifier and write circuit SWR1I via the data line selected by the instruction Y decoder YSEL1I as described above. Is done. The memory cell of the word line 20 selected by the data X decoder group 13 is the data Y decoder YSEL1.
Reading or writing is performed by the data sense amplifier and write circuit SWR1D via the data line selected by D. In this way, the ratio of the instruction memory area to the data memory area is controlled at 3: 1.

The selection of the other area ratios in FIG. 7 is also performed by the combination of the control clock of the clocked inverter of the X decoder group and the data line connection signal as in the above. In this manner, the cache memory circuits shown in FIGS. 1 to 3 select active or inactive of each control signal by, for example, application software, and the combination of blocks of the memory cell array and the instruction or data are selected. Select to transfer to the area. As a result, it is possible to set and control the command area and the data area at a desired ratio. The number of divisions and the size of each block in dividing the memory cell array into blocks can be arbitrarily selected.

4 to 6 are circuit diagrams showing a cache memory circuit which constitutes a memory circuit of the second embodiment of the present invention. FIG. 4 shows the whole, and FIGS. 5 and 6 show partial details thereof. Show. In the cache memory circuit of this embodiment, the four memory cell blocks 2A, 2B, 2C and 2D are arranged in 2 columns 2
4 data X decoder blocks DX arranged in rows
D_2A, DXD_2B, DXD_2C, DXD_2D
However, each memory cell block 2A, 2B,
It is arranged adjacent to 2C and 2D. The data X decoder group 13 is connected to the D-cache address bus 36 and fetches data address information.

The instruction X decoder block IXD--
1AC and IXD_1BD are respectively arranged between the memory blocks 2A and 2C, 2B and 2D arranged in two columns, respectively, are connected to the I-cache address bus 34, and fetch the address information for instructions from this. .
All word lines 40 of each memory block are accessed by the outputs of both the instruction and data X decoder groups 32 and 33. Each X decoder block IXD_1A
C, IXD_1BD, DXD_2A, DXD_2B, D
XD_2C and DXD_2D are control clocks φ2IA, φ2IB, φ of the clocked inverters that form the output stage thereof.
2IC, φ2ID, φ2DA, φ2DB, φ2DC, φ
It is controlled by 2DD.

Two sets of sense amplifiers and write circuits, two sets of Y decoders and selectors are provided for each of data and instructions, and four sets are provided for each circuit as a whole. Sense amplifier and write circuit SWR2I for each instruction
1, SWR2I2 are connected to the I-cache data bus 34, and each data sense amplifier and write circuit SWR
2D1 and SWR2D2 are D-cache data buses 37
Connected with. Among the command and data sense amplifiers and write circuits, either or both of SWR2I1 and SWR2D1 and either or both of SWR2I2 and SWR2D2 are set as active signals. The data lines are selected by Y decoder control signals φSI1, φSI2,
This is performed by an active or non-active signal of φSD1 and φSD2.

An N-channel transistor T for connecting data lines, which forms a transfer gate, is provided between the partition data line pair 38, 39 of the memory cell block 2A and the partition data line pair 38, 39 of the adjacent memory cell block 2B.
r21 and Tr22 are arranged, and a data line connection signal φY2A is applied to their gate electrodes. Further, the divided data line pair 38, 39 of the memory cell block 2C and the block data line pair 38 of the adjacent memory cell block 2D,
Similarly, a switch means including an N-channel transistor is provided between the switch 39 and 39, and the data line connection signal φY2B is applied to its gate electrode. By selecting the H level or the L level of the data line connection signals φY2A and φY2B, both the divided data lines 38 and 39 are controlled as one data line pair, or the data of each of the first and second regions is controlled. It can be controlled as a line pair.

FIG. 8 shows a method of selecting the area ratio of the memory area in the cache memory circuit of the second embodiment, similar to FIG. In the rightmost case where the ratio of the instruction memory area I to the data memory area D is 4: 0, the output of the instruction X decoder block is controlled in order to incorporate all the memory cell blocks into the instruction memory area I. Control clock φ2IA, φ2IB, φ2IC, φ2ID
Become active signals and control clocks φ2DA and φ2D for controlling the output of the data X decoder block
B, φ2DC, and φ2DD are non-active signals.
Further, the data line connection signals φY2A and φY2B are both active signals for connecting the divided data line pairs.

According to the selection of the control signal, the output of either the instruction X decoder block IXD_1AC or IXD_1BD is selected, and the memory cell blocks 2A, 2A and 2B are selected.
One word line from B is the memory cell block 2
One word line is selected from C and 2D.
Therefore, two word lines 40 can be selected at the same time. In this case, the instruction Y decoder and selector YSE
Signals φSI1 and φ for selecting L2I1 and YSEL2I2
Since either of SI2 is an active signal,
Data line pair 3 on the activated side of the memory cells accessed by the selected two word lines 40
Only the memory cells connected to 8 and 39 eventually become readable or writable, and the I-cache data bus 35
Can be connected with. In this way, all memory cells are used as the instruction cache.

Next, referring to FIG. 8, the instruction memory area I
A case where the ratio of the memory area D for data is 3: 1 will be described. In this case, memory block 2
A, 2B, and 2C are assigned for instructions, and the memory block 2D is assigned for data. Therefore, the instruction X decoder IXD
A part of _1AC and IXD_1BD and the output of the data X decoder DXD_2D are activated, and the other X decoders are deactivated. For this purpose, the clocked inverter control clocks φ2IA, φ
2IB, φ2IC, φ2DD are active signals, and φ
2DA, φ2DB, φ2DC, and φ2ID are non-active signals. Further, the data line connection signal φY2A is activated to connect the memory cell blocks 2A and 2B, and the data line connection signal φY2B is set to inactive to disconnect the memory cell blocks 2C and 2D.

In selecting the area ratio, one word line 40 is accessed by one output of the instruction X decoder block and one output of the data X decoder block DXD_2D. One of the Y decoder for instruction and the selector YSEL2I1 or YSEL2I2 is the Y decoder control signal φSI1 or φSI2.
Are selected depending on whether they are active or inactive. Also, a data Y decoder and a selector YSEL2
D2 is selected by the active Y decoder control signal φSD2.

The other area ratios in FIG. 8 are also selected by the active or non-active selection of each control signal as in the above. That is, the ratio of the first memory area for instruction and the second memory area for data is variable according to the selection of the control signal shown in the table. For each block, an optimum block shape can be selected according to the arrangement of the memory array on the chip of the integrated circuit, and by allocating these blocks to either the instruction or data cache memory area according to the arrangement, Area ratio can be selected. Allocation to each area can be made to be an optimal area ratio for application software used at that time, and the merit of having a cache memory can be maximized.

The cache memory circuit of each of the above embodiments is
It is adopted in the control method of the memory circuit of the embodiment of the present invention. The memory circuits of the above embodiments are merely examples, and the memory circuit employed in the memory circuit of the present invention and the control method of the present invention is not necessarily limited to the cache memory circuit. Various modifications and changes are possible from the embodiment.

[0036]

As described above, according to the memory circuit and its control method of the present invention, the memory cell array and the decoder are divided into blocks, and the corresponding divided data lines are connected to each other in a separable manner. Since each memory cell block can be incorporated into either the first or second area, the size ratio of the first area and the second area can be changed without complicating the configuration of each memory cell. is there. Therefore, when the memory circuit and its control method of the present invention are applied to the cache memory circuit, it is possible to select the area ratio that can maximize the performance by mounting the cache memory, and the memory circuit suitable for the cache memory according to the present invention. And a control method thereof.

[Brief description of drawings]

FIG. 1 is an overall view of a memory circuit according to a first embodiment of the present invention.

FIG. 2 is a partial detailed view of the memory circuit according to the first embodiment of the present invention.

FIG. 3 is a partial detailed view of the memory circuit according to the first embodiment of the present invention.

FIG. 4 is an overall view of a memory circuit according to a second embodiment of the present invention.

FIG. 5 is a partial detailed view of a memory circuit according to a second embodiment of the present invention.

FIG. 6 is a partial detailed view of a memory circuit according to a second embodiment of the present invention.

FIG. 7 is a signal selection diagram showing a method of selecting a region ratio in the first embodiment.

FIG. 8 is a signal selection diagram showing a method of selecting a region ratio in the second embodiment.

FIG. 9 is a circuit diagram illustrating a configuration of a Y decoder and a selector, a sense amplifier, and a writing circuit according to the first embodiment.

FIG. 10 is a circuit diagram showing a configuration of a memory cell of a conventional cache memory circuit.

11 is a circuit diagram showing an overall configuration of the cache memory circuit of FIG.

[Explanation of symbols]

SWR1I, SWR2I1, SWR2I2 instruction sense amplifier and write circuit SW1D, SWR2D1, SWR2D2 data sense amplifier and write circuit YSEL1I, YSEL2I1, YSEL2I2, instruction Y decoder and selector YSEL1D, YSEL2D1, YSEL2D2 data Y decoder and selector DIXD_A , IXD_C, IXD_D, IXD_1AC, IXD_1BD X for instruction
Decoder DXD_A, DXD_B, DXD_C, DXD_D, DXD_2A, DXD_2B, DXD_2C, DXD_2
D data X decoder φp, PR1 Precharge signal φY1A, φY1B, φY1C, φY2A, φY2B Data line connection signal φ1DA, φ1DB, φ1DC, φ1DD, φ1IA, φ1IB, φ1IC, φ1ID
X decoder output control signal φS1I, φS1D, φI1, φSI2, φS
D1, φSD2 Y decoder control signal WR1 write signal DW1 write data signal O1 output 11, 31 memory cell array 12, 32 instruction X decoder group 13, 33 data X decoder group 14, 34 I-cache address bus 15, 35 1- Cache data bus 16,36 D-cache address bus 17,37 D-cache data bus 18,19,38,39 Partitioned data line pair 20,40 Word line

Claims (5)

[Claims] 1. A memory circuit having a memory area that can be divided into first and second areas for transmitting information to and from the first and second buses, respectively. At least one corresponding memory read / write circuit, first and second address decoder circuits respectively corresponding to the first and second regions, and outputs of both the first and second address decoder circuits. It is divided into a plurality of word lines that are commonly connected and one of which is independently selectable by the outputs of both of them, and a plurality of section data lines, and each one of the section data lines is the first data line. And a plurality of data lines respectively corresponding to the read and write circuits corresponding to the second area and between the divided data lines and opened / closed by a first control signal. Controlled Switch means for connecting the divided data lines to each other; a decoder control section for controlling the output of the first and second decoders for each block by a second control signal; and the decoder control section for selecting the word lines. A memory cell array composed of a plurality of memory cells respectively connected to the divisional data lines and configured as a memory cell block corresponding to the word lines and the divisional data lines; A memory circuit, wherein the memory cell block is incorporated into either the first or second region depending on the selection. 2. The read and write circuits corresponding to the first and second areas are provided in two or more each, and the read and write circuits corresponding to the first area are provided in response to a third control signal. A first selecting means for selecting any one,
2. The memory according to claim 1, further comprising second selecting means for selecting one of the read and write circuits corresponding to the second area in response to a fourth control signal. circuit. 3. The memory circuit according to claim 1, which is configured as a cache memory circuit. 4. A method of controlling a memory circuit having a memory area that can be divided into first and second areas for transmitting information to and from a first bus and a second bus, respectively. At least one memory read / write circuit corresponding to each of the first and second regions and first and second address decoder circuits corresponding to the first and second regions are provided, and each word line is provided. On the other hand, the outputs of both the first and second address decoder circuits are commonly connected, each data line is divided into a plurality of divided data lines, and the memory cell array is divided into memory cell blocks corresponding to the divided data lines. In addition, the divided data lines can be connected to each other according to a first control signal, and the second control signal causes the first and second decoders to divide the data lines. Controls for each decoder block respond, by selection of the first and second control signals, the method characterized by incorporated each memory cell block in one of said first or second regions. 5. The method of controlling a memory circuit according to claim 4, wherein the memory circuit is configured as a cache memory circuit, and selection of each of the control signals is designated by software.