JPH06324937A - Memory card - Google Patents

Abstract

PURPOSE:To make possible the satisfactory write/read of data at high speed. CONSTITUTION:Write is executed from an EEPROM chip 1 and each time data transfer is completed for the unit of a block, a write command is executed. When data for four chips are completely written, respective chips 1-4 are just under write operations, and the side of a system waits for the next timing of data transfer while observing the RDY/BSY signal of a card. By monitoring the RDY/BSY 1 signal of the chip 1, the write of data from the system side to the respective chips 1-4 is successively changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card having a plurality of EEPROMs (electrically erasable PROMs) mounted therein.

[0002]

2. Description of the Related Art If a memory card is constructed by using a flash type EEPROM chip as a storage medium, a relatively inexpensive and large capacity memory card can be realized. But EEPROM
At present, the writing operation of the chip is slow, and high-speed writing such as writing compressed moving image data in real time cannot be realized.

Therefore, as disclosed in Japanese Patent Laid-Open No. 3-265287, information indicating the position of an empty unit recording area in which image data should be recorded first in a semiconductor memory (memory card). Area is recorded,
An empty unit recording area can be searched in a short time so that the writing speed can be increased, and as disclosed in Japanese Patent Laid-Open No. 4-268284, image information can be recorded in a plurality of EEPROMs.
A technique has been proposed in which a low-speed EEPROM can be used in real time as a high-speed image recording medium by writing data in parallel to the same.

[0004]

However, in general, EE
Since the writing time of the PROM varies depending on the chip (the writing time also varies within the same chip), an efficient high-speed writing operation cannot be realized even by simply using the parallel writing technique. Therefore, it is necessary to implement a write control method that considers the variations in the performance of each chip.

Further, in the case of the flash type EEPROM, the number of times of writing is limited, and defective bits will appear when it is used for many years. Therefore, some kind of defect management means must be provided in order to make the system recognize the defective area inside the memory card, but in the conventional structure, an area with the same type of memory (specifically, file management Areas) only store defect information.

However, in general, the file management area on the memory is an area that is accessed more frequently than the data area, and the file management area itself is likely to be the first defect. Therefore, when the file management area itself inside the memory card becomes defective due to such a structure, there is a problem that the previously recorded data becomes invalid after that time.

An object of the present invention is to provide a memory card which can write / read data at high speed and excellently.

[0008]

In order to achieve the above object, the present invention provides a readable / writable EEPR in block units.
A memory card equipped with a plurality of OM chips has a means for controlling a plurality of blocks in parallel writing in order to realize high-speed writing, and can output a signal indicating that a writing operation is in progress to the outside of the card. It is characterized in that it is possible to monitor whether or not the writing operation is being performed for each chip.

Further, it is characterized in that it is possible to monitor the writing state of the chip which first started writing the signal for outputting the writing operation to the outside of the card.

The writing operation state of each chip can be monitored from the card data bus.

Further, it is characterized in that means for individually setting a write command to each chip is provided.

Further, at the time of writing, in order to carry out a continuous write operation in units of a plurality of blocks, a means for performing chip enable switching to each chip based on the count value of the write command is provided.

Further, the memory card further comprises means for selecting the chip to enable continuous block reading.

Further, it is characterized in that the address setting means for each chip is common to each chip.

Further, the command setting means for setting a specific command to each chip is common to each chip.

Further, it is characterized in that a means for setting a command for checking the status of each chip can be set for each chip independently.

Further, as a signal indicating that the card is being read, a signal obtained by taking a logical product of the read operation state signals of the respective chips is output to the outside of the card for monitoring.

Further, at the time of reading, for enabling a continuous read operation, there is provided a means for performing chip enable switching to each chip every time a set number of blocks of a data read signal input to the card is counted. And

The card terminals for monitoring the write and read operation state signals can be used in common.
Moreover, it is characterized in that a means for switching the monitor signal between the time of writing and the time of reading is provided.

Further, it is characterized in that the means for switching the chip enable for continuous writing or continuous reading can be switched between writing and reading.

Further, the memory card is provided with means for allocating an address to each chip so that an address change from the access side when accessing over a plurality of chips is continuously changed.

The number of chips mounted is an even number.

Further, the minimum number of data erasing units is set to the product of the number of chips inside the card, the number of data within blocks and an arbitrary number.

When a bit in any of the chips has a defect, the minimum data erasing unit including the bit is set in the defective area.

Further, it is characterized in that a memory area capable of storing data of the defective area is provided.

[0026]

In the memory card having the above structure, a plurality of EEPRs are used.
Since it is possible to monitor whether or not the writing operation is being performed for each chip in the OM chip, efficient and high-speed writing control can be performed.

Further, since the write state of a plurality of chips which are being written is monitored from the chip which first started writing,
It is possible to monitor at a higher speed as compared with the case of outputting the signal obtained by the logical product to the outside, and the high speed write operation becomes possible.

The card data bus can monitor the writing state of each chip inside the card, which enables more efficient writing operation.

Further, by allowing the write command to be set for each chip independently, a higher speed write operation becomes possible.

Further, at the time of writing, by performing chip select inside the card, the load on the accessing system side is reduced.

Further, by selecting the chip so as to perform continuous block reading, it becomes possible to read the memory card efficiently and at high speed.

Further, it becomes possible to reduce the address setting cycle from the system side, which enables faster card access.

Further, it becomes possible to reduce the command setting cycle from the system side, and it becomes possible to perform faster card access.

Further, by making it possible to monitor the status of each chip, more detailed control from the system side becomes possible.

Further, it becomes possible to efficiently read the signal (Ready / Busy signal) indicating the read state of the memory card.

Further, the load on the system side is reduced by enabling the chip select function inside the card at the time of reading.

Further, the operating state of the memory card can be monitored without adding a new signal line, which reduces the load on the system side.

Further, during the write operation and the read operation,
The load on the system side is reduced by automatically switching the means for selecting each chip.

Further, since the address change to the memory card seen from the system side is continuous even when accessing across chips, it is easy for the system side to manage files in cluster units even if high-speed writing is performed. It becomes feasible.

Further, by setting the number of chips to be used to an even number (2 to the nth power), it is possible to make the address change continuous when the access is performed across the chips when the parallel writing is performed. Therefore, file management on the system side becomes easy.

Further, by making the block unit spanning a plurality of chips the minimum data erasing unit, high-speed erasing becomes possible and the continuity of the recorded data on the memory card can be maintained.

By setting the minimum data erasing unit as a defective area, the file management load on the system side is reduced.

Further, since the data in the defective area is stored in the other memory area, it is possible to manage the file with high safety.

[0044]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory diagram showing a configuration of a main part in one embodiment of the present invention, and FIG. 2 is an explanatory diagram of memory allocation in this embodiment. In this embodiment, four 2Mbit EEPROM chips 1 are provided. 4 to 4 are used to configure an 8 MByte flash EEPROM card, and the chip select unit 5 performs chip select at the time of writing / reading.

In order to enable high-speed writing / reading, the memory as shown in FIG. 2 is designed so that the addresses are continuously changed in block units (256 word units in this embodiment) between the chips 1 to 4. Uses allocation.

The signal in the figure indicates that ALE is "Address.
Latch Enable signal, CLE is "Clear" signal, WR
Is "Write" signal, CE (1-4) is "Channel End"
Signal, RDY / BSY is "Ready / Busy" signal, OE
Is "Operation End" signal, REG is "Regeneratio"
Abbreviation for n ”signal.

FIG. 3 is a timing chart showing the state of each chip during high speed writing in this embodiment, and FIG. 4 is a timing chart showing the state of each chip during reading.

First, the characteristics of the high speed write operation will be described.
That is, the write command is executed every time when the data transfer in the block unit is completed assuming that the write is executed from the chip 1. Data for 4 chips (256 x 4 words)
When the writing is completed, each chip is in the writing operation, and the system waits for the opportunity of the next data transfer while watching the RDY / BSY signal of the card. In this case, RD
The Y / BSY signal outputs the RDY / BSY1 signal of the chip 1 as it is.

By monitoring the RDY / BSY1 signal of the chip 1, the order of writing the data from the system side to each chip is as follows: chip 1 → chip 2 → chip 3 → chip 4 → chip 1 → chip 2 → ... Thus, data writing can be performed efficiently.

The reason why the state during the write operation of each chip can be monitored is that, for example, when it is desired to transfer data to the chip 2 after executing the write operation of the chip 1.
This is because data transfer to the chip 2 cannot be performed unless it is known whether the writing to the chip 2 is completed.

As a method of each chip select at the time of writing, a method of switching the chip select every time the address setting means and the write command are input is adopted.

Next, the read operation will be described. The address setting to the card at the time of reading is the same as the setting at the time of writing. As a peculiar operation at the time of reading,
The RDY / BSY signal output from the card is output to the RD of each chip.
Y / BSY (1 to 4) signal outputs are logically ANDed, and the chip select inside the card is set every time the address setting means and the OE signal are input in the number of blocks (256 in this embodiment). The point is that the chip select is switched to. However, in this case, the OE signal input to read the status of the card is not counted.

The reason why the output of the RDY / BSY signal is the output of the signal which is the logical product of the RDY / BSY (1 to 4) signal outputs of the respective chips is that in the case of the flash EEPROM,
The read operation is considerably faster than the write operation, and it is faster to read the RDY / BSY signals for all four chips than to read the status for each chip whether reading is in progress. This is because the load will be lighter.

In this embodiment, the memory allocation is as shown in FIG. 2 in order to enable high speed writing. Therefore, in order to erase data in a unit of data, it is desirable to use a block unit that spans a plurality of chips as an erase unit. Therefore, in this embodiment, the minimum data erasing unit is

[0056]

[Equation 1] (Number of chips in card) × (Number of data in block) ×
(n: natural number), the minimum defect management unit on the card is set to be the same as the minimum data erasing unit, and the defect management information is stored in a different type of memory inside the card.

[0057]

As described above, the memory card of the present invention has a plurality of EEPRs according to the structure of claim 1.
Since it is possible to monitor whether or not the writing operation is being performed for each chip in the OM chip, it is possible to write efficiently and at high speed.

According to the second aspect of the invention, since the monitor is performed from the chip that first started writing, for example, writing can be performed at a higher speed than in the case where a signal obtained by taking a logical product is output to the outside.

According to the third aspect of the present invention, the writing state of each chip inside the card can be monitored by the card data bus, so that writing can be performed more efficiently.

According to the structure described in claim 4, since the write command can be set for each chip independently, it is possible to write at a higher speed.

According to the structure of claim 5, at the time of writing, by implementing the chip select function inside the card, it is possible to reduce the load on the system side for accessing.

According to the sixth aspect of the invention, the chips can be selected so that continuous block reading can be performed, so that reading can be performed efficiently and at high speed.

According to the structure of claim 7, it is possible to reduce the address setting cycle from the system side, and it is possible to perform a faster card access.

According to the eighth aspect of the present invention, the command setting cycle from the system side can be reduced and a faster card access can be performed.

According to the ninth aspect of the invention, since the status of each chip can be monitored, fine control can be performed from the system side.

According to the structure of the tenth aspect, it is possible to efficiently read the signal indicating the read state.

According to the eleventh aspect, the load on the system side can be reduced by realizing the chip select function inside the card at the time of reading.

According to the twelfth aspect, the operating state of the memory card can be monitored without adding a new signal line, so that the load on the system side can be reduced.

According to the thirteenth aspect, the means for selecting each chip can be automatically switched between the write operation and the read operation, so that the load on the system side can be reduced.

According to the structure described in claim 14, since the address change to the memory card seen from the system side can be made continuous even when accessing across the chips, the system side can perform even if high speed writing is performed. File management in cluster units can be facilitated.

According to the structure described in claim 15, even when the access is performed across the chips when the parallel writing is performed, the address change can be made continuous and the file management on the system side can be facilitated. .

According to the structure of claim 16, high speed erasing can be performed by setting the block unit spanning a plurality of chips as the minimum data erasing unit, and the continuity of the recorded data on the memory card can be maintained.

According to the structure described in claim 17, by setting the minimum data erasing unit as a defective area, the load of file management on the system side can be reduced.

According to the structure of claim 18, the data in the defective area can be stored in another memory area, so that the file management with high safety and reliability can be performed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of a main part in an embodiment of a memory card of the present invention.

FIG. 2 is an explanatory diagram of memory allocation in this embodiment.

FIG. 3 is a timing chart showing a state of each step at the time of writing in the present embodiment.

FIG. 4 is a timing chart showing a state of each step at the time of reading in the present embodiment.

[Explanation of symbols]

1 to 4 ... EEPROM chip, 5 ... Chip select section.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G11C 16/06 H04N 5/907 7916-5C

Claims (18)

[Claims] 1. An EEPR capable of reading and writing in block units
A memory card equipped with a plurality of OM chips has a means for controlling a plurality of blocks in parallel writing in order to realize high-speed writing, and can output a signal indicating that a writing operation is in progress to the outside of the card. A memory card that can monitor whether or not writing is in progress for each chip. 2. The memory card according to claim 1, wherein a writing state of a chip which first started writing a signal for outputting a writing operation to the outside of the card can be monitored. 3. The memory card according to claim 1, wherein a write operation state of each chip can be monitored from a card data bus. 4. The memory card according to claim 1, further comprising means capable of independently setting a write command to each chip. 5. The device according to claim 4, further comprising means for performing chip enable switching to each chip based on the count value of the write command in order to perform continuous write operation in units of a plurality of blocks at the time of writing. Memory card. 6. An EEPR capable of reading and writing in block units
A memory card having a plurality of OM chips, comprising means for selecting the chips to enable continuous block reading. 7. The memory card according to claim 1, wherein the address setting means for each chip is common to each chip. 8. The memory card according to claim 1, wherein a command setting means for setting a specific command to each chip is common to each chip. 9. The memory card according to claim 1, further comprising means capable of setting a command for observing the status of each chip independently for each chip. 10. A signal obtained by ANDing the read operation state signals of each chip as a signal indicating that the card is reading data, and outputting the signal to the outside of the card for monitoring. Memory card. 11. A means for performing chip enable switching to each chip each time a set number of blocks of a data read signal to be inputted to the card are counted in order to perform continuous read operation at the time of reading. 7. The memory card according to claim 6, wherein the memory card is a memory card. 12. A card terminal for monitoring the operation state signal according to claim 2 and claim 10 can be commonly used,
Moreover, the memory card is provided with a means for switching the monitor signal between writing and reading. 13. A memory card, characterized in that the means for switching chip enable according to claim 5 and claim 11 can be switched between writing and reading. 14. An EEP capable of reading and writing in block units
In a memory card equipped with multiple ROM chips,
A memory card comprising means for allocating an address to each chip so that an address change from an access side when accessing over a plurality of chips is continuously changed. 15. The memory card according to claim 14, wherein the number of chips mounted is an even number. 16. The memory card according to claim 14, wherein the minimum number of data erasing units is set to the product of the number of card internal chips, the number of block data and an arbitrary number. 17. The memory card according to claim 16, wherein when a bit in any of the chips has a defect, the entire minimum data erasing unit including the bit is set in a defect area. 18. The memory card according to claim 17, further comprising a memory area capable of storing data of the defective area.