JPH06324857A - Computer system - Google Patents

Abstract

PURPOSE:To simplify work for program correction by rewriting a boot block in an EEPROM without exchanging chip memory. CONSTITUTION:When a boot block rewriting unit 44 is connected to a system bus 10 via an extended bus connector 43, access to a flash EEPROM 100 is disabled. Thereby, a system address from a CPU is sent to the ROM 201 of the boot block rewriting unit 44, then, the ROM 201 is accessed. As a result, a reloading program stored in the ROM 201 is executed by the CPU, and processing to rewrite a boot block area is started. Therefore, the content of a boot block can be corrected without exchanging the flash EEPROM 100 even when the boot block that is a program to be executed first when a system is started up is destroyed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to a computer system using a rewritable ROM such as a flash EEPROM as a system ROM.

[0002]

2. Description of the Related Art Generally, a computer system such as a personal computer has a system ROM (read only memory) for storing a BIOS (basic input / output program). Conventionally, when the contents of the system ROM are destroyed or when the contents of the BIOS are upgraded, it is necessary to disassemble the computer system and replace the system ROM.

By the way, in recent years, rewritable RO
As M, a flash EEPROM has been developed.
The flash EEPROM has various advantages such as erasing stored data in blocks. For this reason,
Recently, a configuration in which a flash EEPROM is used as a system ROM and a BIOS is rewritable has begun to be adopted.

In this case, it is necessary to store a program for checking the contents of the BIOS in the system ROM composed of the flash EEPROM. This program is the first program to be executed at system startup prior to the execution of BIOS,
It is called a boot block.

In a system using such a flash EEPROM, rewriting of the BIOS is performed in the following procedure. That is, when the system is powered on, the boot block program of the flash EEPROM is first started and the BIOS is checked. If the content of the BIOS is abnormal, the fact is presented to the user. Then, the program is transferred from the floppy disk in which the correct BIOS is stored to the flash EEPROM, and the BIOS of the flash EEPROM is
S is rewritten.

It is a great advantage of using the flash EEPROM that such rewriting of the BIOS can be performed without disassembling work even after the product is shipped. However, since the program of the boot block of the flash EEPROM is executed first when the system is booted, if the contents of the boot block are destroyed, not only the contents of the BIOS cannot be checked,
There is also a problem that the system cannot be started. Therefore, if the contents of the boot block area are destroyed, the flash EEPROM itself must be replaced.

[0007]

In the conventional system,
If the program in the EEPROM that is first executed when the system is started up is destroyed, the program cannot be restored, so the EEPROM must be replaced.

The present invention has been made in view of the above points, and EEPRO which is first executed when the system is started up.
Even if the program in M is destroyed, its EEPR
It is an object to provide a computer system capable of repairing the program without replacing the OM.

[0009]

A computer system according to the present invention includes a CPU, a system bus connected to the CPU, and a predetermined first address range of the system address space connected to the system bus. And an EEPROM having a boot area in which a program to be executed first at system startup is stored,
A memory device having a storage area that is mapped to the same first address range as the boot area, in which a rewriting program for restoring the contents of the boot area is stored. A memory device removably connected to the system bus; means for detecting whether or not the memory device is connected to the system bus; and the EEP when the connection of the memory device is detected.
Means for disabling access to the ROM and the CP
Means for read-accessing the memory device with a system address designating the boot area output from U and causing the CPU to execute the rewriting program; and a boot area of the EEPROM different from the first address range. Remapping to two address ranges and enabling access to the EEPROM through the second address range.

In this computer system, when the memory device is connected to the system bus, the EEPROM
Access is disabled. This allows the CPU
When a system address belonging to the first address range is issued by the, the system address is sent as it is to the memory device via the system bus, and the memory device is read-accessed. As a result, the rewriting program stored in the memory device is executed by the CPU, and the process for rewriting the boot area is started. In this case, EEP
The boot area of the ROM is remapped to the second address range so that the address does not overlap with the memory device and is write-accessed through the address range. Therefore, even if the boot area, which is the first program executed when the system is started up, is destroyed, the contents of the boot area can be restored without replacing the flash EEPROM.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the system configuration of a portable computer according to an embodiment of the present invention. This portable computer is a laptop type or notebook type computer and includes a memory bus 1, a system bus 10, a CPU 11, and an I / O gate array 11A.
And the additional memory 13 are optionally connected.

The CPU 11 controls the entire system, and has a function of displaying various operation menus on the screen and a function of executing various processes designated by the user on the operation menu screen. .

The I / O gate array 11A performs control for various memories and I / O access, and bus cycle control. The main memory 12 stores programs and data to be processed. This main memory 12 has a storage capacity of 2 Mbytes, for example, and 640 Kbytes of the first 1 Mbyte is used as system memory,
The remaining 384 Kbytes are used as a work area. In addition, a part of 2M bytes of the main memory 12 excluding the above-mentioned system memory area is a hard RAM.
Or EMS memory. Expansion memory 13
Is a memory card of 2 Mbytes / 4 Mbytes / 8 Mbytes, which is mounted as needed for memory expansion. It is also possible to set the above-mentioned hard RAM or EMS memory in the memory area expanded by this additional memory 13.

A DMA controller (direct memory access controller) 14, an interrupt controller 15, a timer 16, a real time clock 17 and a backup RAM 18 are connected to the system bus 10.
The real-time clock 17 is a timepiece module having its own battery for operation, and has a static RAM of CMOS configuration in which power is constantly supplied from the battery.
This static RAM is used to store setup information indicating the system configuration and the like. Backup RAM
18 is a battery-backed memory,
It has a storage capacity of 32 Kbytes. The backup RAM 18 stores system environment setting information (CONFIG, SYS) set by the user.

The system bus 10 further includes a Chinese character RO.
M19, dictionary ROM20, DOSROM21, application ROM22, printer firmware ROM2
3, user ROM 24, outline font ROM 2
5, printer buffer RAM 26, and menu RO
M27 is connected.

The Kanji ROM 19 has a storage capacity of 1 Mbyte (64 Kbytes × 16 pages), and various Kanji fonts are stored therein. Dictionary ROM20
Has a storage capacity of 512 Kbytes (64 Kbytes × 8 pages) and stores a Kanner-Kanji conversion dictionary. The DOSROM 21 has a storage capacity of 512 Kbytes (64 Kbytes × 8 pages).
An operating system such as S (Disk Operating System) is stored in advance. Also, this DOS
The ROM 21 stores a menu display program as an automatic execution batch file that is executed when the operating system is activated.

The application ROM 22 is 512K
It has a storage capacity of bytes (64 Kbytes × 32 pages) and has a memory area in which a spreadsheet program is stored and a memory area in which a word processing program is stored.

The printer firmware ROM 23 has 2
It has a storage capacity of 56 Kbytes (64 Kbytes × 4 pages), and stores therein firmware for controlling the built-in printer 36 and firmware for developing character fonts such as outline fonts.
The user ROM 24 is connected to the system bus 10 via an IC socket, and is mounted by the user as needed. This user ROM 24 is, for example, O
It is composed of a TPROM.

The outline font ROM 25 is 8M
It has a storage capacity of bytes (64 Kbytes × 128 pages), in which outline fonts of various typefaces are stored. As for the font source of the outline font, plural kinds of fonts are prepared for each character type so that an appropriate font can be selected according to the character size to be used. The printer buffer RAM 26 is 2M
It is realized by utilizing a 32 Kbyte area in a byte SRAM, and print data is expanded therein.

The menu ROM 27 has a storage capacity of 640 Kbytes (64 Kbytes × 10 pages), in which the icons displayed on the menu screen and PIM programs for managing personal information such as schedules and address books are stored. It is stored.

Here, these Kanji ROM 19 and dictionary RO
M20, DOSROM21, application ROM2
2. Printer firmware ROM 23, user ROM
24, the outline font ROM 25, the printer buffer RAM 26, and the menu ROM 27 are configured to be selectively accessed through an EMS window dedicated to ROM access mapped to a predetermined system address.

A system ROM 28, an FDD controller 29, a printer controller 30, an RS-232C controller 31, a keyboard controller 32, and a display controller 33 are further connected to the system bus 10.

The system ROM 28 has a storage capacity of, for example, 128 Kbytes, and various basic input / output programs (BIOS; Basic I / O System) are stored therein.
em) and a boot block in which a program for checking the contents of the BIOS is stored. This system ROM 28 is actually one flash EEPROM 100 of 1 Mbyte together with the printer firmware ROM 23, the menu ROM 27, and the system ROM 28 described above.
Is realized by. This flash EEPROM
Details of 100 will be described later with reference to FIG.

The FDD controller 29 controls a floppy disk drive (FDD) 38 which drives a 3.5 inch floppy disk. The floppy disk drive (FDD) 38 is a three-mode drive that supports three types of recording formats of 720 Kbytes / 12 Mbytes / 1.44 Mbytes. The FDD controller 29 also controls, for example, a 5-inch floppy disk drive optionally connected via the FDD / printer connector 39. The printer controller 30 is
It controls an external printer that is optionally connected through the FDD / printer connector 39. The RS-232C controller 31 controls the RS-232C device. The keyboard controller 32 controls the built-in keyboard 40 of 85 keys and the mouse. The display controller 33 performs read / write control of the image memory (VRAM) 34 and display control of the monochrome liquid crystal display 41 having a resolution of 640 × 400 dots.

The portable computer also includes a built-in printer controller 35 and a built-in printer 36.
Is equipped with. The built-in printer controller 35 is for controlling the built-in printer 36, and is connected to the I / O gate array 11A. Built-in printer 36
Is built into this portable computer body.
It is a 6-dot serial thermal transfer printer. An automatic paper feeder for postcards can be connected to the built-in printer 36.

Further, this portable computer is
A power controller 42 for supplying operating power and backup power to each of these units is provided, and a 2.5-inch built-in hard disk pack 37 is optionally installed. The hard disk pack 37 includes a hard disk drive (HDD) and a hard disk drive controller (H
DC) is provided.

An extension bus connector 43 is further connected to the system bus 10. The expansion bus connector 43 is for connecting an expansion unit for function expansion to the system bus 10. Here, for example, a boot block rewriting unit 44 for rewriting the boot block is mounted. can do.
The boot block rewriting unit 44 is a system RO.
The ROM has a ROM configured to be addressed by a system address belonging to the same address range as the boot block of the M28, and the ROM stores a program for rewriting the boot block of the flash EEPROM 100.

Next, referring to FIG. 2, the flash EEP
A configuration example of the ROM 100 will be described. Flash EEPR
The OM100 has a storage capacity of 1M bytes of 1M × 8 bit configuration and has a 24-bit wide system address A.
Addressed by a 20-bit wide address A19-0 in 23-0. That is, the flash EE
PROM 100 has physical addresses from 00000H to FF
A 1 Mbyte address space up to FFFH is allocated. In this flash EEPROM 100, an area of 896 Kbytes from physical address 00000H to DFFFFH is an area used for the above-mentioned printer firmware ROM 23 and menu ROM 27, in which printer firmware, menu information, and PIM information are stored. There is. A 128 Kbyte area from the physical address E0000H to FFFFFH is an area used for the system ROM 28, and a 64 Kbyte area from the physical address EOOOOH to EFFFFH is a system BIOS in the 128 Kbyte area. System B in which is stored
Used as IOS area, physical address FC000H to FFFFFH in the remaining 64 Kbyte area
The 8 Kbyte area up to is used as a boot block area in which a boot block is stored.

The boot block is a program for executing the minimum functions for controlling the system, and as shown in the figure, a far jump instruction and a CRC (Cyclic Redundancy) for checking the contents of the system BIOS.
Check) routine and flash EEPROM 10
Routine for address translation to 0, and BI
It is composed of an OS transfer routine. The BIOS transfer routine is the rewriting routine used for rewriting the system BIOS, and is the floppy disk drive (FDD) 2
8 is a program for transfer to the main memory 12. The far jump instruction is stored at a storage position (here, the start address FFFF0 in this case) which is first addressed by the CPU 11 after the CPU 11 is reset.
H), and this far jump instruction is executed first. The jump destination of this far jump instruction indicates a CRC routine. The address conversion routine is for replacing the addresses of the boot block area and the system BIOS area, and details of this address conversion will be described later with reference to FIG.

Next, an example of a memory map managed by the CPU 11 of the portable computer shown in FIG. 1 will be described with reference to FIG. As shown in the figure, the system ROM 28 is mapped in the 64-Kbyte system address space from the system address F0000H to FFFFFH. The CPU 11 accesses the system ROM area of the flash EEPROM 100 via the space of 64 Kbytes from F0000H to FFFFFH.

Since the system ROM area of the flash EEPROM 100 has a size of 128 Kbytes as described above, the system addresses F0000H to FFF are used.
In the 64Kbyte space up to FFH, system BIOS
The S area and the boot block area are selectively mapped.

That is, when the system is booted, the boot block area is mapped to the space from the system address F0000H to FFFFFH in order to check the contents of the system BIOS before executing the system BIOS. On the other hand, after the BIOS check is completed, the system BIOS area is normally mapped in the 64 Kbyte space from the system address F0000H to FFFFFH.

Hereinafter, with reference to FIG. 4, the flash EEP
Details of address allocation to the ROM 100 will be described. As shown in Figure 4, at system startup,
24-bit wide system address A2 from CPU 11
20-bit wide system address A1 for addressing the flash EEPROM 100 within 3-0
9-0 is a flash EE as it is as a physical address.
It is supplied to the PROM 100. As a result, the boot block area and the spare area of the flash EEPROM 100 are mapped in the 64 Kbyte space from the system address F0000H to FFFFFH. Also,
In this case, the system BIOS area is mapped in the space of 64 Kbytes from the system address E0000H to EFFFFH, but since the area is used for accessing the backup RAM and the like, access of the system BIOS area is disabled. It

On the other hand, after execution of the boot block (during normal operation), a 20-bit wide system address A19 for addressing the flash EEPROM 100 is provided.
After the logic of bit 16 (A16) in -0 is inverted,
The 20-bit wide system address A19-0 including the inverted A16 is the flash EE as the physical address.
It is supplied to the PROM 100. The inversion process of the address A16 is performed in the boot block address conversion routine.

The address A16 = "0" designates the segment address E, and the address A16 = "1" designates the segment address F. Therefore, when the logic of the address A16 is inverted, the addresses of the system BIOS area and the boot block area are replaced with each other. As a result, after the inversion of A16, the CPU 11 passes through the space from the system address F0000H to FFFFFH to the system B of the flash EEPROM 100.
You can refer to the IOS area.

Further, in this case, the boot block area is mapped in the space of 8 Kbytes from the system address EC000H to EFFFFH, but since the area is used for access to the backup RAM or the like, it is usually that area. Boot block access through the address space is disabled. However, when rewriting the boot block, the boot block window can be opened in the space of 8 Kbytes from the system address EC000H to EFFFFH.

Thus, the flash EEPROM 10
The system BIOS area 0 and the boot block area 0 are exchanged with each other by the inversion processing of the address A16, and the boot block is mapped in the space from the address F0000H to FFFFFH for the system ROM access at the time of system startup.
After the check of (1) is completed, the system BIOS is mapped in the space.

FIG. 5 shows a flash EEPROM 100.
The peripheral hardware configuration and the configuration of the boot block rewriting unit 44 are shown. As described above, a great advantage of using the flash EEPROM 100 is that the program such as the system BIOS and the bird-up can be repaired even after the product is shipped without disassembling work. However, as described above, the boot block of the flash EEPROM 100 is a program that is first executed when the system is started, so if the contents of the boot block area are destroyed, the contents of the system BIOS cannot be checked. Not only that, there is a problem that the system cannot be started.

Therefore, in the configuration of FIG. 5, the master signal (MAST) of the system bus 10 is used to temporarily prohibit access to the flash EEPROM 100, and control is transferred to the external ROM 201 to rewrite the boot block. I have to.

The specific circuit configuration will be described in detail below. The flash EEPROM 100 is supplied with the chip select signal CS1 from the I / O gate array 11A via the chip select signal line 401. The chip select signal CS1 is activated when the value of the system address belongs to the range of addresses F0000H to FFFFFH. A programming power supply (PRG) of, for example, + 12V is supplied to the programming power supply terminal (VPP) of the flash EEPROM 100 via the programming power supply line 402. The programming power source (PRG) is generated during a programming operation for rewriting the contents of the flash EEPROM 100.

Further, the output enable terminal (OE) and the write enable terminal (WE) of the flash EEPROM 100 are connected to the memory read signal (MEMR) line 101a and the memory write signal (ME) of the system bus 10.
(MW) line 101b. The A16 terminal of the 20-bit width address input terminals of the flash EEPROM 100 is connected to the I / O terminal via the signal line 403.
Address A16 output terminal of gate array 11A (RM1
6), and the remaining 19-bit terminals are the address bus (A23-0) 10 excluding the system address A16.
It is connected to the lower 20 bits of 2 (A19-17, A15-0). Furthermore, the flash EEPROM 100
Data input / output terminal is the data bus (SD15-0) 10
3 are connected to the lower 8 bits (SD7-0). I
/ O gate array 11A address A16 output terminal (R
M16) shows the system address A at system startup.
16 is output to the signal line 403 as it is, and after the boot block program is executed or when the boot block is rewritten, the logic of A16 of the system address is inverted and output to the signal line 403.

The boot block rewriting unit 44 is
It is composed of a ROM 201 and a master signal (MAST) generation circuit 202. The boot block rewriting unit 44 is connected to the system bus 10 via the expansion bus connector 43 as described above. When the boot block rewriting unit 44 is attached to the expansion bus connector 43 as shown in the figure, the output enable terminal (OE) of the ROM 201 is connected to the memory read signal (MEMR) line 101a of the system bus 10, and Address input terminal is address bus (A23-0) 10
2 to the lower 16 bits (A15-0) and the data terminal to the lower 8 bits (SD15-0) 103 of the data bus (SD15-0) (SD
7-0).

As shown in FIG. 6, the ROM 201 has a storage capacity of 64K bytes having a structure of 64K × 8 bits and is addressed by a 16-bit width address A15-0. That is, the ROM 201
64 from physical address 0000H to FFFFH
A K-byte address space is allocated, and the ROM 201 is mapped to a 64-K-byte space from the system address F0000H to FFFFFH by this physical address allocation.

The ROM 201 stores a far jump instruction, an address conversion routine, a boot block window open routine, a boot block transfer routine, and a new boot block.

The address conversion routine is executed by the flash EE.
The boot block area of the PROM 100 is the ROM 201.
In order to avoid overlapping with the address of A, the system address A16 is logically inverted. By the logical inversion of A16, the boot block area of the flash EEPROM 100 is assigned to the address EC000H.

The boot block window open routine is for opening a boot block window for accessing the boot block area of the flash EEPROM 100. This boot block window is from the system dress EC0000H to EFFFF.
It is assigned to the H range. That is, normally, the value of the system address is from address F0000H to FFFFF.
Flash EEPROM 100 only when it belongs to H range
The chip enable signal CS1 of the device is activated, but when the boot block window is opened, the value of the system address is the address EC0 corresponding to the window.
000H to EFFFFH, the chip enable signal CS of the flash EEPROM 100 is also included.
1 is activated. As a result, the boot block of the flash EEPROM 100 can be accessed through the boot block window.

The boot block transfer routine is stored in ROM2.
01 is a program for writing the contents of the new boot block stored in 01 into the boot block area of the flash EEPROM 100. By executing this program, the boot block of the flash EEPROM 100 is rewritten. Like the boot block of the flash EEPROM 100, the new boot block stored in the ROM 201 includes a far jump instruction, a CRC routine, an address conversion routine, a BIOS transfer routine, and the like.

The far jump instruction is stored in a storage position (here, the start address F in this case) which is first addressed by the CPU 11 after the CPU 11 is reset.
FF0H), and this far jump instruction is executed first. The jump destination of this far jump instruction indicates the address conversion routine of the ROM 201.

In FIG. 5, the master signal generation circuit 202
Is connected to the reset (RESET) signal line 104 and the master (MAST) signal line 105 of the system bus 10, and is reset (R) from the I / O gate array 11A.
For a certain period after the ESET signal is generated, the master (MA
ST) signal is generated. This master (MAST) signal indicates that the boot block rewriting unit 44 is mounted by I / O.
It is used to notify the O gate array 11A. In addition, the master signal generation circuit 202 is reset (RESE
The chip enable signal of the ROM 201 is activated in response to the T) signal.

Next, referring to FIG. 7, a hardware configuration for controlling the flash EEPROM provided in the I / O gate array 11A will be described. As shown, the I / O gate array 11A includes a flash memory control register 501, a system ROM enable register 502, an A16 inversion circuit 503, first and second address range determination circuits 504 and 505, and a program power supply output circuit 506. A master signal detection circuit 507 and a reset signal generation circuit 508 are provided.

Flash memory control register 5
In 01, the program control flag (PR
G), address inversion control flag (INV) in bit 4,
The boot block window enable control flag (BBEN) is set to bit 0 by the CPU 11.

The program control flag (PRG) is a program power supply PROG for the flash EEPROM 100.
The program control flag (PRG) of "1" is set at the time of programming. The address inversion control flag (INV) is the address A
This is for designating the presence or absence of inversion of 16 and the address inversion control flag (INV) of "1" is set when the address A16 is inverted. The boot block window enable control flag (BBEN) is set to the flash EE.
This is for designating the opening of a window for accessing the boot block of the PROM 100, and the boot block window enable control flag (BBEN) of "1" is set when the boot block window is opened.

Flash memory control register 5
The values of these flags of 01 are reset to the initial value "0" by the power-on reset signal from the power supply unit 42.

System ROM enable register 502
Flash EEPROM after rewriting the boot block
A system BIOS enable flag (EN-BIS) is set in the bit 7 of the M100 by the CPU 11 to re-enable the access. "1" system BIOS enable flag (EN
-BIS) is set, addresses F0000H to FFFFFH provided by master detect circuit 507
The function of disabling access to the flash EEPROM 100 via the is reset.

System BIOS enable flag (EN
The value of (-BIS) is reset to the initial value "0" by the power-on reset signal from the power supply unit 42.
The A16 inversion circuit 503 is for performing the logical inversion of A16 of the system address A23-0 from the CPU 11, and the address inversion control flag (INV) =
When "1", A16 is inverted and output to the signal line 403,
A1 when the address inversion control flag (INV) = "0"
6 is output to the signal line 403 as it is.

The first address range determination circuit 504 is
The value of the system address from PU11 is the system ROM
Address range F0000H to FF for accessing
Whether or not it belongs to FFFH is determined, and if it belongs, the chip select signal CS1 is generated via the OR gate G1.
Although the operation of the address range determination circuit 504 is normally set to the enabled state, the master signal detection circuit 50
When a detection output is generated from 7, it is disabled thereby.

The second address range determination circuit 505 is C
The value of the system address from PU11 corresponds to the boot block window Address range EC0000H to E
Whether or not it belongs to FFFFH is determined, and if it belongs, a chip select signal CS1 is generated via the OR gate G1. The operation of the address range determination circuit 505 is based on the boot block window enable control flag (BBEN).
Is enabled only when is set to "1" and disabled otherwise.

The program power supply output circuit 506 has a voltage of 12V.
For selecting one of the power supply voltages VPP and GND of the above and outputting it as the program power supply PROG.
12V when the program control flag (PRG) = "1"
The power supply voltage VPP is selected.

The master signal detection circuit 507 is provided to detect whether or not the boot block rewriting unit 44 is attached when the power is turned on.
Sample the master signal (MAST) on the trailing edge of the power-on reset signal from 2. If a significant master signal (MAST) is generated for a certain period or longer, the master signal detection circuit 507 causes the boot block rewrite unit 4 to operate.
4 is attached, and the first address range determination circuit 504 is disabled.

Reset signal generating circuit 508 outputs a system reset signal in response to the power-on reset signal from power supply unit 42. Next, the boot block rewriting operation of the flash EEPROM 100 will be described with reference to FIGS.

When the boot block of the flash EEPROM 100 is destroyed or the boot block is upgraded, the boot block rewriting unit 44 is attached to the expansion bus connector 43.

When the power switch is turned on in this state, a power-on reset signal is generated from the power supply unit 42. In response to this power-on reset signal, I
The reset generation circuit 508 of the / O gate array 11A generates a system reset signal. This reset signal is
It is sent to the master signal generation circuit 202 of the boot block rewriting unit 44.

The master signal generation circuit 202 outputs a significant master signal (MA) for a certain period after the reset signal is cut off.
ST) is output. The master signal detection circuit 507 of the I / O gate array 11A samples the master signal (MAST) at the trailing edge of the power-on reset signal, and if it is significant for a certain period, detects the mounting of the boot block rewriting unit 44. Then, the first address range determination circuit 50
Disable 4. Thus, thereafter, even if a system address belonging to the range of addresses F0000H to FFFFFH is issued, the flash EEPROM 100
No chip select signal (CS1) is generated.

As a result, originally the flash EEPROM is
The system address (start address FFFFF0) for accessing the boot block of 100 is output to the address bus 102 of the system bus 10 as it is, and the ROM 20 of the boot block rewriting unit 44.
Sent to 1.

As a result, the ROM 201 is read-accessed by the system address for originally accessing the boot block of the flash EEPROM 100. Since the far jump instruction is stored in the physical address FFFF0 of the ROM 201, this far jump instruction is addressed and read by the CPU 11 and executed. Then, thereafter, the control shifts to the program of the ROM 201.

When control is transferred to the program of the ROM 201, first, the address conversion routine of the ROM 201 is executed, and the flash memory control register 501 is executed.
The address inversion control flag (INV) of "1" is set to. As a result, the A16 inversion circuit 503 is enabled, and the logic inversion of the address A16 is performed. By this logical inversion of the address A16, the boot block area of the flash EEPROM 100 is remapped in the range from the system address EC0000H to EFFFFH thereafter.

Next, the boot block window open routine of the ROM 201 is executed, and the boot block window enable control flag (BBEN) of "1" is set in the flash memory control register 501. As a result, the second address range determination circuit 5
05 is enabled and the boot block window is opened.

After that, when the value of the system address belongs to the range of addresses EC0000H to EFFFFH, the chip enable signal CS1 for the flash EEPROM 100 is generated, and the boot block access through the window becomes possible.

Thereafter, the boot block transfer routine of the ROM 201 is executed, and the program control flag (PR) of "1" is stored in the flash memory control register 501.
G) is set. As a result, the power supply voltage V of 12V
PP is flash EEP as a program power supply PROG
It is sent to the ROM 100. Then, the new boot block stored in the ROM 201 is transferred to the flash EEPROM 100 as write data, and the flash E
The program operation of the EPROM 100 is started. As a result, the contents of the boot block area of the flash EEPROM 100 are rewritten.

After the rewriting is completed, the boot block rewriting unit 44 is removed after the power is turned off, and the power is turned on again, so that the normal system starting process using the new boot block can be performed.

Also, the boot block rewriting unit 4
Even if 4 is attached, the master signal detection circuit 507 can be reset by setting the system BIOS enable flag of "1" in the system ROM enable register 502, so that normal system startup processing using a new boot block can be performed. You can This system BI
For setting the OS enable flag, for example, a program for setting the system BIOS enable flag to “1” after the end of rewriting the boot block is stored in the ROM 201.
It can be realized by storing in.

As described above, in this embodiment, when the boot block rewriting unit 44 is connected to the system bus 10 via the expansion bus connector 43, F0000H.
To flash EE via address range from ~ FFFFFFH
Access to PROM 100 is disabled. As a result, even if the system address belonging to the address range of F0000H to FFFFFH is issued from the CPU 11,
The flash EEPROM 100 is not accessed and instead the ROM of the boot block rewrite unit 44
201 is accessed. As a result, the program stored in the ROM 201 is executed by the CPU 11, and the process for rewriting the boot block area is started. In this case, the boot block area of the flash EEPROM 100 is EC00 by the inversion processing of A16 so that the address does not overlap with the ROM 201.
It is remapped to an address range of 0H to EFFFFH, and write access is performed through the address range.
Therefore, even if the boot block, which is the first program executed at system startup, is destroyed, the contents of the boot block can be restored without replacing the flash EEPROM 100.

Although a new boot block is stored in the ROM 201 in this embodiment, it is also possible to store only the transfer program in the ROM 201 and transfer the new boot block from the FDD or the like to the flash EEPROM 100. is there.

[0074]

As described above, according to the present invention, even if the program in the EEPROM which is first executed at the time of system startup is destroyed, the program can be restored without exchanging the EEPROM. Becomes

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall system configuration of a portable computer according to an embodiment of the present invention.

FIG. 2 is a diagram showing stored contents of a flash EEPROM provided in the system of the embodiment.

FIG. 3 is a diagram showing an example of a memory map in the system of the embodiment.

FIG. 4 is a flash EEP in the system of the embodiment.
The figure which shows an example of the address allocation with respect to ROM.

FIG. 5 is a flash EEP in the system of the embodiment.
FIG. 3 is a diagram showing a hardware configuration around a ROM and a configuration of a boot block rewriting unit mounted in the system.

6 is a diagram showing an example of stored contents of a ROM provided in the boot block rewriting unit shown in FIG. 5;

FIG. 7 is a diagram showing a circuit configuration for flash EEPROM control provided in the system of the embodiment.

[Explanation of symbols]

10 ... System bus, 11 ... CPU, 11A ... Bus controller, 28 ... System ROM, 43 ... Expansion bus connector, 44 ... Boot block rewriting unit. 100
... Flash EEPROM, 105 ... Master signal line, 2
01 ... ROM.

Claims (2)

[Claims] 1. A CPU, a system bus connected to the CPU, and a program which is connected to the system bus and is mapped to a predetermined first address range of a system address space and which is first executed at system startup are stored. An EEPROM having a boot area and a storage area mapped to the same first address range as the boot area, and a rewriting program for restoring the contents of the boot area is stored in the storage area. A memory device that is detachably connected to the system bus, means for detecting whether or not the memory device is connected to the system bus, and connection of the memory device is detected. When the EEPRO
M means for disabling access, M means for performing read access to the memory device by a system address that specifies the boot area output from the CPU, and causing the CPU to execute the rewriting program, and booting the EEPROM. Means for remapping an area to a second address range different from the first address range and enabling access of the EEPROM through the second address range. 2. A CPU, a system bus connected to the CPU, various I / O devices connected to the system bus, and an EEPROM connected to the system bus,
A system BIOS area in which a basic input / output program for controlling the I / O device is stored, and the contents of the system BIOS area for determining whether the system BIOS area is first executed when the system is booted. A boot area in which a program for checking is stored, and the boot area and the system BIOS area are respectively mapped to the first and second address ranges of the system address space; An expansion bus connector for connecting an expansion device and a storage area mapped to the first address range, and a rewriting program for restoring the contents of the boot area is stored in the storage area. A procedure including a ROM, which is detachably attached to the expansion bus connector. A program rewriting unit, means provided in the program rewriting unit, for outputting a signal indicating that the program rewriting unit is mounted on a predetermined signal line defined in the system bus, and the predetermined unit. Means for disabling access to the EEPROM through the first address range in response to a signal output supplied from the rewrite unit via the signal line and output from the CPU. Means for making a read access to the memory device by a system address designating the boot area and causing the CPU to execute the rewriting program; and the boot area and the system BIOS area having their address ranges exchanged with each other. Remap the area to the second address range and Computer system characterized by comprising means for the access of the EEPROM through the second address range enabled.