JPH06311532A - Jitter correction circuit for video signal - Google Patents

Abstract

(57) [Summary] [Purpose] To obtain the average correction coefficient from a plurality of phase difference data and remove the jitter of the video signal. A phase difference detection unit 1 that inputs a burst lock clock 6 and an H lock clock 7 and detects a phase difference between them, a coefficient generation unit 2 that generates a predetermined coefficient based on the phase difference, and Based on an averaging unit 3 for averaging, a delay unit 4 for counting the video signal 8 including jitter by the H lock clock 7 and delaying it by a predetermined clock time, and a coefficient for averaging the delayed video signal. The correction calculation unit 5 outputs the video signal 9 in which the jitter is corrected according to the phase of the burst lock clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal jitter correction circuit for removing jitter within one clock period.

[0002]

2. Description of the Related Art A color television signal transmitted from a broadcasting station is an NTSC system including a video signal for reproducing an image on a receiving side, a synchronizing signal for assembling a color image, a carrier color signal and a color burst. The composite video signal (standard signal) conforming to is used. For example, NTS
In the C method, since the composite video signal multiplexes the color signal in a part of the frequency of the luminance signal, interference (cross color, cross luminance) due to interference between the luminance signal (Y) and the color signal (C) is caused. Occurs. In high-definition televisions such as EDTV (Clear Vision), cross color and cross luminance interference are ideally improved by using a frame memory and a comb-shaped YC separation system that uses a PLL lock clock signal (burst lock clock) for color bursts. is doing. However, since color TV signals (non-standard signals) such as home video contain jitter, the phase of the color burst and the phase of the horizontal sync signal do not hold a fixed relationship,
There is no choice but to adopt a YC separation method between lines using a clock signal (H lock clock) locked to the horizontal synchronization signal by PLL. For this reason, the degree of improvement in the above-mentioned interference is the same as that of the conventional analog television. Conventionally, as a method of removing the jitter of the non-standard signal, “Electronic Technology 1991-
Jitter Removal L in the article "Multimedia Digital Video Processing LSI Family and Its Applications"
There is an explanation of SI. In summary, the phase difference between the horizontal synchronizing signal and the clock signal (burst lock clock) PLL-locked to the phase of the color burst is detected, and the clock signal is imaged based on the parameter normalized by the phase difference and the cycle of the clock signal. Combine the signals (Y signal in this case). However, the period for detecting the phase difference between the horizontal synchronizing signal and the clock signal is once in one horizontal scanning period, and if there is a detection error, it is necessary to wait until the next horizontal synchronizing signal.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is possible to detect a phase difference without fail within one horizontal scanning period of a video signal including jitter.
An object of the present invention is to provide a video signal jitter correction circuit that removes jitter by matching a video signal with a clock signal.

[0004]

In order to achieve the above object, a phase difference detecting section for inputting a burst lock clock and an H lock clock to detect a phase difference, and generating a predetermined coefficient based on the phase difference. A coefficient generating section, an averaging section for averaging the coefficients, a delay section for delaying the video signal by a predetermined clock time, and a correction for matching the delayed video signal with the phase of the burst lock clock based on the average coefficient. It consists of a calculation unit.

[0005]

With the above configuration, the phase difference between the H lock clock and the burst lock clock input by the phase difference detection unit is detected for each clock, and the coefficient generation unit generates a coefficient for each phase, and the average value is calculated. The calculation unit is based on a predetermined number of coefficients,
Calculate the average value of the coefficients. The correction calculation unit generates interpolation data that matches the sample time of the burst lock clock based on the sample data of the video signal delayed by the delay unit by the clock time corresponding to the predetermined number.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A jitter correction circuit for video signals according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a video signal jitter correction circuit according to the present invention. Reference numeral 1 is a phase difference detection unit that inputs the burst lock clock 6 and the H lock clock 7 and detects the phase difference between them. Reference numeral 2 is a coefficient generator that generates a predetermined coefficient for the jitter correction calculation based on the phase difference. 3 is an averaging unit that averages the coefficients. A delay unit 4 counts the video signal 8 including jitter with the H lock clock 7 and delays it by a predetermined clock time. Reference numeral 5 denotes a correction calculation unit that generates interpolation data matching the phase of the burst lock clock based on an averaged coefficient of the delayed video signal and outputs a video signal 9 in which jitter is corrected (removed).

FIG. 2 shows an embodiment of a correction operation section of the jitter correction circuit for a video signal according to the present invention. Reference numeral 10 is an input video signal including jitter. Reference numeral 12 is an averaged coefficient supplied from the average calculator 3. 11 is a correction calculation unit 5
Is a video signal in which the jitter obtained as a result of the calculation by the 1-clock delay (D), the logical sum (+), and the logical product (×) of the coefficients is corrected.

The operation of the video signal jitter correction circuit according to the present invention will be described. FIG. 3 is a time chart showing the phase difference between the burst lock clock and the H lock clock of the jitter correction circuit for the video signal according to the present invention. Reference numeral 20 is an H lock clock, and 21 is a burst lock clock. 22 is one clock cycle of the H lock clock 20 or the burst lock clock 21. 23 is a phase difference (jitter amount) between the H lock clock 20 and the burst lock clock 21. The two types of clocks are supplied to the phase difference detection unit 1.

FIG. 4 is a diagram illustrating the principle of a jitter correction circuit for a video signal according to the present invention. Reference numeral 30 is an input video signal including jitter. Reference numeral 31 samples the input video signal 30 including the jitter to obtain data A and data B.
Is an H lock clock. 32 is a video signal in which the data C is calculated from the data A and the data B by weighted averaging by the equation 35 for obtaining the interpolated data, and the phase is made coincident with the burst lock clock 33 (jitter corrected) interpolated by the data. Is. The phase difference detector 1 extracts the phase difference between the supplied burst lock clock 6 and H lock clock 7, the coefficient generator 2 generates a jitter correction coefficient based on the phase difference, and the average calculator 3
Calculates a correction coefficient average value according to a predetermined number of clocks. The delay unit 4 counts the input video signal 8 including the jitter with the H lock clock 7 and delays it by the clock time for calculating the correction coefficient average value, and the continuous 2
Interpolation data is sequentially obtained from two data, for example, data A and data B by weighted averaging, like data C,
Since the interpolated data is generated so that its phase matches the burst lock clock, the jitter of the video signal is corrected. The number of clocks for detecting the phase difference is
It may be appropriately set within several clocks to a maximum of 1H according to the fluctuation of the jitter. Also, since the delay time needs to match the corresponding clock time for detecting the phase difference, the delay element of the delay unit 4 can easily change the delay time by using a shift register. Further, the connection order of the coefficient generation unit 2 and the average calculation unit 3 may be exchanged.

[0010]

As described above, according to the present invention, the phase difference can be detected without fail within one horizontal scanning period of the video signal including jitter, and the interpolation data of the newly generated video signal is matched with the clock signal based on the phase difference detection. Thus, a jitter correction circuit for a video signal that removes jitter is provided. Therefore, there is an advantage that the jitter can be surely and quickly removed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a video signal jitter correction circuit according to the present invention.

FIG. 2 is an embodiment of a correction operation unit of a jitter correction circuit for a video signal according to the present invention.

FIG. 3 is a time chart showing the phase difference between the burst lock clock and the H lock clock of the video signal jitter correction circuit according to the present invention.

FIG. 4 is a diagram illustrating the principle of a jitter correction circuit for video signals according to the present invention.

[Explanation of symbols]

 1 Phase Difference Detection Section 2 Coefficient Generation Section 3 Average Calculation Section 4 Delay Section 5 Correction Calculation Section 6 Burst Lock Clock 7 H Lock Clock 8 Video Signal with Jitter 9 Video Signal with Jitter Corrected 10 Input Video Signal with Jitter 11 Video signal with jitter corrected 12 Averaged coefficient 20 H lock clock 21 Burst lock clock 22 1 clock period 23 Phase difference (jitter amount) 30 Input video signal including jitter 31 H lock clock 32 In phase (jitter Video signal 33 burst burst clock 35 Expression for obtaining interpolation data

Claims (2)

[Claims] 1. A phase difference detecting section for inputting a burst lock clock and an H lock clock to detect a phase difference, a coefficient generating section for generating a predetermined coefficient based on the phase difference, and an average for averaging the coefficients. A video signal, comprising: an arithmetic unit, a delay unit that delays the video signal by a predetermined clock time, and a correction arithmetic unit that matches the delayed video signal with the phase of the burst lock clock based on an average coefficient. Jitter correction circuit. 2. The jitter correction circuit for a video signal according to claim 1, wherein the delay unit is a shift register.