JPH06317812A - Active matrix element and its production - Google Patents

Abstract

PURPOSE:To provide an active matrix element which improves a pixel potential holding characteristic by decreasing off currents without degrading data writing characteristics and improves the opening rate of pixels and does not change its characteristics by writing charges no matter whether these charges are positive or negative by reducing the area of the storage capacitance parts of a liquid crystal and the process for production of the element. CONSTITUTION:This active matrix element and the process for production of the element consist as follows: Gate electrodes 4a, 4b are formed so as to cross the base side part of a square shaped semiconductor active layer 2. The lower parts of these gate electrodes 4a, 4b of the semiconductor active layer 2 are channel regions 2c, 2c'. Offset regions 2d, 2e are formed adjacently to the respective left sides of these channel regions 2c, 2c'. A data electrode 7 is connected to a high-density region 2f in the central part between the channel regions 2c and 2c' and pixel electrodes 8a, 8b are connected to high-density regions 2a, 2b at both ends of the semiconductor active layer 2. These pixel electrodes 8a, 8b are a common electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an active matrix element used in a liquid crystal display or the like, and particularly has a high pixel potential holding characteristic, a good data writing characteristic and a large aperture ratio of a pixel. The present invention relates to an active matrix device and a manufacturing method thereof.

[0002]

2. Description of the Related Art As an active matrix device of a liquid crystal display, for example, a thin film transistor (po-type) using a thin film of polycrystalline silicon (poly-Si) as a semiconductor active layer is used.
ly-SiTFT) is used. poly-Si TFT is
It is easy to form a large amount and evenly on an inexpensive glass substrate, and because of its high current drive capability,
It can be applied to a peripheral drive circuit, and has an advantage that a liquid crystal display can be formed at low cost.

The basic structure of a thin film transistor (poly-Si TFT) using polycrystalline silicon will be described with reference to FIG. FIG. 6 is a cross-sectional explanatory diagram of a poly-Si TFT. As shown in FIG. 6, a poly-Si TFT has a semiconductor active layer 2 made of polycrystalline silicon (poly-Si), a gate insulating layer 3, and a gate electrode 4 made of polycrystalline silicon on an insulating substrate 1. And an interlayer insulating layer 5 are sequentially laminated, and a source electrode 18 connected to the source region 2a through an opening provided in the interlayer insulating layer 5,
Similarly, a drain electrode 19 connected to the drain region 2b is provided.

Incidentally, the source region 2a and the drain region 2
b, and the gate electrode 4 is a region where the n-type impurity is implanted at a high concentration and the resistance is low. In addition, a portion between the source region 2a and the drain region 2b is a channel region 2c in which a channel is formed when the transistor operates.
Has become.

However, in the structure of the conventional poly-Si TFT described above, current leakage is likely to occur, resulting in a large off current, and when used as an active matrix element, the potential holding characteristic of the pixel deteriorates, and the This was one of the causes of deterioration of display characteristics.

Therefore, as an active matrix element for reducing the off current, one using a poly-Si TFT having a dual gate structure as shown in FIGS. 7 and 8 is known (B / W and Color LC Video). Displays Addressed
by Poly Si TFTs, SID 83 Digest, pp156-157). FIG. 7 is a plan explanatory view of one pixel of a liquid crystal display using a dual gate TFT as an active matrix element, and FIG. 8 is a sectional explanatory view of a BB ′ portion of FIG. 7.

An active matrix device using a dual gate TFT is formed on a substrate 1 by using polycrystalline silicon (poly-S).
i) semiconductor active layer 2 and silicon oxide (SiO 2
₂ ) and a gate insulating layer 3 composed of ₂ ) are sequentially laminated, and two gate electrodes 4a and 4b made of poly-Si or the like having a common gate line 14 are provided thereon, and the semiconductor active layer 2
In, the interlayer insulating layer 5 formed so as to cover the whole
A structure is provided in which a data electrode 7 connected to the data line 15 through an opening provided in the pixel electrode 8 and a pixel electrode 8 connected to the display pixel electrode 9 of the storage capacitor portion 11 are provided. That is, the dual-gate TFT has a structure in which two thin film transistors having gate electrodes 4a and 4b are connected in series between the data line 15 and the display pixel electrode 9.

In the semiconductor active layer 2, the portion to which the data electrode 7 or the pixel electrode 8 is connected is the source region 2a.
Alternatively, the drain region 2b is formed, and specifically, when the potential of the data line 15 is higher than the pixel potential of the pixel electrode 8 (+
Writing), the portion connected to the data electrode 7 is the drain region, the portion connected to the pixel electrode 8 is the source region, and when the pixel potential is higher than the potential of the data line 15 (writing −), the data electrode 7 is The connecting portion serves as a source region, and the connecting portion serves as a drain region.
7 and 8, the portion connected to the data electrode 7 is the source region, and the portion connected to the pixel electrode 8 is the drain region 2b.
I am trying.

Further, of the semiconductor active layer 2, the gate electrode 4
Impurities are not implanted into the channel regions 2c and 2c 'which are the lower layers of a and 4b, and the high concentration region 2f between the source region 2a, the drain region 2b and the gate electrodes 4a and 4b is formed.
Impurities are implanted at a high concentration into the region to form a region having low resistance.

The storage capacitor section 11 for writing charges as data includes a storage capacitor poly-Si layer 2'made of poly-Si formed on the substrate 1 and an insulating layer of a gate insulating layer 3 made of SiO _2. , Poly-Si storage capacitor electrode 10
, The interlayer insulating layer 5 made of SiO ₂ , and the storage capacitor portion 11
Indium tin oxide (I
The display pixel electrode 9 made of TO) is sequentially laminated, and the storage capacitor poly-Si layer 2'and the display pixel electrode 9 are connected to the pixel electrode 8 of the active matrix element. There is.

The active matrix element using the dual gate TFT having the above-mentioned structure distributes the potential difference between the data electrode 7 and the pixel electrode 8 which is generated at the time of off to the two thin film transistors connected in series to thereby obtain the electric field strength. To reduce the off current.

However, even if the dual gate TFT is used, the off-current can be suppressed to about 1/10 at most as compared with the active matrix element using the single TFT, and the pixel potential is retained. In order to
A large storage capacitor section 11 is required, and therefore Cr
The area of the storage capacitor electrode 10 must be increased,
Then, the aperture ratio is lowered, which is one of the causes of impairing the image quality.

As a method of further reducing the off current, there is an active matrix element using a thin film transistor having a gate offset structure or an LDD (Lightly Doped Drain) structure as shown in the sectional view of FIG. -74077). A TFT having a gate offset structure has a semiconductor active layer 2 of poly-Si, a gate insulating layer 3 of SiO ₂ , a gate electrode 4 of poly-Si, and an interlayer insulating layer 5 of SiO ₂ on a substrate 1 in order. An offset containing no impurities between the high-concentration regions 2a and 2b of the stacked semiconductor active layer 2 in which a high-concentration impurity is implanted and the channel region 2c directly below the gate electrode 4 in which no impurity is implanted. It is a thin film transistor provided with regions 2d and 2e. The TFT having the LDD structure is a thin film transistor in which impurities are added to the offset regions 2d and 2e at a low concentration.

The gate offset TFT and L having the above structure
In the TFT having the DD structure, the off-current is reduced by decreasing the impurity concentration of the semiconductor active layer on the drain side adjacent to the channel region 2c to increase the resistance and relaxing the electric field. Therefore, the lengths Ld and Le of the offset regions 2d and 2e, which are high resistance regions, are important factors in determining the characteristics of the TFT.

The gate offset TFT and L having the above structure
In the active matrix device using the DD structure TFT, the off current is 1 when the dual gate TFT is used.
It can be reduced to / 10 or less, and the area occupied by the storage capacitor portion 11 is 1/1 of that in the case of using the dual gate TFT.
Since a sufficient pixel potential can be obtained even if the pixel size is reduced to 0 or less, the whole pixel can be reduced and the aperture ratio can be dramatically improved.

When a gate offset TFT and a TFT having an LDD structure are used as an active matrix element, positive charges and negative charges are alternately stored in the liquid crystal capacitor, so that the data electrode 7 side has a high potential and the pixel electrode 8 side has a high potential. There are cases where the potential becomes high. Therefore, the high concentration regions 2a, 2
There are cases where b acts as a source and a case where it acts as a drain. Therefore, in order to obtain a TFT whose characteristics do not change even if the source and drain are inverted, the offset region 2d on the data electrode 7 side is used. It is necessary to form the same length Ld and the length Le of the offset region 2e on the pixel electrode 8 side.

Assuming that the length Ld of the offset area 2d is
When the lengths Le of the offset regions 2e are not formed equal, when the source / drain is inverted, the TFT characteristics before and after inversion do not become equal. The charge actually written differs from that when the negative charge is written, which impairs the display image quality.

In the manufacturing process of the above TFT, the length Ld of the offset region 2d and the length L of the offset region 2e.
e is a mask for forming the pattern of the gate electrode 4,
Since it is determined by two times of photolithography forming a resist mask at the time of high-concentration ion implantation for forming the high-concentration region, if the alignment shift occurs, the length of the offset region shifts from the design value. For example, when formed on a large screen substrate of about 6 inches square,
Usually, the offset length varies within ± 0.5 μm with respect to the design value.

Further, the gate offset TFT and the LDD
In the TFT having the structure, even if the length of the offset region on the high potential electrode (drain) side deviates from the design value, the effect on the on-current is small, but the length of the offset region on the low potential electrode (source) side shifts. Then, the on-current changes greatly, and the characteristics as designed cannot be obtained. For example, when the offset length on the source region side becomes 0.5 μm larger than the design value, the amount of charge injected into the channel region 2c through the high resistance offset region is significantly reduced, so that the ON current is It is reduced to about 1/10 of the design value.

[0020]

Therefore, in the active matrix device using the conventional gate offset TFT and the LDD structure TFT, the offset regions 2d,
Since the length of 2e is determined by photolithography twice, the length of the offset region varies due to misalignment and the like, and it is difficult to obtain the designed characteristics. If the offset length on the () side is longer than the design value, the on-current becomes small, and there is a problem that data writing to the liquid crystal pixels cannot be performed sufficiently.

Further, in the above-mentioned conventional active matrix device, it is difficult to form the offset regions 2d and 2e in the same length, and when the offset regions 2d and 2e are not formed in the same length, liquid crystal pixels are formed. When the source / drain is inverted depending on whether the accumulated charge is positive or negative, the TFT characteristics due to the electrode inversion do not become equal, so that the display characteristics of the display are impaired.

The present invention has been made in view of the above situation. The off current is reduced to improve the pixel potential retention and the area of the storage capacitor portion of the liquid crystal is reduced without impairing the data writing characteristics. It is an object of the present invention to provide an active matrix device which improves the aperture ratio of a pixel and whose characteristics do not change depending on whether the write charge is positive or negative, and a manufacturing method thereof.

[0023]

The invention according to claim 1 for solving the above-mentioned problems of the prior art, comprises a semiconductor active layer formed on a substrate and an insulating layer so as to cross the semiconductor active layer. In the active matrix element having the first and second gate electrodes formed via the above, an end high concentration region having a high impurity concentration is formed at both ends of the semiconductor active layer, and the end high concentration region is common. Connected to an electrode of the first gate electrode, the semiconductor active layer portion below the first gate electrode forms a first channel region that does not include impurities, and the semiconductor active layer portion below the second gate electrode includes impurities. A second channel region containing no impurities is formed, a central high-concentration region having a high impurity concentration is formed between the first channel region and the second channel region, and the central high-concentration region is separated. Connect to the electrode A first offset region having a low impurity concentration is formed between the first channel region and the end high concentration region, and an impurity concentration is formed between the second channel region and the central high concentration region. Is characterized in that a second offset region having a low

According to a second aspect of the present invention for solving the above-mentioned problems of the conventional example, a step of forming a semiconductor active layer on a substrate in a method of manufacturing an active matrix element,
Forming a first and a second gate electrode via an insulating layer so as to cross a side of the semiconductor active layer, and implanting a low concentration impurity using the first and the second gate electrode as a mask A step of forming a resist mask to cover one side portion of the same direction where the first and second gate electrodes are adjacent to each other and injecting a high concentration impurity, and a step of implanting a high concentration impurity into the side of the semiconductor active layer. Forming an electrode layer so as to connect the end high concentration region formed at the end to a common electrode; and implanting the high concentration impurity into the first and second gate electrodes on the side of the semiconductor active layer. And a step of forming an electrode layer so as to connect the central high-concentration region formed in the intervening part to another electrode.

[0025]

According to the first aspect of the invention, the offset regions adjacent to the first and second channel regions below the first and second gate electrodes are the same with respect to the first and second gate electrodes. Direction, the end high concentration region of the end of the semiconductor active layer is connected to a common electrode, and the center high concentration region between the first and second channel regions is connected to another electrode. Since the matrix element is used, the two offset regions have the same length even if misalignment occurs, and the two transistors formed by the two gate electrodes can have the same characteristics during operation.

According to the second aspect of the present invention, the first and second gate electrodes are formed so as to cross the sides of the semiconductor active layer, and low concentration impurity implantation is performed using these gate electrodes as masks. A high-concentration impurity implantation is performed by forming a resist mask so as to cover the adjacent part of the gate electrode in one direction, and as a result, the high-concentration regions at the ends of the sides of the semiconductor active layer are used as a common electrode. Since the active matrix element manufacturing method is such that the electrode layers are formed so as to connect and connect the central high-concentration region formed in the central portion of the side of the semiconductor active layer to the common electrode, even if misalignment occurs The lengths of the two offset regions of the low-concentration region formed under the resist mask are equal, and the two transistors formed by the two gate electrodes have the characteristic during operation. It can be made to be single.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan explanatory view of one pixel of a liquid crystal display using an active matrix element according to an embodiment of the present invention, and FIG. 2 is a sectional explanatory view of a portion AA ′ in FIG. The active matrix device of this embodiment is provided in a one-to-one correspondence with each pixel of a liquid crystal display arranged in a two-dimensional matrix, and as shown in FIGS. 1 and 2, on an insulating substrate 1, Polycrystalline silicon (poly
-Si) layer, the semiconductor active layer 2 and silicon oxide (S
A gate insulating layer 3 made of iO ₂ ) is sequentially laminated, and a gate insulating layer 3 made of poly-Si 2 having a common gate line 14 is formed thereon.
Two gate electrodes 4a and 4b are formed, and further an interlayer insulating layer 5 made of SiO ₂ is formed so as to cover the entire surface,
The data electrode 7 connected to the semiconductor active layer 2 is formed through the opening 6c provided in the interlayer insulating layer 5, and similarly, for displaying the storage capacitor portion 11 through the openings 6a and 6b of the interlayer insulating layer 5. The pixel electrodes 8a and 8b connected to the pixel electrode 9 are formed, that is, an active matrix element including two thin film transistors.

The poly-Si layer has a square V shape, and the upper side 2'corresponds to the lower portion of the storage capacitor electrode 10 in the square-shaped poly-Si layer. And a bottom portion is a semiconductor active layer 2 of the thin film transistor.
It is the part that acts as. In the semiconductor active layer 2, the channel region 2c below the gate electrode 4a and the channel region 2c ′ below the gate electrode 4b do not contain impurity ions, and the offset region 2d adjacent to the left side of the channel region 2c and the channel Impurities of low concentration are implanted into the offset region 2e adjacent to the left side of the region 2c ', and the length Ld of the offset region 2d and the length Le of the offset region 2e are formed to be equal. .

In the semiconductor active layer 2, the left side of the offset region 2d is a high concentration region 2a containing high concentration impurities,
The high concentration region 2b is on the right side of the channel region 2c ', and the high concentration region 2f is between the channel region 2c and the offset region 2e. That is, the TFT having the gate electrode 4a
(Thin film transistor) 1 and T having a gate electrode 4b
The FT2 is a thin film transistor having an LDD structure having offset regions 2d and 2e having a low impurity concentration on the left side of the channel regions 2c and 2c '.

As described above, the offset areas 2d and 2e
Are provided on the left side of the gate electrodes 4a and 4b, the offset regions 2d and 2e have the same length even if a slight misalignment occurs in the photolithography for forming the mask of high-concentration impurity implantation. Offset area 2d,
The length of 2e can be made equal.

The TFT 1 and the TFT 2 share the high concentration region 2f and are connected to the data line 15 via the data electrode 7 provided in the high concentration region 2f. The high-concentration region 2a of the TFT 1 is connected to the display pixel electrode 9 of the storage capacitor section 11 via the pixel electrode 8a, and similarly, the high-concentration region 2b of the TFT 2 is connected to the storage capacitor section via the pixel electrode 8b. 11 is connected to the display pixel electrode 9. Therefore, the TFT1 and the TFT2 are connected in parallel with each other between the data line 15 and the storage capacitor section 11. Further, the gate electrode 4a and the gate electrode 4b are formed to have the same length in the channel direction.
a and 4b are connected to a common gate line 14.

The TFT1 and the TFT2 have an offset region 2
The offset lengths in d and 2e, the channel lengths in the channel regions 2c and 2c 'below the gate electrode, the impurity concentrations in the offset regions and the high concentration regions, and the like are made equal, and show the same characteristics. is there. That is, the active matrix element of the present embodiment is one in which, in FIG. 1, two thin film transistors having the same characteristics and having an offset region on the left side of the gate electrode are connected in parallel with a common gate line. And 2
The gate electrodes 4a and 4b of the active matrix elements of each pixel arranged in a dimensional matrix are connected to a common gate line 14 for each row, and the data electrodes 7 are connected to a common data line 15 for each column.

Next, the manufacturing method of the active matrix device of this embodiment will be described with reference to FIGS. 3 (a) to 3 (e) and 4 (f).
This will be described with reference to the process explanatory diagrams of (i) to (i). Incidentally, FIG.
(A), (c), (d), and FIGS. 4 (f) and (h) are plan views, and FIGS. 3 (b), (e), and 4 (g) and (i) are A in the corresponding plan views. It is a section explanatory view of a -A 'portion. First, a poly-Si layer is deposited on the insulating substrate 1, and is patterned into a square shape by photolithography and etching to form a poly-Si layer under the storage capacitor electrode and the semiconductor active layer 2 of the active matrix element. To form (Fig. 3
(See (a) and (b)).

Next, a portion other than the storage-capacitor poly-Si layer 2'under the storage-capacitor electrode 10 is covered with a resist, impurity ions are implanted, and the storage-capacitor poly-Si layer 2'has a low resistance. It is a layer (see FIG. 3C). Note that this impurity implantation step can be omitted.

Then, an insulating layer such as silicon oxide (SiO ₂ ) is deposited to form a gate insulating layer 3, and a gate insulating layer 3 is formed thereon.
-Si is deposited and patterned by photolithography and etching to form the gate electrodes 4a and 4b, the gate line 14, and the storage capacitor electrode 10 (FIG. 3).
(See (d) and (e)).

Next, using the gate electrodes 4a and 4b as a mask, low-concentration impurity implantation is performed on the entire surface of the substrate with the impurity concentration of the offset regions 2d and 2e (first impurity implantation). Although this step can be omitted, it is preferable to perform this step in order to increase the on-current by controlling the resistance of the offset regions 2d and 2e.

Further, resist masks 17a and 17b are formed so as to cover the offset regions 2d and 2e, and high-concentration impurities are injected from above (second impurity injection) to form high-concentration regions 2a, 2b and 2f. (Fig. 4 (f))
(See (g)). Here, since the second impurity implantation is not performed on the portions below the gate electrodes 4a and 4b and the resist masks 17a and 17b, the lower portions of the resist masks 17a and 17b other than the gate electrodes 4a and 4b are the first portions. Offset region 2 with a low impurity concentration, which is implanted with impurities only
d, 2e.

At this time, since the offset regions 2d and 2e are formed on the left side of the corresponding gate electrodes 4a and 4b, even if the mask alignment at the time of forming the resist masks 17a and 17b is slightly deviated, the offset regions are formed. The length Ld of 2d and the length Le of the offset region 2e can be formed equal. In the present embodiment, the design values of the lengths Ld and Le of the offset regions 2d and 2e are set to 1 μm, and in a normal process, the offset region 2 is set within the range of 1 ± 0.5 μm even when the misalignment is taken into consideration.
By forming d and 2e to have the same length, the characteristics of the TFT1 and the TFT2 can be made equal.

Then, silicon oxide (SiO ₂ ) is deposited and openings 6a, 6b and 6c are formed to form an interlayer insulating layer 5, on which pixel electrodes 8a and 8b made of ITO and a display pixel electrode 9 are formed. Then, the data electrode 7 and the data line 15 made of aluminum (Al) are formed thereon (see FIGS. 4H and 4I). In this way, the active matrix device of this embodiment is formed.

Next, the operation of the active matrix device of this embodiment will be described with reference to the equivalent circuit diagram of FIG. FIG. 5A is an equivalent circuit diagram showing the operation when the potential of the data line 15 is higher than the potential of the display pixel electrode 9, and FIG. 5B is the equivalent circuit diagram showing that the potential of the display pixel electrode 9 is data. FIG. 6 is an equivalent circuit diagram showing the operation when the potential is higher than the potential of line 15.

First, as shown in FIG. 5A, when the potential of the data line 15 is higher than the potential of the display pixel electrode 9 and positive charges are written in the pixel ((+) writing), the gate is turned on. , The data electrode 7 is the drain,
The pixel electrodes 8a and 8b serve as source electrodes. That is,
In the TFT 1, the high-concentration region 2a adjacent to the offset region 2d serves as a source, and the high-concentration region 2f without offset serves as a drain. On the contrary, in the TFT 2, the high-concentration region 2b without offset is a source and a high-concentration region 2e adjacent to the offset region 2e. The concentration region 2f acts as a drain.

In the thin film transistor, if a high resistance offset region is provided on the source side for supplying carriers, the amount of charges flowing into the channel is reduced and the on-current is reduced. If an offset region is provided on the drain side, the on-current is reduced. Although it does not affect much, it has an effect of reducing off current. In this embodiment, the offset regions 2d and 2e are formed within a range of 1 ± 0.5 μm in consideration of misalignment. Therefore, in the case of (+) writing, the TFT
1, the offset region 2 of 0.5 μm or more on the source side
Since the d is formed, the resistance of the TFT1 is extremely higher than that of the TFT2 having no offset on the source side, and no current flows in either the ON state or the OFF state.

Therefore, when a positive voltage is applied to the gate electrodes 4a and 4b at the same time to turn on the gate, the TFT is turned on.
No current flows through 1 and an on-current flows through TFT 2, and writing to the pixel is performed. Since the TFT 2 has the offset region 2e of 0.5 to 1.5 μm formed on the drain side, the off current is reduced to the conventional dual gate TF.
T (see FIG. 7) can be reduced to about 1/10, and the area of the storage capacitor portion 11 can be reduced to the dual gate T.
Even if it is reduced to about 1/10 of the case of using FT, the pixel potential can be sufficiently held, and further, the storage capacitor section 11
The aperture ratio of the display can be improved as the area of the display is reduced. Further, since the TFT 2 has no offset region on the source side and the length of the offset region 2e on the drain side is 0.5 to 1.5 μm,
Has almost no effect on the on-state current, and the writing characteristic to the pixel is not impaired.

On the other hand, as shown in FIG. 5B, when the potential of the display pixel electrode 9 is higher than the potential of the data line 15 and negative charges are written in the pixel ((-) writing), it is turned on,
Regardless of whether it is off, the data electrode 7 serves as a source electrode and the pixel electrodes 8a and 8b serve as drain electrodes. That is, TF
At T1, the high concentration region 2 adjacent to the offset region 2d
In the TFT 2, the high-concentration region 2b without offset acts as a drain and the high-concentration region 2f adjacent to the offset region 2e acts as a source.

In this case, in the TFT2, 0.5 on the source side.
Since the offset region 2e of μm or more is provided,
TFT2 is TFT1 with no offset area on the source side.
The resistance is much higher than that of, and no current flows in either the ON state or the OFF state.

When a positive voltage is applied to the gate electrodes 4a and 4b and the gate is turned on, no current flows through the TFT2, and an on-current flows through the TFT1 to write data in a pixel. In the case of (-) writing as well, as in the case of (+) writing, since the offset region 2e of 0.5 to 1.5 μm is formed on the drain side in the actually operating TFT 1, the off current is significantly reduced. Therefore, the potential holding property of the pixel can be improved, the area of the storage capacitor portion 11 can be reduced, and the aperture ratio can be improved.

Therefore, in the active matrix element of the present embodiment, of the two thin film transistors connected in parallel, only the one having no offset on the source side and the one on the drain side operates, and writing to the pixel is performed. The switching is performed. That is, the TFT2 operates in the case of (+) writing, and the TFT1 operates in the case of (-) writing. In addition, TFT1
And the TFT2 are formed so that the offset regions 2d and 2e have the same length and the channel regions 2c and 2c 'have the same length so that the TFT1 and the TFT2 have the same characteristic (+) writing and the TFT1. The writing characteristics of (-) writing in which are operated become equal, and there is an effect that the display image quality of the liquid crystal display can be improved.

The active matrix device of this embodiment has two thin film transistors TFT1 and TFT2 having polycrystalline silicon (poly-Si) as a semiconductor active layer.
Since the offset region 2d of the TFT 1 and the offset region 2e of the TFT 2 are both formed in one direction of the corresponding gate electrodes 4a, 4b, for example, on the left side, the second impurity that determines the length of the offset regions 2d, 2e. Even if the mask alignment for implantation is slightly deviated, the offset region 2d,
There is an effect that the lengths of 2e can be formed to be equal and the characteristics of the TFT1 and the TFT2 can be equalized.

Further, the TFT 1 and the TFT 2 are connected to the data electrode 7
And the pixel electrode 9 for display are connected in parallel, the TFT 1 and the TF are connected depending on the polarity of the charges written in the liquid crystal capacitance.
Of T2, only one of the TFTs that has no offset on the source side operates, so that the off current is reduced and the potential retention of the pixel is improved without degrading the writing characteristics due to the decrease in on current. The area of the storage capacitor portion 11 can be reduced, and therefore the aperture ratio of the pixel can be improved, and since the characteristics of the TFT1 and the TFT2 are equal, the writing characteristics of (+) writing and (−) writing are equal. Thus, there is an effect that the display quality of the liquid crystal display can be improved.

In this embodiment, the offset area 2
Although d and 2e are provided on the left side of the gate electrodes 4a and 4b, they may be provided on the right side of the gate electrodes 4a and 4b. In this case, only the TFT1 operates during the (+) writing, and only the TFT2 operates during the (-) writing, and the effect is similar to that when the offset region is provided on the left side of the gate electrode. .

[0051]

According to the present invention, the offset regions adjacent to the first and second channel regions below the first and second gate electrodes are arranged in the same direction with respect to the first and second gate electrodes. An active matrix element in which the end high concentration region of the end of the semiconductor active layer is connected to a common electrode and the central high concentration region between the first and second channel regions is connected to another electrode. Therefore, even if misalignment occurs, the lengths of the two offset regions become equal and the two transistors formed by the two gate electrodes can have the same characteristics during their operation. Since the off-state current can be reduced and the potential holding characteristics can be improved by the formed offset region, the area of the liquid crystal storage capacitor portion of each pixel connected to the common electrode can be reduced and the image can be reduced. In addition, since both transistors operate with the same characteristics when writing positive and negative charges to pixels, the writing characteristics of positive and negative charges become the same, and the image quality can be improved. There is an effect that can be done.

According to the second aspect of the present invention, the first and second gate electrodes are formed so as to cross the sides of the semiconductor active layer, low-concentration impurity implantation is performed using these gate electrodes as masks, and two more are performed. A high-concentration impurity implantation is performed by forming a resist mask so as to cover the adjacent part of the gate electrode in one direction, and as a result, the high-concentration regions at the ends of the sides of the semiconductor active layer are used as a common electrode. Since the active matrix element manufacturing method is such that the electrode layers are formed so as to connect and connect the central high-concentration region formed in the central portion of the side of the semiconductor active layer to the common electrode, even if misalignment occurs The lengths of the two offset regions of the low-concentration region formed under the resist mask are equal, and the two transistors formed by the two gate electrodes have the same characteristics during operation. Since the offset region formed in each transistor can reduce off current and improve potential holding characteristics, the area of the liquid crystal storage capacitor portion of each pixel connected to the common electrode can be reduced. There is an effect that it can be reduced, and the aperture ratio of the pixel can be improved. Furthermore, since both transistors operate with the same characteristics when writing positive and negative charges to the pixel, the positive and negative charge writing characteristics become the same, and the image quality is improved. There is an effect that can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of one pixel of a liquid crystal display using an active matrix device according to an embodiment of the present invention.

FIG. 2 is an explanatory cross-sectional view of a portion AA ′ in FIG.

3A to 3E are process explanatory views showing a method of manufacturing the active matrix device of the present embodiment.

4 (f) to (i) are process explanatory views showing a method for manufacturing the active matrix device of the present embodiment.

5A and 5B are equivalent circuit diagrams of the active matrix device of the present embodiment.

FIG. 6 is an explanatory sectional view showing a basic structure of a poly-Si TFT.

FIG. 7 is a plan view of one pixel of a liquid crystal display using a conventional dual gate TFT as an active matrix element.

8 is a cross-sectional explanatory view of a portion BB 'in FIG.

FIG. 9 is a cross-sectional explanatory diagram of a conventional gate offset TFT.

[Explanation of symbols]

1 ... Substrate, 2 ... Semiconductor active layer, 2 '... Storage capacitor po
ly-Si layer, 3 ... Gate insulating layer, 4 ... Gate electrode,
5 ... Interlayer insulating layer, 6 ... Opening part, 7 ... Data electrode,
8 ... Pixel electrode, 9 ... Display pixel electrode, 10 ... Storage capacitor electrode, 11 ... Storage capacitor part, 14 ... Gate line,
15 ... Data line, 16 ... Upper part, 17 ... Resist mask, 18 ... Source electrode, 19 ... Drain electrode

Claims (2)

[Claims] 1. An active matrix device having a semiconductor active layer formed on a substrate, and first and second gate electrodes formed across an insulating layer so as to cross the semiconductor active layer. Edge high-concentration regions having a high impurity concentration are formed at both ends of the active layer, the end high-concentration regions are connected to a common electrode, and the semiconductor active layer portion below the first gate electrode is used to remove impurities. Forming a first channel region that does not include an impurity, and forming a second channel region in which the semiconductor active layer portion below the second gate electrode does not include an impurity, and forming the first channel region and the second channel region. A central high-concentration region having a high impurity concentration is formed between the channel region and the central high-concentration region is connected to another electrode,
A first offset region having a low impurity concentration is formed between the first channel region and the end high concentration region, and an impurity concentration between the second channel region and the central high concentration region is reduced. An active matrix device, characterized in that a low second offset region is formed. 2. A step of forming a semiconductor active layer on a substrate, a step of forming first and second gate electrodes across an edge of the semiconductor active layer via an insulating layer, and the first step.
And a step of implanting a low-concentration impurity using the second gate electrode as a mask, and forming a resist mask so as to cover one side portion in the same direction where the first and second gate electrodes are adjacent to each other, and a high-concentration impurity is added. Implanting step, forming an electrode layer so as to connect the end high concentration region formed at the end of the side of the semiconductor active layer by the high concentration impurity implantation to a common electrode, and the high concentration impurity implantation The step of forming an electrode layer so as to connect the central high-concentration region formed in the portion of the side of the semiconductor active layer between the first and second gate electrodes to another electrode. And a method for manufacturing an active matrix device.