JPH06303152A - Product code constructing method and apparatus, error correcting apparatus, and digital data recording / reproducing method - Google Patents

Abstract

(57) [Abstract] [Purpose] When weighting N types of parity numbers of outer codes with respect to digital data of arrays of inner code formats having different degrees of importance, parity numbers Pn (where n = 1, 2, 3,
..) when the number of data is Dn, Σ (P
n−G) × Dn = 0 (where G is an integer) By constructing the product code so as to satisfy the relational expression, it is possible to make the code length of one block uniform during recording or transmission, and according to the degree of importance. Since the weighting can be performed, the efficiency of error correction can be significantly improved, and the reproducibility of data can be maximized. [Structure] When weighting N types of parity check numbers of outer codes for digital data of an inner code array having different degrees of importance, the number of parity Pn (where n = 1,
The product code is configured so as to satisfy the relational expression of Σ (Pn−G) × Dn = 0 (where G is an integer), where the number of data of 2, 3, ...

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a digital VT.
The present invention relates to a method and apparatus for constructing a product code, an error correction apparatus, and a recording / reproducing method for digital data, which are suitable for application to equipment that handles digital data such as R.

[0002]

14 and 15 show, for example, a digital V
FIG. 14 and FIG. 15 show the TR recording system and the reproducing system, respectively.
The digital VTR will be described with reference to FIG.

In FIG. 14, a digital video signal input through an input terminal 1 is stored in a buffer memory 2 and then supplied to a DCT (discrete cosine transform) circuit 3 which produces a 4 × 4 signal. For each block, the DC component is converted into high-order AC component coefficient data, and is converted into two-dimensional spatial frequency data (coefficient data).

The coefficient data from the DCT circuit 3 is supplied to a quantizing circuit 4, and in the quantizing circuit 4, information is obtained by sequentially coarsening the quantization level from low frequency coefficient data to high frequency coefficient data. The amount is reduced. The quantized coefficient data obtained by being quantized by the quantization circuit 4 is supplied to the outer coding circuit 5.

The quantized coefficient data supplied to the outer code circuit 5 is parity O of the outer code in the outer code circuit 5.
P is added and stored in the field memory 6 by the write address from the address counter 7. The quantized coefficient data stored in the field memory 6 is read by the address counter 7 by the read address supplied from the ROM 8 and is supplied to the encoding circuit 9. In the encoding circuit 9, the parity IP of the inner code is added and the product is added. After being converted into a code, ID data and sync data are added for each inner code, and a recording head is passed through an amplifier circuit 10 and a rotary transformer 11 after being converted from an 8-bit parallel signal to a 1-bit serial signal with a clock frequency of 8 times. 13 and is recorded on the magnetic tape 14 like an inclined track.

Here, the format of the product code will be described with reference to FIG. As shown in FIG. 16, the product code format includes an inner code and an outer code. The inner code is composed of the digital data DA and the parity IP of the inner code as shown in FIG. 16A, and the outer code is added to the vertical data of the digital data DA shown in FIG. 16A and this as shown in FIG. 16C. It is composed of the parity OP of the outer code. 16B, the product code is composed of the inner code shown in FIG. 16A and the outer code shown in FIG. 16C.

Next, the reproducing system of the digital VTR will be described with reference to FIG. The recording signal recorded on the magnetic tape 14 is reproduced by the reproducing head 15, then supplied to the reproducing equalization circuit 17 via the rotary transformer 16, where the waveform is equalized and then supplied to the PLL circuit 18.

The PLL circuit 18 reproduces the clock signal based on the reproduced data. Then, in the sync detection circuit 19, the reproduction data of 1-bit serial data is set to 1 when recorded.
It is converted to 8-bit parallel data having a clock frequency of / 8 times. This converted data is used as the inner code error correction circuit 20.
Is supplied to.

The reproduction data supplied to the inner code error correction circuit 20 is subjected to error correction processing by the parity IP of the inner code to correct a random error, and then the field memory 22 together with the error flag generated here.
And the ID decoding circuit 21.

The ID decoding circuit 21 decodes the ID from the output data from the inner code error correction circuit 20, and the decoded ID
A write address is generated based on. Therefore, the output data from the inner code error correction circuit 20 is the ID decoding circuit 21.
It is stored by the write address from.

The data written in the field memory 22 is read by the read address generated by the address counter 24 on the basis of the synchronizing signal supplied through the input terminal 23 and supplied to the outer code error correction circuit 25. After the burst error is corrected by the outer code parity OP in the outer code error correction circuit 25, the ID
It is supplied to a CT (inverse discrete cosine transform) circuit 26.

The output of the outer code error correction circuit 25 supplied to the IDCT circuit 26 is inversely quantized and then inverse discrete cosine transformed to be original digital data. Then, after this, it is supplied to the error correction circuit 27 together with the error flag. Then, after being subjected to processing such as interpolation based on the error flag in the error correction circuit 27, it is output from the output terminal 28 as a reproduced digital video signal.

[0013]

By the way, when the digital data converted from the direct current to the high order alternating current component by the DCT circuit 3 are arranged in the order of the internal code in the order from the direct current component to the high order alternating current component, the arrangement shown in FIG. As is apparent, since the number of parity of the outer code parity OP for each data is the same, the error correction capability by the outer code parity OP at the time of error correction is the same for all data.

When an error occurs in the data, the closer the errored data is to the direct current or the direct current component, the greater the visual effect. Also, when a variable length code such as Huffman or run length is used, Since the data indicating the code length in each code is included, if an error occurs at the beginning of the block, all the data after the block also becomes an error.

That is, although the data has different levels of importance, the error correction capability for them is the same, and this is not taken into consideration in the conventional error correction, and therefore the error correction as a whole is made. There was an inconvenience that the efficiency of was poor.

When forming a magnetic track on the magnetic tape 14 by the recording head 13, the magnetic head 13 always intrudes into the magnetic tape 14 first, and then scans.
Further, the magnetic tape 14 is separated. Note that this separated portion will be referred to as an outlet.

That is, when a magnetic track is formed on the magnetic tape 14, the so-called contact between the magnetic head 13 and the magnetic tape 14 is not stable at the time of recording near the plunge portion and the exit of the magnetic track, so that a reproduction error may occur during reproduction. This is a part that has a high probability of occurrence, and the probability of causing a reproduction error at the time of reproduction gradually decreases as approaching the center of the magnetic track from these parts.

That is, in the conventional digital VTR, when data is recorded, for example, the data read from the field memory 6 (parity OP of data and outer code) is parity IP of inner code in the coding circuit 9. ,
Since ID data, sync data, etc. are added and converted into serial data and recorded so that recording tracks are sequentially formed from the beginning of the data string, the most important data is the magnetic head 13 described above. It is recorded near the entry or exit of the station, and is not recorded considering the importance of the data. Therefore, if
When data such as the above-mentioned DC component, which has a great visual effect at the time of error, is recorded in the rush portion or the outlet portion where a reproduction error is likely to occur, there is a disadvantage that the image quality is significantly deteriorated.

The present invention has been made in consideration of the above points, and it is possible to perform error correction in consideration of the importance of data and to prevent the deterioration of the image quality during reproduction. An attempt is made to propose a configuration method and apparatus, an error correction apparatus, and a digital data recording method.

[0020]

According to the method of constructing a product code of the present invention, the parity number Pn (however, if the number of parity of the outer code with respect to the digital data of the array of the inner code format having different importance is weighted to N types) n = 1, 2, 3, ...
) (Pn-
G) × Dn = 0 (where G is an integer), and the product code is configured to satisfy the relational expression.

Further, in the method of constructing the product code of the present invention, in the above description, the number of parity of the outer code for the digital data is N.
When the data is read from the storage area after weighting the types, the read inner code blocks have the same code length.

Further, the product code constituent device of the present invention adds outer code parity adding means 32, 33 for adding the outer code parity weighted based on the importance to the digital data of the inner code format having different importance. 34, 35 and inner code for adding inner code parity to digital data of different inner code formats with different importance, to which outer code parity weighted by outer code parity adding means 32, 33, 34, 35 is added. Parity adding means 36, 37, 38
And have.

Further, the error correction device of the present invention uses the parity of the inner code of the product code format digital data to which the parity of the outer code weighted based on the importance is added, and further the parity of the inner code is added. Error correction is performed using inner code error correction means 57, 58, 61 for correction and outer code parity weighted based on the importance of the digital data error-corrected by the inner code error correction means 57, 58, 61. Outer code error correction means 5 for performing
9, 62, 63, and 64.

Further, the error correction device of the present invention adds outer code parity adding means 32, 33, 34 for adding the outer code parity weighted based on the importance to the digital data in the inner code format having different importance. 35 and inner code parity addition for adding inner code parity to digital data in inner code formats having different degrees of importance, to which outer code parity weighted by outer code parity adding means 32, 33, 34, 35 is added. Means 36, 37, 38
And the parity of the outer code weighted based on the importance, and further the parity of the inner code is added, the inner code error correction means 57 for performing error correction using the parity of the inner code of the product code format digital data. , 58, 61,
Outer code error correction means 59, 62, 63, 64 for performing error correction using the parity of the outer code weighted based on the importance of the digital data error-corrected by the inner code error correction means 57, 58, 61. Is to have.

Further, the product code constituent device or the error correction device according to the present invention is as described above in the outer code parity adding means 3.
The address control means 37 is provided for controlling the address when storing the digital data after the parity of the outer code weighted to the digital data of the inner code format is added by 2, 33.

Further, in the above-described product code constituent device or error correction device of the present invention, the address control means 37 is provided with the horizontal write address signal generation means 46 for generating the horizontal write address signal and the vertical write address signal. A vertical write address signal generating means 45 for generating a horizontal read address signal, a horizontal read address signal generating means 51 for generating a horizontal read address signal,
A vertical read address signal generation means 53 for generating a vertical read address signal, and a horizontal write address signal and a vertical write address signal generation means 4 from a horizontal write address signal generation means 46.
On the basis of the vertical write address signal from 5, the address code conversion means 47 performs address conversion so that at least the product code array of the digital data has a uniform horizontal and vertical code length.

Further, the error correction apparatus of the present invention performs address control when reading out digital data in the product code format in which the parity of the outer code weighted based on the importance is added and the parity of the inner code is further added in the above description. The address control means 61 is provided.

Further, in the error correction device of the present invention, in the above description, the address control means 61 includes the horizontal write address signal generation means 51 for generating the horizontal write address signal and the vertical write operation for generating the vertical write address signal. Address signal generation means 53, horizontal read address signal generation means 46 for generating a horizontal read address signal, vertical direction read address signal generation means 45 for generating a vertical read address signal, and horizontal read address signal. Based on the horizontal read address signal from the generation means 46 and the vertical read address signal from the vertical read address signal generation means 45, based on the digital data in which at least the product codes are arranged in uniform vertical and horizontal code lengths. To be an array of Which is constituted by the address conversion unit 47 for performing address translation.

Further, according to the digital data recording / reproducing method of the present invention, when recording digital data having different importance, the most important digital data is recorded in the vicinity of the center of the recording track, and then the importance is increased. Accordingly, recording is sequentially performed from the center of the recording track to the outer side, and this is reproduced.

[0030]

According to the method of constructing the product code of the present invention described above, when the number of parity of the outer code with respect to the digital data of the array of the inner code format having different importance is weighted to N types, the number of parity Pn (where n = 1, 2, 3, ...)
Σ (Pn−G) ×, where Dn is the number of data
The product code is configured so as to satisfy the relational expression of Dn = 0 (where G is an integer).

Further, according to the method of constructing the product code of the present invention described above, when the parity number of the outer code for the digital data is weighted to N types and then read from the storage area, the read inner code block data is Make sure that each has the same code length.

According to the product code constituent device of the present invention described above, the outer code parity adding means 32 adds the outer code parity weighted based on the importance to the digital data of the inner code format having different importance. 33, 34 and 35, and the outer code parity adding means 32, 33 and 3
The inner code parity adding means 36, 37, and 38 add the inner code parity to the digital data of the inner code formats having different degrees of importance, to which the outer code parity weighted by 4, 35 is added.

According to the error correction device of the present invention described above, the parity of the outer code weighted based on the importance is added, and the parity of the inner code is further added. Error correction by the inner code error correction means 57, 58, 61 using
The outer code error correction means 5 uses the parity of the outer code weighted based on the importance of the digital data error-corrected by the inner code error correction means 57, 58, 61.
Error correction is performed at 9, 62, 63, and 64.

Further, according to the error correction apparatus of the present invention described above, the outer code parity weighting means 32, 33, for the outer code parity weighted based on the importance of the inner code format digital data having different degrees of importance. 34, 35, and the outer code parity adding means 32, 33, 34,
The inner code parity adding means 36, 37 and 38 add the inner code parity to the digital data of the inner code format having different degrees of importance to which the outer code parity weighted by 35 is added and weighted based on the importance. The inner code error correction means 57, 58, 61 performs error correction using the inner code parity of the product code format digital data to which the outer code parity is added and the inner code parity is further added. Code error correction means 57, 58, 6
The outer code error correction means 59, 62, 63, 64 performs error correction using the outer code parity weighted based on the importance of the digital data error-corrected in 1.

Further, according to the product code constituent device or the error correction device of the present invention described above, the digital code after the weighted outer code parity is added to the inner code format digital data by the outer code parity adding means 32 and 33. The address control means 37 performs address control when storing data.

Further, according to the product code constituent device or the error correction device of the present invention described above, the horizontal write address signal from the horizontal write address signal generating means 46 and the vertical write from the vertical write address signal generating means 45 are written. Based on the address signal, the address conversion means 47 performs address conversion so that at least the product code array of the digital data has a uniform vertical and horizontal code length.

Further, according to the error correction apparatus of the present invention described above, an address for reading digital data in a product code format in which the parity of the outer code weighted based on the importance is added and the parity of the inner code is further added is read. The control is performed by the address control means 61.

Further, according to the error correction apparatus of the present invention described above, based on the horizontal read address signal from the horizontal read address signal generating means 46 and the vertical read address signal from the vertical read address signal generating means 45, Address conversion is performed by the address conversion means 47 so that digital data in which at least the product code array has a uniform code length in the vertical and horizontal directions becomes the original array.

According to the digital data recording / reproducing method of the present invention, when recording digital data of different importance, the most important digital data is recorded near the center of the recording track. In accordance with this, recording is sequentially performed from the center of the recording track to the outside, and this is reproduced.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the product code construction method and apparatus, error correction apparatus and digital data recording method of the present invention will be described in detail below with reference to FIG.

In FIG. 1, reference numeral 30 denotes coefficient data which has been discrete cosine transformed by a DCT (discrete cosine transform) circuit of a reproducing system of a digital VTR as shown in FIG. 14 and further quantized (further run length or Huffman). The same applies to variable length code data such as), and 31 is an input terminal to which an ECC (error correction code) block start signal from a digital VTR main circuit (not shown) is supplied. is there.

Here, in the coefficient data array supplied via the input terminal 30, the most important data (DC component coefficient data and low-order AC component coefficient data) is arranged at the beginning of the array, and later It is assumed that low importance data (higher-order AC component coefficient data) is placed in the part.

Reference numeral 32 denotes a memory, which stores the coefficient data of the high-order AC component from the DC component supplied through the input terminal 30 by the address signal from the memory control circuit 33.
The memory control circuit 33 has, for example, a write address counter and a read address counter inside, and starts a counting operation after being reset by an ECC block start signal supplied via the input terminal 31,
A write address signal, a read address signal, and a write / read enable signal are generated. The coefficient data for each block stored in the memory 32 is read out in the outer code format, that is, in the vertical direction, and supplied to the outer code generation circuit 34.

The outer code generation circuit 34 reads the coefficient data for each block supplied from the memory 32 based on the read data timing signal supplied from the memory control circuit 33. On the other hand, the memory control circuit 33 supplies the read address signal to the code length detection circuit 35. The code length detection circuit 35 controls the number of parities generated by the outer code generation circuit 34 based on the address indicated by the read address signal from the memory control circuit 33.

Therefore, the outer code generation circuit 34 receives the coefficient data supplied from the memory 34 and detects the code length detection circuit 35.
The outer code parity based on the outer code parity number control signal supplied from is added as shown in FIG. The outer code format data string supplied to the memory 36 is stored in the memory 36 in response to a write address signal from the memory control circuit 37.

The memory control circuit 37 has, for example, a write address counter and a read address counter inside, and after being reset by the outer code timing signal supplied from the outer code generation circuit 34, the counting operation is started to write the write address signal. , Read address signals and write / read enable signals.

The outer code stored in the memory 36 is read out in the form of the inner code, that is, in the horizontal direction by the read address signal from the memory control circuit 37, and the inner code generating circuit 3
8 are supplied.

The internal code generation circuit 38 is based on the read timing signal from the memory control circuit 37 and is stored in the memory 36.
The parity of the inner code is added to the data string in the inner code format from and is supplied to the not-shown VTR coding circuit or the like through the output terminal 39.

Here, in explaining FIG. 2, first,
How to configure the product code will be described with reference to FIGS.

As shown in FIG. 3A, the input terminal 30 shown in FIG. 1 has discrete data from a DC component to a high-order AC component, that is, as shown in FIG. 3B, an array of one inner code. The supplied data sequence is an array of the coefficient data d1 of the DC component and the coefficient data of higher frequency sequentially (though quantized or after variable length coding) d18.
As described above, among these components, the direct current and the low-order alternating current components have a high visual influence, and the high-order alternating current components have a low visual influence. Therefore, as shown in FIG. 3B, the direct current component coefficient data d1 is Most important, d2, d3, d4, d
5, d6, d7, d8, d9, ... d15, d1
Up to 6, d17 and d18, the low-order AC component becomes a high-order AC component. That is, the importance becomes lower in order.

FIG. 3C shows the arrangement state of the inner code of the data as shown in FIGS. 3A and 3B. That is,
As shown in FIG. 3C, the data string in the inner code format is the data DA1, DA2, DA as shown in FIGS. 3A and 3B.
3, ... DAn−1, DAn, and an internal code parity (inner parity) IP is added.

The outer code format array is the inner code format data DA1, DA2, DA3, ... Shown in FIG. 3C.
As shown in FIG. 3D, a plurality of Dan-1 and DAn (for example, variable length code block units) are collected, and a parity (outer parity) OP of the outer code is added to the vertical data to form a data array.

In FIG. 3C, each data of one inner code block is DA1, DA2, ... DAn-1, D.
Let An be the data when a plurality of inner code blocks are grouped in FIG. 3D, DA1, DA2, ...
1, DAn, but without doing this, for example, the data of the inner code block is da1, da2, ... Dan.
-1, dan, the formed data blocks when a plurality of inner code blocks composed of these data are arranged in the vertical direction are DA1, DA2, ... DAn as shown in FIG. 3D.
-, DAn, but the configuration of the outer code block in which the parity of the outer code is read from the memory 32 shown in FIG. If it is one inner code block, it may be confusing if multiple codes are applied to the same data corresponding to the array state, which may confuse the description. In the case of a code block, in the case of one outer code block and in the case of a plurality of outer code blocks, the data DA1, DA
2, ..., DAn-1, DAn are described.

Actually, if the data is after the variable length code,
If the data is the minimum unit, that is, the data that has been DCT-transformed and quantized, the quantized coefficient data are sequentially arranged in the block, which are vertically overlapped as shown in FIG. The outer code parity is added, and then the inner code parity is added to the horizontal configuration data.

As shown in FIG. 3D, each data DA1, D1
The outer code parity is added according to the importance of A2, ..., DAn-1, DAn. In other words, important data is the one that attempts to perform error correction with a high error correction capability during error correction. As shown in FIG. 3D, the number of outer code parities indicated by P1 in the vertical direction is added to the most important data DA1, and thereafter, as the importance decreases, the number indicated by P2 in the vertical direction increases. Outer code parity, ... The number of outer code parities indicated by Pn in the vertical direction is added.

Here, the data DA1, D shown in FIG. 3D
The number of data (or code length) in the horizontal direction (inner code direction) of A2, DA3, ...
.., Wn-1, Wn, the total number of data (excluding parity IP) WW in the inner code direction (horizontal direction in the figure) is as follows.

WW = W1 + W2 + W3 + ... Wn-1 + Wn (1)

Therefore, the parity OP of the outer code shown in FIG.
Assuming that Ps is the number of parities of, that is, the number of parity of the outer code that is the same as when the conventional parity is added without considering the importance, Ps can be expressed by the following equation (2).

Ps = (W1 × P1 + W2 × P2 + W3 × P3 + ... ・ ・ ・ + Wn-1 × Pn-1 + Wn × Pn) / WW (2) (however, W1, ... Wn, P1 , ... Pn is a positive integer)

Incidentally, in FIG. 3D, the data DA1, DA
2, ... The total number of parity of the outer code for each block added to DAn-1, DAn is W1 x P1, W2 x P, respectively.
2, ... Wn−1 × Pn−1, Wn × Pn.

That is, the number of horizontal data (or code length) W1, W2, ...
..Data of Wn-1, Wn DA1, DA2, ... D
For An-1 and DAn, the parity numbers P1, P2, ... Pn-1, Pn of the parity OP of the outer code are determined for each block based on the importance.

That is, when weighting the number of outer code parities to N types, the number of parities Pn (n = 1, 2, 3 ...
..) when the number of data is Dn, Σ (Pn-G) × Dn = 0 (where G is an integer).

Next, referring to FIG. 4, an example is shown in which one inner code block is composed of data DA1, DA2 and DA3, and the parity IP of the inner code (a small number is used for convenience of explanation). Actually the data DA1, DA
2. A case will be described in which the parity OP of the outer code is added according to the importance of DA3. Also, in this case DA1
Each data of, for example, the low-frequency component data having the highest importance, each data of DA2 is the data of the middle-frequency component having the second highest importance, and each data of DA3 is the data of the high-frequency component having the low importance. To do.

FIG. 4A shows one inner code block. As shown in FIG. 4A, one inner code block is composed of data DA1, DA2 and DA3, and inner code parity IP.

When a plurality of inner code blocks are grouped and the outer code parities OP1, OP2 and OP3 are added in correspondence with the degree of importance (DA1>DA2> DA3),
As shown in FIG. 4B.

As already described in FIG. 3, the data D
Assuming that the data lengths (or code lengths) of A1, DA2, and DA3 are W1, W2, and W3, respectively, the total code length (excluding parity IP) WW in the inner code direction (horizontal direction in the figure) is calculated from equation (1). It becomes W1 + W2 + W3.

Therefore, the parity OP of the outer code shown in FIG.
If the parity number in the outer code direction, which is the same as when the conventional parity is added without considering the importance, is Ps, then the parity number Ps in this case is as follows from equation (2). Can be expressed as

(W1 × P1 + W2 × P2 + W3 × P3) / WW (3)

Incidentally, in FIG. 4B, the data DA1, DA2
, DA3, the total number of parity of the outer code for each block is W1 × P1, W2 × P2, ... Wn−1.
XPn-1 and WnxPn.

That is, the parity number Ps is (W1 × P1 +
W2 × P2 + W3 × P3) / WW, so that the number of data in the horizontal direction (or code length) W1, W2, and W3 data DA1, DA2, and DA3 is the parity number of the outer code parity OP. P1, P2, ... P
n-1 and Pn are determined for each block based on the degree of importance.

By the way, as shown in FIG. 1, the outer code generating circuit 34 adds the parity of the outer code to the data DA1, DA2, DA3 of the array in the inner code direction, and the memory 36.
In the case of storing in the memory, if the memory space of the memory 36 does not have the shape shown in FIG. 4B, not only all the data cannot be stored, but also the arrangement shown in FIG. 4B remains horizontal. When the data is read in the direction, the sync data and the ID data are added while the lengths of the inner code blocks are made different, and normal processing cannot be performed.

Therefore, the total parity number of the outer code added to the block of the data DA1 in excess of the normal amount is d.
Let p1 be dp2 × W2 be the total number of parities that are usually insufficient for the outer code parity assigned to the block of data DA2, and be the total number of parity that is normally insufficient for the outer code parity numbers assigned to the data DA3. d
When p3 × W2 is set, as shown in FIG. 4C, the data D
Parity number dp1 × W1 added to A1
Of the parity OP1 of the number dp2 × W2 of the parity OP1 are allocated to the data DA2 (memory 3
6 is stored in that area), and the parity OP1 of the number of parity dp3 × W3 is assigned to the data DA3 (stored in that area on the memory 36). By doing so, the block length of the synchronization block (in which the sync data, the ID and the sector data are added to the inner code block) at the time of recording or transmission can be fixed, and further, at the time of writing to the memory 36 as well. No processing or formatting problems occur.

Next, referring to FIG. 5, quantized coefficient data,
Alternatively, the flow until the variable length code data is input to the circuit shown in FIG. 1 and stored in the memory 36 will be described.

First, when the ECC block start signal (see FIG. 5A) supplied to the input terminal 31 shown in FIG. 1 becomes the high level "1", the memory control circuit 33 causes the input terminal 30 to operate.
Data DA1, DA shown in FIG. 5B supplied via
2, DA3 is written in the memory 32. As shown in FIG. 5B, inner code blocks are written in the memory 32 so as to be vertically stacked.

That is, from the address 0 in the X direction to immediately before the address Q1, the block data DA1 and the address Q1.
From the block immediately before the address Q2 to the block data DA2,
The area from the address Q2 to immediately before the address Q3 is the area of the block data DA3. Further, the addresses in the Y direction are up to the address R1.

Next, in response to the read address signal and the read enable signal from the memory control circuit 33, the block data DA1 and DA shown in FIG.
2, DA3 is read in the vertical direction. At the same time, the code length detection circuit 35 controls the outer code as shown in FIG. 5D in order to notify the outer code generation circuit 34 of the code length of the parity OP of the outer code by the read address signal from the memory control circuit 33. And supplies the outer code parity number control signal to the outer code generation circuit 34.

As shown in FIG. 5E, the outer code generation circuit 34 supplies the number of outer code parities supplied from the code length detection circuit 35 to the data DA1, DA2, and DA3 sequentially read from the memory 32 in the outer code direction. On the basis of the control signal, for the block data DA1 read in the vertical direction (strictly speaking, it becomes one vertical data string of the block data DA1 shown in FIG. 5C), the outer code of the parity number P1 is used. The parity OP1 is added, the outer code parity OP2 having the parity number P2 is added to the block data DA2 read in the vertical direction, and the parity number P3 is added to the block data DA3 read in the vertical direction. The outer code parity OP3 is added.

That is, when the horizontal address of the memory 32 is X and the vertical address of the memory 32 is Y, the control of the outer code generation circuit 34 by the code length detection circuit 35 is performed in accordance with the following conditions. ing.

When the horizontal address X is 0 ≦ X ≦ Q1, if X ≦ Q1, the number of parity of the outer code parity OP1 is P1. If Q1 <X ≦ Q2, the number of parity of the outer code parity OP2 is P2 Q2. If X ≦ Q3, the parity number of the outer code parity OP3 is P3.

According to this condition, the data DA of each block
FIG. 5F shows a state in which the parity OP of the outer code is added to each of 1, DA2, and DA3.

In the example shown in FIG. 5F, as described above, the same parity number as the conventional one (the total number of parity is the total number of data or the average divided by the code length) is Ps, and
The parity number P2 of the parity OP2 added to the data DA2 is the average parity number Ps, and the parity number P3 of the parity OP3 added to the data DA3 is the parity number Ps.
Parity OP1 smaller and added to data DA1
Shows the case where the parity number P1 is larger than the parity number Ps.

From the above equation (3), in this case, the parity numbers P2-P3 are equal to the parity numbers P3-P2,
Of the parity OP1 added to the data DA1, the parity OP1 of the parity number P1-P2 can be stored in the area of the memory 36 corresponding to the parity number P2-P3 of the parity OP3 added to the data DA3. Become.

Therefore, the memory control circuit 37 performs the parity O of the outer code added to the data DA1 under the following conditions.
Addresses of P1 that exceed the parity number Ps are converted into addresses of an extra area of the memory 36 of the data DA3 and stored in this area.

As a condition, when X is a write address signal in the horizontal direction and Y is a vertical address signal supplied to the memory 36, and X ≦ Q1 and Y> R3, X is X + Q2 + 1, Y. Becomes R2 + (Y-R3). Here, X ≦ Q1 is set because the parity OP3 of the outer code added to the data DA1 in FIG. 5F is targeted, and Y> R3 is set in FIG.
Outer code parity O added to data DA1 in F
This is because the number of P1s exceeding the average number of parity Ps is targeted.

Here, Q1 is the final address of the most important data block (block of data DA1 in this example), and Q2 is the final address of the second most important data block (block of data DA2 in this example). Address, Q3
Is the data block with the lowest importance (in this example, data D
The final address of the A3 block).

The address R1 is the start address of the outer code parity OP, the address R2 is the last address of the outer code parity OP3 added to the data DA3 shown in FIG. 5F, that is, the average parity number Ps is smaller than the parity number. Address corresponding to block (data D in this example)
Address of block A3), address R3
Is the above-mentioned average parity number Ps and the parity OP of the outer code
Is written in the memory 36 and the address R4 is a virtual address when the address R3 is exceeded.

Here, R1 is 10, R2 is 20, R3 is 30, R4 is 31 or more, Q1 is 10, Q2 is 20, and Q3.
An example will be described where 30 is set to 30.

In this case, if the parity OP1 of the outer code added to the data DA1 in the example shown in FIG. 5F is written in the memory 36, the horizontal write address X is "0" and the vertical write address Y is "31". , The horizontal write address X is X + Q2.
+1 to 0 + 20 + 1, that is, "21" (the address next to Q2 and the parity OP3 of the outer code of the data DA3)
Storage area) and the write address Y in the vertical direction is Y + R2-R3 to 31 + 20-30, that is, "21" (becomes the area next to R2).

That is, the average parity number Ps shown in FIG. 5F
The parity OP1 having the number of parities that exceed the above is the rest of the area for the outer code parity OP3 added to the data DA3 shown in FIG. 5F in the memory 36, that is, X is “21” and Y is “21” in the above example. Therefore, the area is the remaining area of the outer code parity OP3 added to the data DA3 shown in FIG. 5F.

Next, referring to FIG. 6, the data DA1, DA2, DA3 and the outer code parities OP1, OP2, O added to the data DA1, DA2, DA3, respectively, are stored in the memory 36 by the processing described above.
The operation from the state of storing P3 to the addition of the inner code parities IP1, IP2, and IP3 by the inner code generation circuit 38 and the output as a data string will be described.

FIG. 6A shows the memory 36 by the above processing.
3 shows a state in which the data DA1, DA2, DA3 and the outer code parities OP1, OP2, OP3 are stored. In this case, as an example, the code length W of the data DA1
1, the code length W2 of the data DA2 and the code length W3 of the data DA3 are equal to each other and have a length T, and the parity number P1 of the parity OP1 of the outer code added to the data DA1 and the outer code added to the data DA3. The case in which the total number of parity numbers P3 of the parity OP3 is equal to the result obtained by multiplying the parity number P2 of the outer code parity OP2 added to the data DA2 by 2. Further, as shown in the figure, it is assumed that the average parity number Ps is equal to the parity number P2 of the parity OP2 added to the data DA2.

As shown in FIG. 6A, the number of parities P in the parity OP1 of the outer code added to the data DA1 is P.
The parity OP1 exceeding s is the parity O of the outer code added to the data DA3, as indicated by the solid arrow in the figure.
It is stored in the area P3 (indicated by diagonal lines in the figure, and the parity code OP1 is shown in that portion).

After that, the memory control circuit 37 shown in FIG.
Is read out for each inner code block in the horizontal direction by the start signal (see FIG. 6B). Here, the vertical address Y indicated by the read address signal of the counter (described later with reference to FIG. 2) of the memory control circuit 37 is 0 ≦.
If Y ≦ R1, the data DA1, as shown in FIG. 6C,
DA2 and DA3 are sequentially read in the horizontal direction, that is, in units of inner code blocks, and when the address Y is R1 <Y ≦ R2, they are added to the respective data DA1, DA2, and DA3 as shown in FIG. 6D. Outer code parity OP1, O
When P2 and OP3 are read in the horizontal direction, that is, sequentially in units of inner code blocks, and the address Y is R2 <Y ≦ R3, as shown in FIG. 6E, they are added to the respective data DA1, DA2, and DA3. Outer code parity OP1, OP
2 and OP3 are sequentially read in the horizontal direction, that is, in units of inner code blocks.

Here, it should be noted that when the address Y is R2 <Y≤R3 as shown in FIG. 6E, the outer code parity OP3 of the original data DA3 is output as shown in the figure. In the shaded portion to be formed, part of the outer code parity OP1 added to the data DA1 is assigned to part of the storage area of the outer code parity added to the data DA3 of the memory 36 by the above-described processing. , As described above, the shaded portion (period) in which the parity OP3 of the outer code of the data DA3 should be output at the time of reading
The parity OP1 of the outer code assigned to the data DA1 is output.

That is, in this example, as the block of the original product code format, as shown in FIG. 6F, when the parity number of the outer code parity OP3 added to the data DA3 is smaller than the average parity number Ps, the average The remaining parity number is allocated to the parity number Ps, and the parity number exceeding the average parity number Ps is allocated among the parity numbers P1 of the outer code parity OP1 added to the data DA1. Therefore, as shown in FIG. 6F, the product code block in this example is the data DA1, DA
2 and DA3 and the parities OP1, OP2 and OP3 are configured as described above, and then the parity IP of the inner code is further added.

Now, as shown in FIGS. 6C, 6D and 6E, the memory 3 is controlled by the memory control circuit 37 in FIG.
The data string in the unit of the inner code read from 6 in the unit of the inner code is sequentially supplied to the inner code generating circuit 38 shown in FIG.

Then, the internal code parity IP is added by the internal code generation circuit 38, and is supplied to a recording system such as a digital VTR (not shown) or a codec or a transmission system via an output terminal 39.

That is, the data string of the inner code unit shown in FIG. 6C is supplied to the inner code generating circuit 38, and the parity IP of the inner code generated by the inner code generating circuit 38 is added to the inner code generating circuit 38 to generate the inner code as shown in FIG. 6G. The data string in the inner code unit shown in FIG. 6D is supplied to the inner code generating circuit 38, and the parity IP of the inner code generated by the inner code generating circuit 38 is added to the inner code as shown in FIG. 6H. The data sequence in the inner code unit shown in FIG. 6E is supplied to the inner code generating circuit 38, and the parity IP of the inner code generated by the inner code generating circuit 38 is added to the inner block as shown in FIG. 6I. It is made into a code block.

Next, the internal structure of the memory control circuit 37 shown in FIG. 1 will be described with reference to FIG.

In the figure, 40 is an input terminal to which the outer code timing signal from the outer code generating circuit 34 shown in FIG. 1 is supplied, and 41 is an inner code based on the outer code timing signal supplied through the input terminal 40. Start signal, read E
CC block start signal (EC stored in the memory 36
C block reading signal), write ECC block start signal (ECC from the outer code generation circuit 34)
A signal for writing a block in the memory 36), an outer code start signal, a write enable signal, a read enable signal, and a read timing signal indicating the beginning of the code block.

Reference numeral 45 is a counter for generating a write address in the vertical direction of the memory 36 shown in FIG. 1, which is reset by an output signal from an AND circuit 48 which will be described later, and then starts an outer code from the timing generation circuit 41. A clock signal from a clock generation circuit (not shown) is counted in synchronization with the signal, the count value Y is supplied to an address conversion circuit 47 described later, and the count value Y is a vertical address R3 (see FIGS. 5 and 6). (Corresponding to R3 in 1), the carry signal output from carry output terminal CO is set to high level "1".

This carry signal corresponds to the memory 3 shown in FIG.
6 is supplied to a terminal P of an address counter 46 for generating a horizontal write address. This counter 46 is reset by the write ECC block start signal from the timing generation circuit 41, and then the counter 4
Every time the carry signal from 5 becomes high level "1", the increment operation is performed, and the count value obtained as a result is supplied to the address conversion circuit 47.

Although the address conversion circuit 47 has already been described,
Regarding the count value X from the counter 46 and the count value Y from the counter 45, when X ≦ Q1 and Y> R3, the horizontal write address WX output from the output terminal 49 is obtained by the count value X + Q2 + 1. The write address WY in the vertical direction is counted value Y + R2
-Determine with R3. That is, as described with reference to FIGS. 5 and 6 by the addresses WX and WY, the average number of parity P in the parity OP1 of the outer code added to the data DA1 is P.
The amount exceeding s can be stored in the storage area for the parity OP3 of the outer code added to the data DA3.

Further, this address conversion circuit 47 has
<X ≦ Q2 and Y ≧ R3, and Q2 <X ≦
A reset signal for resetting the counter 45 is obtained when Q3 and Y ≧ R2, and this reset signal is supplied to the AND circuit 48.

The former condition is the data D in this example.
Since the area corresponding to A2 is the average parity number Ps, when the outer code parity OP2 is written in this area, the counter 45 is reset after counting up to the highest value of the address R3. is there.

The latter condition is that in this example, when the parity OP3 of the outer code is written in the area corresponding to the data DA3, the parity of the outer code already added to the data DA1 is added after the address R2. This is because, among OP1, the parity OP1 that has exceeded the average number of parity Ps has been written, and this is not erased.

The AND circuit 48 includes the timing generation circuit 4
1 is supplied with the write ECC block start signal.
The logical product of the CC block start signal and the reset signal (for example, low level “0”) from the address conversion circuit 47 is calculated. As a result, the counter 45 is reset when the reset signal is valid.

That is, the counter 45 first outputs the vertical write address WY sequentially up to the maximum value in the vertical direction, and when the vertical write address WY reaches the maximum value, the counter 46 outputs the horizontal write address WX. By sequentially performing the operation of incrementing by “1”, the data string in the form of the outer code block shown in FIG. 5E can be written in the memory 36.

Reference numeral 51 denotes an address counter for generating a horizontal read address signal, which is reset when the read ECC block start signal from the timing generation circuit 41 is supplied to the reset terminal RST and is synchronized with the inner code start signal. The clock signal from the clock signal generating circuit (not shown) is counted, and the count value X
As a read address RX in the horizontal direction
And a carry signal output from the carry output terminal CO when the count value X reaches the horizontal address Q3.

This carry signal is supplied to the address counter 53 for generating a read address signal in the vertical direction. The address counter 53 is reset by the read ECC block start signal from the timing generation circuit 41, and then performs an increment operation each time the carry signal from the counter 51 becomes a high level "1", and the count value Y in the vertical direction. The read address RY is output from the output terminal 54.

That is, the counter 51 first outputs the horizontal read addresses RX sequentially to the maximum value in the horizontal direction, and when the horizontal read address RX reaches the maximum value, the counter 46 sets the read address in the vertical direction to " By sequentially performing the operation of incrementing by 1 ″, the data of the storage array as shown in FIG. 6A can be read from the memory 36 as a data string in the form of the inner / outer code block as shown in FIGS. 6C, D and E. Is.

Next, the operation of the entire circuit shown in FIG. 1 will be described with reference to FIG. 7 focusing on the operation of the memory control circuit 37 shown in FIG.

The input terminal 30 shown in FIG. 1 is supplied to the inner code format (horizontal direction) block data DA1 and DA shown in FIG. 7A.
2 and DA3 are sequentially supplied, and when the ECC block start signal shown in FIG. 7B is supplied to the input terminal 31, the memory control circuit 33 obtains the inner code signal shown in FIG. 7C, and based on this, the various signals described above. To get The block data DA1, DA2, DA3 shown in FIG.
Data is sequentially written to the memory 32 by the write address signal and the write enable signal from 3.

Then, the block data DA1 and D once written in the memory 32 by the read address signal and the read enable signal from the memory control circuit 33.
As shown in FIG. 7D, A2 and DA3 are read in a data array in the outer code format. Then, the read data timing signal (see FIG. 7E) from the memory control circuit 33 is taken into the outer code generation circuit 34.

The outer code generation circuit 34 is based on the outer code number control signal from the code length detection circuit 35 shown in FIG.
As shown in, block data D of an array of each outer code format
Outer code parity OP1 for parity number P1 for A1, DA2, DA3, outer code parity OP2 for parity number P2, and outer code parity OP3 for parity number P3, respectively.
Is added.

Outer code parity OP1, OP2, OP3
Of the outer code block DA1 and DA to which is sequentially added
2, DA3 are sequentially output from the outer code generation circuit 34. The outer code timing signal shown in FIG. 7H is supplied to the memory control circuit 37. The counter 45 starts counting by the outer code start signal generated by the timing generation circuit 41 shown in FIG.
The count value Y is sequentially supplied to the address conversion circuit 47.

The address conversion circuit 47 monitors the count values from the counters 45 and 46, and checks the above-mentioned condition (X≤Q
1 and count values X and Y until Y> R3)
Are supplied to the memory 36 as write addresses WX and WY.

When the conditions are met, the parity numbers P1 and P2 of the parity OP1, OP2 or OP3.
Or data DA in which P3 does not reach the average parity number Ps
1, DA2 or DA3 outer code parity OP1, O
The parity OP in the storage area of P2 or OP3
Data DA1, DA in which the parity number P1, P2 or P3 of 1, OP2 or OP3 exceeds the average parity number Ps
2 or parity of outer code OP1, O added to DA3
In order to store P2 or OP3 in the memory 36, the horizontal write address WX is set to the count value X + Q2 + 1.
The write address WY in the vertical direction is obtained by the count value Y + R2-R3, and these addresses WX and WY are supplied to the memory 36.

Next, when the read ECC block start signal is supplied to the counter 51, the counter 51 is reset, and the counting operation is started in synchronization with the inner code start signal, and the count value is read in the horizontal direction. The address RX is supplied to the memory 36. On the other hand, the read address RY in the vertical direction is the count value Y that is incremented by the carry signal after the address RX reaches the maximum value. Therefore, from the memory 36, as shown in FIGS. 7I and 7J, the data DA1, DA
2, DA3 and outer code parity OP1, OP2, O
P3 is read.

The block data DA1, DA2, DA3 and the parities OP1, OP2, OP3 read as shown in FIGS. 7I and J are read data timing signals (see FIG. 7) from the timing generation circuit 41 shown in FIG.
(See K), the data is read into the inner code generation circuit 38, and as shown in FIGS. 7L and 7M, the inner code parity IP is added to each of the inner code blocks. That is, as shown in FIGS. 7L and 7M, the data DA1 and D of the array in the inner code format
Parity IP of the inner code is added to A2 and DA3,
..Parity OP1 and OP of outer code of array in inner code format
2 and OP3 are added with the inner code parity IP,
..Parity OP1 and OP of outer code of array in inner code format
2. Parity IP of inner code in OP1 (shown by diagonal lines in the figure)
Is added. Here, the hatched portion is the portion where the outer code parity OP3 should originally exist on the time axis, as described sequentially from FIG. 5, but the outer code parity OP1 added to the data DA1 Average parity number P of
Since the parity OP1 exceeding s is stored in the memory 36, the parity OP3 of the outer code exists at the position where it should exist on the time axis even during reading.

For reference, an array of data obtained by the above-mentioned processing is shown for each processing.

D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D45 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59

This is the data D00-D09, D10-D1 of the data string input in the circuit of FIG. 1 in the inner code format.
9, D20 to D29, D30 to D39, D40 to D4
9, D50 to D59, and in this case, the data of the data string in the outer code format is D00, D10, D20, D3.
It becomes a data string when read vertically such as 0, D40, and D50. In addition, among the numbers of each data, the number on the left side indicates the order (or the number of steps, etc.) in the outer code, and the number on the right side indicates, for example, the degree of importance (or the height of frequency).

When the outer code parity OP is generated in the outer code generation circuit 34 based on the degree of importance of the data string in the outer code direction of the data block, for example, the following occurs.

D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D45 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 000 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 030 031 032 033 034 035 040 041 042 042 051 052 053

The lower data string is the outer code parity O.
It is P, and it can be seen that many outer code parities OP are added to the left side, that is, the data of high importance. Next, as described above, since the length of the synchronization block stored in the memory 36 or formed by adding sync data and ID data is changed as it is, the parity OP on the right side is set in the remaining area on the left side. assign.
Then, the following new array can be created.

D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D45 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 000 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 040 041 042 043 030 031 032 033 034 034 043 0030. 051 052 053

As can be seen, the left parity 0
40, 041, 042, 043, 050, 051, 05
2,053 are assigned (stored) to the empty area on the right side. That is, the address conversion is performed here.

After being stored in the memory 36 in this way, the data is sequentially read out in the horizontal direction and supplied to the inner code generating circuit 38, where the parity IP of the inner code is read.
Is added as shown below.

D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 I01 I02 I03 I04 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 I11 I12 I13 I14 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 I21 I22 I23 I24 D30 D31 D32 D33 D33 D35 D36 D37 D38 D39 I31 I32 I33 I34 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 I41 I42 I43 I44 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 I51 I52 I53 I54 000 001 002 002 003 004 005 006 007 008 009 I61 I61 I64 010 011 012 013 014 015 016 017 018 019 I71 I72 I73 I74 020 021 022 023 024 025 040 041 042 043 I81 I82 I83 I84 030 031 032 033 034 035 050 051 052 053 I91 I92 I93 I94

Here, the data with I at the right end is the parity of the inner code. In this way, the parity I of the inner code is
After P is added, the data is read in the horizontal direction in order from the top.

When the product code format data string thus output is applied to a digital VTR as shown in FIGS. 14 and 15, for example, it is recorded so as to form an inclined track on the magnetic tape. It

At this time, in this example, as shown in FIG. 8, when forming a recording track on the magnetic tape, a not-shown plunge portion IN where the head is strong and an outlet portion OUT where the head separates from the magnetic tape. Data having a low degree of importance, for example, parity OP of an outer code is recorded in a portion corresponding to, and high frequency component data Hda is recorded in portions from both ends of these magnetic tracks to the center. The data Mda of the high-frequency component and the data Lda of the low-frequency component, which are highly important, are recorded in the stable central portion where the head and the magnetic tape hit.

By doing so, in the digital VTR, errors at the time of reproduction are reduced, and even when variable length coding is performed, the direct current component or the low frequency component which becomes the leading data is located near the central portion of the magnetic track. I can record it,
Even in the case of variable-length code data, a digital V for preventing an error in the leading data and performing a highly accurate recording / reproduction with a low error occurrence rate.
TR can be obtained.

Next, the configuration on the decoder side for performing error correction on the data having the product code configuration configured as described above will be described with reference to FIG.

In the figure, reference numeral 55 is an input terminal to which a data string of an inner code block is sequentially supplied from a reproduction system of a digital VTR (not shown), 56 is an input terminal to which an inner code start signal is supplied, and 60 is an ECC block start. It is an input terminal to which a signal is supplied.

Reference numeral 57 denotes an inner code decoder which synchronizes the data of the inner code block supplied through the input terminal 55 with the data of one inner code in synchronization with the inner code start signal supplied through the input terminal 56. The error correction process is performed using the parity IP of the inner code.

Data DA1 subjected to error correction processing by the inner code parity IP in the inner code decoder 57,
DA2, DA3 and the parity OP of the outer code are stored in the memory 5
8 are supplied. At this time, the memory control circuit 61 uses the inner code correction data timing signal supplied from the inner code decoder 57 and the ECC block start signal supplied via the input terminal 60 to write address signal, write enable signal, read address signal. , A read address signal and a read data timing signal are generated.

The data DA1, DA2, DA3 error-corrected by the parity IP of the inner code and the parity OP of the outer code are stored in the memory 58 by the write address signal and the write enable signal from the memory control circuit 61.

Then, by the read address signal and the read enable signal from the memory control circuit 61, they are sequentially read from the memory 58 in the outer code format, that is, in the vertical direction, and are supplied to the outer code decoder 59. The outer code decoder 59 reads the outer code type block data DA1, DA2, DA3 and the outer code parities OP1, OP2, OP3 read from the memory 58 based on the read data timing signal from the memory control circuit 61.

A read address signal is supplied from the memory control circuit 61 to the code length detection circuit 62. The code length detection circuit 62 obtains an outer code parity number control signal based on the read address signal from the memory control circuit 61, and supplies this to the outer code decoder 59 (the operating condition is the code length detection circuit 35 shown in FIG. 1). Is similar to). The outer code decoder 59 converts outer code parity OP1, OP2 and OP3 supplied from the memory 58 into outer code block data DA1, DA2 and DA3 based on the outer code parity number control signal from the code length detection circuit 62. Data DA1, DA2, which have been subjected to error correction processing and have been subjected to error correction processing,
DA3 is supplied to the memory 63.

The outer code decoder 59 also supplies an outer code timing signal to the memory control circuit 64. The memory control circuit 64 generates a write address signal, a write enable signal, a read address signal and a read enable signal based on the outer code timing signal from the outer code decoder 59. The error-corrected data DA1, DA2, DA3 supplied to the memory 63 is stored in the memory control circuit 6
A write address signal and a write enable signal from the memory 4 are stored in the memory 63, then read out in the horizontal direction, and output through the output terminal 64, for example, an inverse quantizing circuit, IDC of a reproducing system of a digital VTR (not shown).
After passing through a T (inverse discrete cosine transform) circuit, an error correction circuit, etc., it is output as a reproduced video signal.

Before explaining FIG. 10, the processing on the decoder side shown in FIG. 9 will be described with reference to FIGS. 11 and 12. In the following description, the encoding example with the encoder described in FIG.
This will be described as an example. That is, the encoder shown in FIGS.
A case will be described in which encoded data is recorded, transmitted, reproduced, or received in the same manner as the example described with reference to FIG.

The ECC block start signal shown in FIG. 11A is supplied to the input terminal 60 shown in FIG. 9, and the data of the inner code block shown in FIGS. 11B, 11C and 11D is sequentially supplied to the input terminal 55. That is, the data DA1, DA2,
Inner code block data in which the parity IP of the inner code is added to DA3 (only one is shown in FIG. 11B, but a plurality of these are supplied) is added to these data DA1, DA2, DA3 in the outer code direction, respectively. In the outer code direction, the inner code block data in which the inner code parity IP is added to the outer code parities OP1, OP2, and OP3 (only one is shown in FIG. 11C, but a plurality of these are supplied) is used. Inner code block data in which the inner code parity IP is added to the outer code parity OP1 and OP2 added to the data DA1 and DA2 (FIG. 11D).
, Only one is shown, but a plurality of them are supplied).

The positions indicated by the diagonal lines on the time axis in FIG. 11D are due to the memory operation on the encoder side as described above. That is, the area on the time axis indicated by the diagonal line should be the area of the parity OP3 of the outer code originally added to the data DA3, but as in the above-described example, the outer code of the outer code added to the data DA1. The parity number P1 of the parity OP1 is larger than the average parity number Ps, the parity number P2 of the outer code parity OP2 added to the data DA2 is the same number as the average parity number Ps, and the data D.
The parity number P of the parity OP3 of the outer code added to A3
If 3 is less than the average parity number Ps, the data DA
Out of the parity OP1 of the outer code added to 1, the number exceeding the average parity number Ps is allocated to the area for the parity OP3 of the outer code added to the data DA3.

Therefore, each data DA is placed in the corresponding area on the time axis when the decoder receives this data string.
When the same number of outer code parities are added to 1, DA2 and DA3, there is a parity OP1 that does not originally exist in the corresponding area on the time axis. In this example, O
Although it is P1, in the case of OP1, OP2, and OP3, that is, OP2 and OP3 are originally located in the area of OP1 on the time axis.
However, it is natural that OP1 and OP3 are assigned to the area of OP2 and OP1 and OP2 are assigned to the area of OP3.

In other words, in the product code configuration, the parity O of the outer code added to the data DA3 as shown in FIG. 11E.
In the remaining area of P3, the parity OP1 that exceeds the average parity number Ps of the outer code parity OP1 added to the data DA1 is allocated at the time of encoding (for this, refer to FIG. 5 and FIG. 6). Since it has been described in detail, it is omitted here).

The data supplied in the inner code block format as shown in FIGS. 11B, 11C and 11D is subjected to error correction processing by the inner code parity IP in the inner code decoder 57. The data after this is shown in FIGS. 11G, H and I, respectively. Now, these data shown in FIGS. 11G, H and I are stored in the memory 58. The array of each data in the storage area of the memory 58 has a product code configuration configured on the encoder side as shown in FIG. 11J. As shown in FIG. 11J, in this memory 58, the data DA1
Outer code parity O corresponding to the addresses R3 to R2 of
P3 (indicated by a broken line in the figure) is stored in the area of addresses R4 to R3 of the data DA3 as indicated by a solid line arrow in the figure. Also, as explained on the encoder side,
In this example, the average parity number Ps is the data DA2.
It is set to the same number as the parity number P2 of the parity OP2 added to.

Next, description will be made with reference to FIG. An ECC block start signal (see FIG. 12A) supplied from the memory 58 shown in FIG. 9 to the input terminal 60 causes the original data structure, that is, each data DA1, DA2, DA3 to be respectively provided as shown in FIG. 12B. Outer code OP1, OP
2 and OP3 must be read so as to have a configuration in which OP3 is added.

That is, by the address conversion described later,
After the outer code parity OP1 added to the data DA1 is read to the address R3 in the memory 58, the parity OP1 stored in the area of the outer code parity OP3 added to the data DA3 is continuously read.

Data is read from the memory 58 in the outer code direction as shown in FIG.
9 is supplied. At this time, the outer code decoder 59 is supplied with the outer code parity number control signal shown in FIG. 12C from the code length detection circuit 62. Then, as described above, the data DA1 of high importance is subjected to the error correction processing by the parity OP1 of P1 having the largest parity number, and the data DA2 of the next highest importance is the parity OP2 of P2 having the second largest parity number. The error correction process is performed, and the data DA3 of low importance is subjected to the error correction process with the smallest parity number P3.

The data subjected to the error correction processing by the outer code decoder 59 is stored in the memory 63 by the write address signal and the write enable signal from the memory control circuit 64 as shown in FIG. 12E, and then the memory control circuit 64. 12F is read out in the horizontal direction by the read address signal and the read enable signal, and then supplied to the reproducing circuit quantizer circuit, IDCT circuit, error correction circuit, etc. of the digital VTR as described above. It In the above description, the description of the error flag is omitted for convenience of description.

As described above, when the number of parity OPs exceeding the average number of parity Ps at the time of encoding is stored in the area of another parity OP and read, recorded, or transmitted, a reproduced signal, or The memory control circuit 61 shown in FIG. 9 performs the memory control for performing the error correction processing upon reception. here,
The memory control circuit 61 will be described with reference to FIG. Since the internal configuration of the memory control circuit 61 is the same as that of the memory control circuit 37 shown in FIG. 2, the same reference numerals are given and detailed description thereof will be omitted.

Here, the memory control circuit 37 shown in FIG.
Is different from the memory control circuit 61 in that
The counters 46 and 45 are used to generate the read address of the memory 58, and the address conversion circuit 47 uses the counter 4
The address conversion is performed based on the count value Y from 5 and the count value X from the counter 46, and the horizontal read address RX is output from the output terminal 49 and the vertical read address RY is output from the output terminal 50. 53 is used for generating the write address of the memory 58, and the horizontal write address WX is output from the output terminal 52.
Is output, and the vertical address WY is output from the output terminal 54.

The operation of the address conversion circuit 47 shown in FIG. 10 is similar to that of the address conversion circuit shown in FIG.
The conditions of the conversion operation in the example shown in FIG. 10 are as follows.

That is, when X ≦ Q1 and Y> R3,
The horizontal read address RX is given by X + Q2 + 1, and the vertical read address RY is Y + R2-.
Given by R3.

The counter 45 is reset when Q1 <X ≦ Q2 and Y ≧ R3 and when Q2 <X ≦ Q3 and Y ≧ R2.

Therefore, the memory control circuit 37 shown in FIG.
The output of is changed only from writing to reading, and there is no change in the circuit configuration, so all are given the same reference numerals. However, it is very preferable that the memory control circuit can be realized with the same configuration on the encoder side and the decoder side, because it leads to a significant reduction in circuit cost.

The operation of the entire circuit shown in FIG. 9 will be described with reference to FIG. 13 centering on the operation of the memory control circuit 61 shown in FIG.

13A and 13B are connected to the input terminal 55 shown in FIG.
Data DA1, DA2, DA of the inner code block shown in
3, inner code parity IP, and data DA1, D
Outer code parity OP1 and O added to A2 and DA3
P2, OP3, and the parity IP of the inner code are sequentially supplied,
The input terminal 60 is supplied with the ECC block start signal shown in FIG. 9C, and the input terminal 56 is supplied with the inner code start signal shown in FIG. 9D.

In the inner code decoder 57, error correction processing is performed based on the parity IP of the inner code as described above, as shown in FIGS. 13E and 13F. This is memory 5
8 and is stored in the memory 58 by the memory control circuit 61 shown in FIG.

Here, when a write ECC block start signal (not shown) is supplied to the counter 51, the counter 51 is reset, and further, the counting operation is started in synchronization with the inner code start signal, and the count value is changed in the horizontal direction. The write address WX is supplied to the memory 58. On the other hand, the write address WY in the vertical direction is the count value Y that is incremented by the carry signal after the address WX reaches the maximum value. Therefore, as shown in FIGS. 13E and 13F, the memory 58 stores data D in the inner code format.
A1, DA2, DA3 and parity OP1 of the outer code,
OP2, OP3, and the parity IP of the inner code are written.

At the time of reading, the inner code correction data timing signal shown in FIG. 13G is supplied to the memory control circuit 61. The outer code start signal generated by the timing generation circuit 41 shown in FIG. 10 by the inner code corrected data timing signal causes the counter 45 to start counting, and the count value Y of the counter 45.
Are sequentially supplied.

The address conversion circuit 47 monitors the count values from the counters 45 and 46, and checks the above-mentioned condition (X≤Q
1 and count values X and Y until Y> R3)
Is supplied to the memory 58 as read addresses RX and RY.

When the conditions are met, the parity numbers P1 and P2 of the parity OP1, OP2 or OP3.
Or data DA in which P3 does not reach the average parity number Ps
1, DA2 or DA3 outer code parity OP1, O
Parity number P1 of the parity OP1, OP2 or OP3 stored in the storage area of P2 or OP3,
Data D in which P2 or P3 exceeds the average parity number Ps
In order to read the parity OP1, OP2 or OP3 of the outer code added to A1, DA2 or DA3 from the memory 58, the horizontal read address RX is obtained by the count value X + Q2 + 1, and the vertical read address RY.
Is calculated from the count value Y + R2-R3, and these addresses RX and RY are supplied to the memory 58.

The data read from the memory 58 is read in the outer code format and has an array as shown in FIG. 13H. This data is supplied to the outer code decoder 59. On the other hand, the read address signal from the memory control circuit 61 is supplied to the code length detection circuit 62, whereby the code length detection circuit 62 obtains the outer code parity number control signal shown in FIG. 13J and sends it to the outer code decoder 59. Supply.

The outer code decoder 59 includes the memory control circuit 6
1 to the read data timing signal shown in FIG. 13I, the outer code decoder 59 reads the data of the outer code block from the memory 58 at the timing of this read data timing signal, and the outer code supplied from the code length detection circuit 62. Data DA1 and D1 according to the parity number control signal and the parity OP1, OP2 and OP3 of each outer code
Error correction processing is performed on A2 and DA3.

The data after the error correction shown in FIG. 13K is supplied to the memory 63. Then, this data is stored by the write address signal and the write enable signal supplied from the memory control circuit 64 based on the outer code timing signal (see FIG. 13L) from the outer code decoder 59, and thereafter, from the memory control circuit 64. The supplied read address signal and read enable signal (see FIG.
(See 3M) and is read out in the horizontal direction. In this way, the data whose error is corrected by the inner code parity by IP and the outer code parity OP (FIG. 13N
(See) is supplied to the reproducing system such as the digital VTR via the output terminal 64 as described above.

As described above, in this example, the parity number P of the outer code parity OP is changed and weighted in accordance with the importance of the data, and the parity OP corresponding to the average parity number Ps is averaged. It is assigned to an area of a parity OP smaller than the number of parity Ps, encoded, and at the time of decoding, the parity OP of which the number exceeds the average number of parity Ps is read from the area of the parity OP smaller than the average number of parity Ps to be the original parity OP. Since it is output continuously, without changing the code length of the synchronization code,
Moreover, since error correction can be performed with an error correction capability according to the importance of data, efficient error correction can be performed, and when applied to various electronic devices such as a digital VTR, the quality of reproduced or reproduced images can be improved. Degradation can be minimized.

Further, since the recording position of the magnetic track is selected according to the importance after weighting according to the importance as described above, it is possible to further suppress the deterioration of the image quality of the reproduced image.

In the above example, for convenience of explanation,
It is assumed that the data is DA1, DA2, DA3, and that the parity number P of the parity OP exceeds the average parity number Ps, the parity OP1 and the parity OP of the outer code of the data DA1.
Although the parity number OP of the outer code of the data DA3 is described as being less than the average parity number Ps, the parity is greater than the average parity number Ps even when the data is DA1 to DAn. The number of data DAs having the number P of parity OPs and the number of data DAs having the number of parity OPs of the parity number P smaller than the average parity number Ps do not matter. That is, when weighting N types of parity numbers of outer codes with respect to digital data of arrays of inner code formats having different degrees of importance, the number of data items of parity number Pn (where n = 1, 2, 3, ...). Σ (Pn-G) × Dn = 0
That is, the product code is configured to satisfy the relational expression (where G is an integer). Further, it can be applied not only to video as in the above example, but also to audio and other data.

In the above example, the data DA1,
As described above, the case where the areas corresponding to the importance are set to have the same width in the inner code direction as DA2 and DA3 (in the example given in the specification as actual data, different widths), The width W may be different for each data (individual data of the block data DA1, DA2, DA3). In this case, the product code has a configuration in which the number of parity OPs of the outer code gradually decreases from the above-mentioned product code in a stepwise manner in descending order of importance. Then, in the same manner as described above, the addresses of the outer code parities OP exceeding the average parity number Ps are expanded to the areas of the parity parity number not reaching the average parity number Ps by expanding the conditions described above. Can be obtained and stored.

In the above example, the amount of data itself is the same for the low frequency band, the middle frequency band, and the high frequency band component. However, for example, for the low frequency band and the middle frequency band data, the code length W described above is used. Speaking of which, each is for one sync, the code length W of the high frequency component data is for two syncs, and the ratio of the data to the parity in the code length of the outer code for the low frequency component is 1: 3.
(12 bytes and 36 bytes), the ratio of data to parity in the code length of the outer code in the middle band component is 1: 5.
(8 bytes and 40 bytes), the ratio of data to parity in the code length of the outer code in the low frequency component is 1:11.
(4 bytes and 44 bytes) may be used. here,
For example, sync data is 2 bytes and ID data is 2 bytes.
te, data 135 bytes, inner code parity 1
It may be 4 bytes and one sync may be 135 bytes.

Similarly, for example, the data of the low frequency band, the middle frequency band and the high frequency band component is the total of two syncs in terms of the code length W, and the ratio of the code length W of the low frequency band, the middle frequency band and the high frequency band is set. 1: 2: 3
In addition, the ratio of data to parity in the code length of the outer code in the low frequency component is 1: 2 (18 bytes and 36).
ratio of data to parity in the code length of the outer code in the middle band component is 1: 5 (9 bytes and 45 b).
yte), the ratio of data to parity in the code length of the outer code in the low-frequency component is 1: 6 (6 bytes and 48 bytes).
te). Here, for example, the sync data is 2
Byte, ID data 2 bytes, data 121b
y, the parity of the inner code is 12 bytes, and one sync is 121 bytes.

By the way, in such a case, in the former method, the code length of the outer code is always 48 bytes, and the code length of the inner code is one sync for the low band and the middle band, respectively.
Since the high frequency band is for two syncs, the address conversion operation of the data as described above is not necessary, and it is sufficient to adjust the data amount and the parity number of the outer code or to decide whether to fix it. Therefore, in this case, there is an advantage that the circuit configuration is further simplified.

In the latter method, the code length of the outer code is always 54 bytes, and the code length of the inner code is 1 sync when the low band and the middle band are combined, and 1 sync for the high band. If the inner code block is treated as the low band and the middle band, the address conversion operation of the data as described above is the address operation in the horizontal direction of the low band and the middle band. Therefore, in this case, there is an advantage that the circuit configuration is further simplified. In any case, even if such a method is adopted, the same effect as described above can be obtained.

As an example of implementation of the above two methods, for example, in the case of the former method, a signal having a sync 1 block length is used, and further, the outer code is synchronized with a signal of 48 pulses for 1 pulse. This can be realized by using a simple method such as reading the inner data and the parity of the outer code in this order.

The above-described embodiment is an example of the present invention, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0179]

According to the above-described method of constructing the product code of the present invention, when the number of parity of the outer code with respect to the digital data of the array of the inner code format having different importance is weighted to N types, the number of parity Pn (however, n = 1, 2, 3, ...
) (Pn-
G) × Dn = 0 (where G is an integer), so that the product code is configured to satisfy the relational expression, the code length of one block can be made uniform during recording or transmission, and
Since the weighting can be performed according to the degree of importance, the efficiency of error correction can be significantly improved, and the reproducibility of data can be maximized.

Further, according to the method of constructing the product code of the present invention described above, when the parity number of the outer code with respect to the digital data is weighted to N types and then read from the storage area, each read inner code block is read. Since the code lengths are the same, the code lengths can be adjusted and the processing can be performed according to the format or the like at the time of transmission or recording, and the external circuit can be performed without changing the circuit configuration. The number of code parities can be weighted to N types, which enables good recording and transmission of data, and improves reproduction or reproduction accuracy of received data as described above.

Further, according to the product code constituent device of the present invention described above, the parity of the outer code weighted based on the importance of the inner code format digital data having different importance is added to the outer code parity adding means 32. 33, 34 and 35, and the outer code parity adding means 32, 33 and 3
Since the inner code parity adding means 36, 37, and 38 add the inner code parity to the digital data of the inner code formats having different importances to which the outer code parity weighted by 4, 35 is added, It is possible to perform error correction with the error correction capability based on the degree of importance, and thereby reproducibility of data can be significantly improved.

According to the error correction device of the present invention described above, the parity of the inner code of the product code format in which the parity of the outer code weighted based on the importance is added and the parity of the inner code is further added is added. Error correction by the inner code error correction means 57, 58, 61 using
The outer code error correction means 5 uses the parity of the outer code weighted based on the importance of the digital data error-corrected by the inner code error correction means 57, 58, 61.
Since the error correction is performed in 9, 62, 63 and 64, the error correction can be performed with the error correction ability based on the importance, and the reproducibility of the data can be greatly improved.

According to the error correction device of the present invention described above, the parity of the outer code weighted based on the importance of the inner code format digital data having different importance is added to the outer code parity adding means 32, 33. 34, 35, and the outer code parity adding means 32, 33, 34,
The inner code parity adding means 36, 37 and 38 add the inner code parity to the digital data of the inner code format having different degrees of importance to which the outer code parity weighted by 35 is added and weighted based on the importance. The inner code error correction means 57, 58, 61 performs error correction using the inner code parity of the product code format digital data to which the outer code parity is added and the inner code parity is further added. Code error correction means 57, 58, 6
Since the outer code error correction means 59, 62, 63 and 64 perform the error correction by using the outer code parity weighted based on the importance of the digital data error-corrected in 1, at the time of recording or transmission. Since the code length of one block can be made uniform and weighting can be performed according to the degree of importance, the efficiency of error correction can be significantly improved, and thereby the reproducibility of data can be maximized. Furthermore, the circuit configuration can be simplified.

Further, according to the above-described product code constituent device or error correction device of the present invention, the digital data after the weighted outer code parity is added to the inner code format digital data by the outer code parity adding means is stored. Since the address control at the time of performing is performed by the address control means, it is possible to perform the storage with the vertical and horizontal code lengths of the product code being aligned, and thereby, when reading, the individual code lengths of the inner code format are the same. it can.

Further, according to the product code constituent device or the error correction device of the present invention described above, the horizontal write address signal from the horizontal write address signal generating means and the vertical write address signal from the vertical write address signal generating means. Based on the above, since the address conversion means performs the address conversion so that at least the product code array of the digital data has a uniform vertical and horizontal code lengths, in addition to the above-mentioned effects, a simple circuit configuration can be used efficiently. It is possible to control the arrangement of the product codes, which enables good data transmission.

Further, according to the error correction device of the present invention described above, an address for reading digital data in the product code format in which the parity of the outer code weighted based on the importance and the parity of the inner code are further added is read. Since the control is performed by the address control means, the original product code array data can be obtained with a simple circuit configuration.

Further, according to the error correction apparatus of the present invention described above, based on the horizontal read address signal from the horizontal read address signal generating means 46 and the vertical read address signal from the vertical read address signal generating means 45, Since the address conversion unit 47 performs the address conversion so that the digital data in which at least the product code array has a uniform vertical and horizontal code lengths, the address conversion unit 47 performs the address conversion, and in addition to the above-described effect, a simple circuit configuration is provided. Thus, the product code array can be restored efficiently, and good data can be reproduced.

According to the digital data recording / reproducing method of the present invention, when recording digital data of different importance, the most important digital data is recorded in the vicinity of the center of the recording track. Since the recording is sequentially performed from the center of the recording track to the outer side and the data is reproduced, the error of highly important data can be prevented and the accuracy of the reproduced data can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an encoder side of an embodiment of a product code configuration method and device and an error correction device of the present invention.

FIG. 2 is a configuration diagram showing a main part on an encoder side of an embodiment of a product code configuration method and device and an error correction device according to the present invention.

FIG. 3 is an explanatory diagram of a parity of a weighted outer code used for describing an embodiment of a method and an apparatus for constructing a product code and an error correction apparatus according to the present invention.

FIG. 4 is an explanatory diagram showing storage of a parity of a weighted outer code in a memory for explaining an embodiment of a method and an apparatus for constructing a product code according to the present invention and an error correction apparatus.

FIG. 5 is an explanatory diagram showing an original array of weighted outer code parities, which is used for describing an embodiment of a method and an apparatus for constructing a product code and an error correction apparatus according to the present invention.

FIG. 6 is an explanatory diagram showing storage of a parity of a weighted outer code in a memory for explaining an embodiment of a method and an apparatus for constructing a product code according to the present invention and an error correction apparatus.

FIG. 7 is a timing chart for explaining the operation of one embodiment of the method and apparatus for constructing a product code and the error correction apparatus according to the present invention.

FIG. 8 is a track configuration diagram for explaining a digital data recording / reproducing method of the present invention.

FIG. 9 is a configuration diagram on the decoder side of an embodiment of a product code configuration method and device and an error correction device of the present invention.

FIG. 10 is a configuration diagram showing a main part on a decoder side of an embodiment of a method and an apparatus for constructing a product code and an error correction apparatus according to the present invention.

FIG. 11 is an explanatory diagram showing a code array at the time of decoding, which is used for explaining an embodiment of a method and an apparatus for forming a product code and an error correction apparatus according to the present invention.

FIG. 12 is an explanatory view showing a code array at the time of decoding for explaining an embodiment of a method and an apparatus for constructing a product code and an error correction apparatus according to the present invention.

FIG. 13 is a timing chart for explaining an operation at the time of decoding for explaining an embodiment of a method and an apparatus for constructing a product code and an error correction apparatus according to the present invention.

FIG. 14 is a configuration diagram showing an example of a recording system of a digital VTR.

FIG. 15 is a configuration diagram showing an example of a reproduction system of a digital VTR.

FIG. 16 is an explanatory diagram showing a format of a product code.

[Explanation of symbols]

 32, 36, 58, 63 memory 33, 37, 61, 62 memory control circuit 34 outer code generation circuit 35, 62 code length detection circuit 38 inner code generation circuit 57 inner code decoder 59 outer code decoder

Claims (10)

[Claims] 1. When weighting N types of parity numbers of outer codes for digital data of arrays of inner code formats having different degrees of importance, parity numbers Pn (where n = 1, 2,
, ..., where Dn is the number of data, the product code is configured so as to satisfy the relational expression of Σ (Pn-G) × Dn = 0 (where G is an integer) Code construction method. 2. The read inner code block has the same code length when the data is read from the storage area after the number of parity of the outer code for the digital data is weighted to N types. A method of constructing a product code according to item 1. 3. Outer code parity adding means for adding the parity of the outer code weighted based on the importance to the digital data of the inner code format having different importance, and the outer code weighted by the outer code parity adding means. An inner code parity adding means for adding inner code parity to digital data of the above-mentioned inner code format with different importance added with code parity. 4. An inner code error for performing error correction using the parity of the inner code of the product code format digital data to which the parity of the outer code weighted based on the importance is added and further the parity of the inner code is added. Correction means and outer code error correction means for performing error correction using parity of the outer code weighted based on the importance of the digital data error-corrected by the inner code error correction means. Error correction device. 5. Outer code parity adding means for adding the parity of the outer code weighted based on the importance to the digital data of the inner code format having different importance, and the outer code weighted by the outer code parity adding means. An inner code parity adding means for adding the parity of the inner code to the digital data of the inner code format with the different importance added with the parity of the code, and the parity of the outer code weighted based on the importance, Further, an inner code error correction means for performing error correction using the inner code parity of the product code format digital data to which the inner code parity is added, and the digital data error-corrected by the inner code error correction means Outer code error correction means for performing error correction using outer code parity weighted based on importance An error correction device characterized by the following. 6. An address control means is provided for performing address control when storing the digital data after the outer code parity adding means adds the outer code parity weighted to the inner code format digital data. 6. The product code constituent device or error correction device according to claim 3 or 5. 7. The address control means comprises: a horizontal write address signal generation means for generating a horizontal write address signal; a vertical write address signal generation means for generating a vertical write address signal; A horizontal read address signal generating means for generating a read address signal; a vertical read address signal generating means for generating a vertical read address signal; a horizontal write address signal from the horizontal write address signal generating means; On the basis of the vertical write address signal from the vertical write address signal generating means, an address converting means for performing address conversion so that at least the product code array of the digital data has a uniform vertical and horizontal code lengths. Claim 6 characterized by the above Configuration device or error correction device for a product code. 8. An address control means is provided for performing address control when reading digital data in a product code format in which parity of an outer code weighted based on importance is added and further parity of an inner code is added. The error correction device according to claim 4 or 5, characterized in that: 9. The address control means comprises: a horizontal write address signal generation means for generating a horizontal write address signal; a vertical write address signal generation means for generating a vertical write address signal; A horizontal read address signal generating means for generating a read address signal; a vertical read address signal generating means for generating a vertical read address signal; a horizontal read address signal from the horizontal read address signal generating means; Address conversion for performing address conversion based on the vertical read address signal from the vertical read address signal generating means so that at least digital data in which the product code array has a uniform vertical and horizontal code length becomes the original array. That it consisted of means and Error correction apparatus of claim 8, symptoms. 10. When recording digital data having different importance levels, the most important digital data is recorded near the center of the recording track, and thereafter, sequentially from the center of the recording track to the outer side according to the importance level. A method for recording / reproducing digital data, characterized in that the data is recorded on and reproduced.