JPH0630085A - Communication equipment with insertion function of error code - Google Patents

Abstract

(57) [Summary] [Purpose] In a communication device having a monitoring function for judging whether the communication status is normal or abnormal, the monitoring function is provided without connecting a device for generating a signal for a test to the outside of the communication device. It is an object of the present invention to provide a communication device capable of performing the above test. An error insertion control circuit for controlling an error code insertion method, and a supervisory signal insertion circuit capable of inserting a plurality of forms of error code in a communication signal according to an output signal of the error insertion control circuit are provided. Is set to the test state, an error code is inserted from the supervisory signal insertion circuit into the communication signal so that it can be tested whether or not the supervisory function circuit operates normally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device having a monitoring function for determining whether or not the communication device is operating normally, and more particularly to a signal for a test provided outside the communication device. The present invention relates to a communication device that enables testing of a monitoring function without connecting an additional device that occurs.

[0002] A communication device has a synchronization monitoring function for preventing synchronization (backward protection) with an erroneous synchronization signal, and for preventing immediate out-of-sync determination due to an instantaneous code change of the synchronization signal (forward protection). , Has various functions for monitoring whether or not communication is normally performed, such as an error monitoring function for detecting or correcting code errors, and in many cases,
In the case of an abnormality, the monitoring function circuit issues an alarm.

If communication is continued without these monitoring functions operating normally, the information output from the receiving device during that time will be different from the information input to the transmitting device.
There is a possibility of causing great damage to the society using communication.

Therefore, in the shipping inspection of a company that manufactures communication devices and in the periodic inspection of companies that operate communication devices, in addition to the function and performance of the original communication, the monitoring function is strictly tested. .

[0005]

2. Description of the Related Art FIG. 5 is a diagram showing a configuration of a conventional communication device and a configuration for performing a monitoring function test thereof.

In FIG. 5, reference numeral 1 is a communication signal constituent circuit, and 2
Is a supervisory signal generating circuit, 3a is a supervisory signal inserting circuit, 5 is a transmitting circuit, and 1, 2, 3a and 5 constitute a transmitting device. Reference numeral 6 is a receiving circuit, 7 is a supervisory signal separating circuit, 8 is a supervisory circuit, and 9 is a communication information reproducing circuit, and 6 to 9 constitute a receiving device.

When performing communication, the output terminal of the transmitter is connected to the transmission line and the input terminal of the receiver is connected to the transmission line to form a communication line. Reference numeral 10 is a test device.

The monitoring function as a communication device is usually provided in the receiving device, and in order to test this monitoring function, the test device 10 is installed between the transmitting device and the receiving device, and the test device is installed. In 10, the output signal of the transmitter is received, the signal required for the monitoring function to be tested is taken out, this signal is processed, and then sent to the receiver via the circuit having the same function as the transmitter circuit 5. Then, the monitoring circuit of the receiving device is activated.

For example, in the case of synchronous monitoring, since the synchronizing signal is changed by the test device, if the synchronous monitoring function is normal, a synchronous alarm is issued, and if the synchronous monitoring function is abnormal, the synchronous alarm is issued. There is no alarm. Further, the operation of the error correction circuit can be tested by performing an error correction operation with this signal and comparing the correction result with the signal before being processed by the test apparatus. In this way, the functionality of various supervisory circuits is tested.

However, the test equipment required here becomes large-scale for the following reasons. That is, in order to extract the signal required for the monitoring function from the output signal of the transmitting device, the functions of the receiving circuit 6 of the receiving device and the monitoring signal separation circuit 7 are required, and the signals necessary for the monitoring function test are output. Is required to have the same function as the supervisory signal insertion circuit 3a and the transmission circuit 5 of the transmitter.

Therefore, not only is the test apparatus economically expensive, but since the test apparatus and the apparatus under test are almost the same, in the case of a completely newly developed apparatus, the reliability of the function of the test apparatus is high. However, there is also a problem in reliability of the test result, and there is a possibility that the test cannot be performed smoothly.

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a means for solving such problems, which is economical, allows simple tests, and improves the reliability of the tests. To do.

[0013]

FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, 1 is a communication signal configuration circuit, 2 is a supervisory signal generation circuit, 3 is a supervisory signal insertion circuit, 4
Is an error insertion control circuit, 5 is a transmission circuit, and 1 to 5 constitute a transmission device.

Reference numeral 6 is a receiving circuit, 7 is a supervisory signal separating circuit, and 8
Is a monitoring circuit, 9 is a communication information reproducing circuit, and 6 to 9 constitute a receiving device. At the time of communication, the error insertion control circuit 4 is stopped from the outside, and a normal signal is transmitted without inserting an error in the supervisory signal.

On the other hand, at the time of the shipping inspection at the manufacturing company and the regular inspection at the operating company, the error insertion control circuit 4 is externally driven to insert an error into the supervisory signal and send it out.

[0016]

[Function] During shipment inspection at the manufacturing company and periodic inspection at the operating company, the error insertion control circuit 4 is driven from the outside,
An error is inserted in the supervisory signal and transmitted. In the receiving device,
The monitoring function is activated by the monitoring signal having this error inserted.

For example, when the monitoring function is the synchronization monitoring function, since an error is inserted in the synchronization signal, if the synchronization monitoring function is normal, the synchronization cannot be detected and the synchronization alarm is issued after the predetermined operation. Further, in the case of the error correction circuit, the signal output after the correction operation is compared with the signal before the error is inserted. In this way, the normality / abnormality of the monitoring function can be tested.

[0018]

FIG. 2 is a diagram showing details of the supervisory signal insertion circuit 3 and the error insertion control circuit 4 in the embodiment of the present invention.

In FIG. 2, 31 is an error code setting circuit for determining the number of error codes in the data, 32 is correct data and erroneous data according to the control signal of the error insertion control circuit.
A data selector 33 for selection is an insertion circuit for inserting a supervisory signal into the main signal or a signal obtained by inserting an error into the supervisory signal, and the supervisory signal inserting circuit is constituted by 31 to 33. Further, 41 is a logical product circuit, 42 is a set / reset flip-flop circuit, 43 is a counter that outputs a control signal for inserting an error, 44 is a time setting circuit that sets the duration of the control signal output by the counter, Reference numeral 45 is a differentiating circuit that generates a pulse at the falling edge of the output signal of the set / reset flip-flop circuit, and 46 is an inverting circuit.
The error insertion control circuit is composed of 1 to 46.

FIG. 3 is a block diagram showing an application device of the circuit of FIG.
It is a figure which shows the structure of a signal. In the communication signal configuration circuit, signals are processed in parallel with 8 bits (1 byte). The basic unit of signal is a cell consisting of 53 bytes.
The cell is divided into 5 bytes of header and 48 bytes of data. The last byte of the header 5 bytes is a supervisory signal obtained by performing a predetermined operation on the preceding 4 bytes of the header. An error code is inserted in 1 byte of this supervisory signal.

FIG. 4 is a time chart of the circuit configuration of FIG. The operation of the embodiment of the present invention will be described below with reference to FIG. 4, a clock signal 1 and a clock signal 2 are supplied from the communication code constituent circuit 1 of FIG. Is a test start signal, which is input from the outside of the transmitter to start the operation of the error insertion control circuit. Is an output signal of the set / reset flip-flop circuit 42, which is a signal which is set by the test start signal of and reset by the clock 1 of. A signal obtained by differentiating the trailing edge of this signal is input to the load terminal of the counter 43. The value to be loaded into the counter 43 by this load signal is input from the time setting circuit 44 to the load value input terminal of the counter 43. Further, the logical product of the clock 2 with the test start signal is calculated and input to the clock terminal of the counter 43.

The count value of the counter 43 becomes equal to the load value by the first clock pulse that arrives at the clock terminal after being loaded, and the count value increases by 1 each time the clock pulse arrives.

Here, assuming that the counter is a 3-bit binary counter and the load value is set to 5, the description will be continued. 3-bit binary counter is 0 to 7
The carry terminal outputs "H" when 7 is reached. Also, when loaded, the carry changes to "L".

Since the load value is set to "5" now, the count value of the counter 43 becomes "5" at the first clock pulse reaching the clock terminal, and the count value reaches 1 clock pulse thereafter. Advances "1" and outputs "H" to the carry terminal when it reaches "7". As shown in FIG. 2, since the negation of the carry output is applied to the enable terminal of the counter 43, the counter 43 holds the state when the count value becomes "7" and stops.
Therefore, the carry is also held at "H" and changes to "L" the next time it is loaded.

The negation of this carry output is applied to the word select terminal of the data selector 32, and the output signal of the error setting circuit 31 is selected only while the carry output is "H" to set the time for inserting an error. .

The operation of the circuit configuration shown in FIG. 2 has been described above, but hereinafter, the test of the monitoring function by this circuit configuration will be specifically described. In addition, an error correction function and a synchronous monitoring function will be taken up here as the monitoring functions.

First, in the case of the error correction function, the time for inserting an error is arbitrarily set, and the number of errors to be inserted is made equal to the number of correctable errors of the error correction circuit, and the error setting circuit 31 is used. Set. For example, when the target is a 1-bit error correction circuit, the error setting circuit is set to cause a 1-bit error.

A signal in which this error has been inserted is sent out and input to the error correction circuit of the receiving device for correction operation. Since a correct signal is known, it is possible to determine whether the error correction circuit is operating normally by matching the known signal with the output signal of the correction circuit.

Next, in the case of testing the synchronization monitoring function, the number of error pulses set by the error setting circuit is set to a number exceeding the correction capability of the error correction circuit. When the number of errors commensurate with the correction capability is inserted, if the receiving circuit is provided with an error correction circuit, it is corrected by the error correction circuit,
This is because the synchronization monitoring function cannot be tested. If the circuit has no error correction circuit, the number of error codes at the time of testing the synchronization monitoring function is arbitrary. For example, in the case of a 1-bit error correction circuit, it is set to 2 bits or more. However,
Depending on the capability of the error correction circuit, a 2-bit error of a specific pattern may be corrected, so it is desirable to insert as many errors as possible.

Here, the front protection function will be described. As a hypothesis, the number of front protection stages is 7. First, the load value of the counter is set to "6", and the error setting circuit 31
By this, the predetermined code number is erroneous, and when "H" is input to the word select terminal of the data selector 32, the signal in which the error is inserted is selected so as to be selected. In this way, when the test start signal is input, the error insertion control circuit 31 operates as described above. In this case, a pulse having a time equal to one cycle of the clock 2 is output, and the word selector of the data selector 32 is selected. Apply to the terminal. Therefore, a signal in which the synchronization signal is incorrect only once is transmitted.

On the receiving side, this signal is used for synchronization detection, but since the number of synchronization protection stages has not been reached, loss of synchronization does not occur if the function is normal. Then, set the load value to 5, apply the test start signal, and set the clock 2 to 2
A signal equal to the cycle is output, and the synchronization signal sends an erroneous signal twice.

If the synchronization monitoring circuit of the receiving device is normal,
After all it does not get out of sync. When this is repeated and the load value is set to "0" and the synchronization signal is erroneously transmitted seven times in succession, if the synchronization monitoring circuit is normal, the synchronization loss occurs.

If the synchronization monitoring circuit is abnormal, the synchronization is lost before the synchronization signal is erroneously repeated seven times. By repeating such a test, the test of the front protection function can be performed. In the case of the backward protection function, after the synchronization is lost once in the receiving device, an incorrect synchronization signal is inserted a set number of times for testing, sequential error insertion is eliminated, and the correct synchronization signal is inserted seven consecutive times. Until it is done, the normality / abnormality of the function is known depending on whether or not it is determined that synchronization is established.

The input of the test start signal and the setting input of the time setting circuit necessary for this test can be applied manually or automatically every time the test progresses one step. Further, since the time is set by setting the load value of the counter, the number of consecutive times is set to be erroneous. However, it is also possible to erroneously set an arbitrary number of times which is not necessarily continuous.

Also, the case of a device handling a parallel signal has been described as an example, but the same function can be realized also in a device handling a serial signal. Further, it is possible to add an error code insertion function to the receiving device to test the monitoring function. However, when testing the synchronization monitoring function with this configuration, a predetermined period is set while synchronization is not established. Since it becomes necessary to insert an error in the phase of 1), it is necessary to separately provide a synchronization signal detection circuit and supply a clock signal to the error insertion control circuit. However, it is still possible to perform a test with a much simpler configuration than that using a test device that is comparable in size to the communication device that is the device under test.

[0036]

As described above, the communication device is provided with the error insertion control circuit and the output of the error insertion control circuit.
By providing the circuit for inserting the error code into the supervisory signal, the supervisory function can be economically tested, and also the test of the newly developed device can be smoothly conducted.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing details of a supervisory signal insertion circuit and an error insertion control circuit in the embodiment of the present invention.

FIG. 3 shows a signal configuration according to an embodiment of the present invention.

FIG. 4 is a time chart of an example of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional communication device and a configuration at the time of testing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 communication signal configuration circuit 2 supervisory signal generation circuit 3 supervisory signal insertion circuit 4 error insertion control circuit 5 transmission circuit 6 reception circuit 7 supervisory signal separation circuit 8 supervisory circuit 9 communication information reproduction circuit

Claims (1)

[Claims] An error insertion control circuit (3) for controlling an error code insertion method in a communication device having a monitoring function for judging whether a communication state is normal or abnormal.
And a supervisory signal inserting circuit (4) capable of inserting an error code into a signal relating to a supervisory function among communication signals in accordance with an output signal of the error inserting control circuit. A communication device having an error code insertion function.