JPH06291201A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH06291201A JPH06291201A JP10518593A JP10518593A JPH06291201A JP H06291201 A JPH06291201 A JP H06291201A JP 10518593 A JP10518593 A JP 10518593A JP 10518593 A JP10518593 A JP 10518593A JP H06291201 A JPH06291201 A JP H06291201A
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- JP
- Japan
- Prior art keywords
- film
- manufacturing
- semiconductor device
- sio
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】 （修正有）
【目的】 製造工程を煩雑にすることなく、かつ製造装
置を複雑化することのない、Ｃｕ配線を用いた半導体装
置の製造方法を提供する。
【構成】 半導体基板１上に配線としての銅（Ｃｕ膜）
４を形成する過程と、前記Ｃｕ膜上に層間絶縁膜として
の酸化シリコン（ＳiＯ2）膜７を形成する過程とを有す
る半導体装置の製造方法に於いて、前記Ｃｕ膜４を形成
した後に、ＣＶＤ装置を用いて、前記Ｃｕ膜に水素（Ｈ
2）ガス及び所定のエネルギーを供給することにより、
前記Ｃｕ膜の表面に生成した自然酸化膜を還元する過程
と、前記還元過程に連続して、前記ＣＶＤ装置にて、前
記Ｃｕ膜の表面に酸化シリコン（ＳiＯ2）膜を形成する
過程とからなることを特徴とする半導体装置の製造方法
を提供することにより、Ｃｕ酸化膜の除去を、チャンバ
内で水素ガスを用いて還元することにより行い、製造装
置が複雑にならず、また製造工程が複雑にならない。
(57) [Summary] (Correction) [Object] To provide a method for manufacturing a semiconductor device using Cu wiring, without complicating the manufacturing process and without complicating the manufacturing apparatus. [Structure] Copper (Cu film) as wiring on the semiconductor substrate 1
In the method of manufacturing a semiconductor device, which comprises the step of forming Cu film 4 and the step of forming a silicon oxide (SiO 2 ) film 7 as an interlayer insulating film on the Cu film, after forming the Cu film 4, Using a CVD apparatus, hydrogen (H
2 ) By supplying gas and predetermined energy,
From the process of reducing the natural oxide film formed on the surface of the Cu film, and the process of forming a silicon oxide (SiO 2 ) film on the surface of the Cu film by the CVD apparatus in succession to the reducing process. By providing a method for manufacturing a semiconductor device, the Cu oxide film is removed by reducing with a hydrogen gas in a chamber, the manufacturing apparatus is not complicated, and the manufacturing process is It doesn't get complicated.
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に配線として銅（Ｃｕ）を用いた半導体装置の
製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using copper (Cu) as wiring.
【０００２】[0002]
【従来の技術】近年、半導体装置の配線としてＣｕ膜が
注目されている。特に多層配線の半導体装置の配線材と
してＣｕが使用される。2. Description of the Related Art In recent years, Cu films have attracted attention as wiring for semiconductor devices. In particular, Cu is used as a wiring material for a semiconductor device having multi-layer wiring.
【０００３】上記の、配線材としてＣｕを用いた多層構
造の半導体装置は、例えば図５に示すように、半導体基
板１上に開口部２を有する絶縁膜としてのＳiＯ2膜３を
ＣＶＤ法等により形成し、続いて配線材としてのＣｕ膜
４をスパッタリング法などにより堆積させた後、Ｃｕ膜
４上に層間絶縁膜としてのＳiＯ2膜７をＣＶＤ法等によ
り形成し、更にその上にＣｕ膜、ＳiＯ2膜の形成を繰り
返すことにより製造している。In the above-described semiconductor device having a multilayer structure using Cu as a wiring material, for example, as shown in FIG. 5, a SiO 2 film 3 as an insulating film having an opening 2 is formed on a semiconductor substrate 1 by a CVD method or the like. And then depositing a Cu film 4 as a wiring material by a sputtering method or the like, forming an SiO 2 film 7 as an interlayer insulating film on the Cu film 4 by a CVD method or the like, and further forming a Cu film thereon. It is manufactured by repeating the formation of the film and the SiO 2 film.
【０００４】しかしながら、実際には図６に示すよう
に、ＳiＯ2膜７の形成前に、Ｃｕ膜４の表面が外気に触
れて酸化されることによりＣｕ酸化膜５が自然生成する
ため、図７に示すように、Ｃｕ酸化膜５がＳiＯ2膜７と
Ｃｕ膜４との間に介在するようになることから、その後
に形成されるＳiＯ2膜７とＣｕ膜４との接着性能が悪化
し、ＳiＯ2膜７が基板１から剥離し易いという問題点が
あった。However, in reality, as shown in FIG. 6, since the surface of the Cu film 4 is exposed to the outside air and oxidized before the formation of the SiO 2 film 7, the Cu oxide film 5 is naturally generated. as shown in 7, since the Cu oxide film 5 is so interposed between the SiO 2 film 7 and the Cu film 4, the adhesive performance is deteriorated with the SiO 2 film 7 and the Cu film 4 formed thereafter However, there is a problem that the SiO 2 film 7 is easily peeled from the substrate 1.
【０００５】そこで、Ｃｕ膜４の表面に自然生成したＣ
ｕ酸化膜５を、ＳiＯ2膜７の形成前にエッチング法によ
り取り除く、或いはＣｕ酸化膜５が自然生成しないよう
にＣｕ膜及びＳiＯ2膜の成膜をロードロックを経由して
行う等の製造方法が取られてきた。Therefore, C naturally generated on the surface of the Cu film 4 is formed.
Manufacturing in which the u oxide film 5 is removed by an etching method before the formation of the SiO 2 film 7, or the Cu film and the SiO 2 film are formed via a load lock so that the Cu oxide film 5 does not spontaneously form. The method has been taken.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上述の
エッチング法によりＣｕ酸化膜５を除去する方法は、工
程が煩雑であり、またＣｕ膜５及びＳiＯ2膜７の形成を
ロードロックを経由して行うことによりＣｕ酸化膜５を
自然生成させないようにする方法は、製造装置が複雑に
なるという問題点があった。However, the method of removing the Cu oxide film 5 by the above-mentioned etching method has complicated steps, and the Cu film 5 and the SiO 2 film 7 are formed via a load lock. The method of preventing the Cu oxide film 5 from being spontaneously generated by performing it has a problem that the manufacturing apparatus becomes complicated.
【０００７】このような従来技術の問題点に鑑み、本発
明の主な目的は、製造工程が煩雑化することのない、ま
た製造装置が複雑化することのないＣｕ配線を用いた半
導体装置の製造方法を提供することにある。In view of the above problems of the prior art, the main object of the present invention is to provide a semiconductor device using Cu wiring which does not complicate the manufacturing process and does not complicate the manufacturing apparatus. It is to provide a manufacturing method.
【０００８】[0008]
【課題を解決するための手段】上述した目的は本発明に
よれば、半導体基板上に配線としてのＣｕ膜を形成する
過程と、前記Ｃｕ膜上に層間絶縁膜としての酸化シリコ
ン（ＳiＯ2）膜を形成する過程とを有する半導体装置の
製造方法に於いて、前記Ｃｕ膜を形成した後に、ＣＶＤ
装置を用いて、前記Ｃｕ膜に水素（Ｈ2）ガス及び所定
のエネルギーを供給することにより、前記Ｃｕ膜の表面
に生成した自然酸化膜を還元する過程と、前記還元過程
に連続して、前記ＣＶＤ装置にて、前記Ｃｕ膜の表面に
酸化シリコン（ＳiＯ2）膜を形成する過程とからなるこ
とを特徴とする半導体装置の製造方法を提供することに
より達成される。According to the present invention, the above object is to provide a process of forming a Cu film as a wiring on a semiconductor substrate and a silicon oxide (SiO 2 ) film as an interlayer insulating film on the Cu film. In a method of manufacturing a semiconductor device, including a step of forming a film, a CVD method is performed after the Cu film is formed.
A hydrogen (H 2 ) gas and a predetermined energy are supplied to the Cu film by using an apparatus to reduce the natural oxide film formed on the surface of the Cu film, and the reducing process. And a step of forming a silicon oxide (SiO 2 ) film on the surface of the Cu film in the CVD device.
【０００９】[0009]
【作用】このようにすれば、Ｃｕ膜の表面上に形成され
たＣｕ酸化膜の除去を、ＳiＯ2の成膜するチャンバと同
じチャンバ内で行うことができる。In this way, the Cu oxide film formed on the surface of the Cu film can be removed in the same chamber in which SiO 2 is formed.
【００１０】[0010]
【実施例】以下に、本発明の好適実施例を添付の図面に
ついて詳しく説明する。The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
【００１１】図１〜図４は、本発明が適用された一実施
例である半導体装置の製造方法を工程順に示す部分断面
図である。1 to 4 are partial cross-sectional views showing, in the order of steps, a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【００１２】まず、図１に示すように、半導体基板１上
に開口部２を有するＳiＯ2膜３を形成し、前記開口部２
の面内及び前記ＳiＯ2膜３上に電極・配線材料としての
Ｃｕ膜４をスパッタリング法等により成膜する。First, as shown in FIG. 1, a SiO 2 film 3 having an opening 2 is formed on a semiconductor substrate 1, and the opening 2 is formed.
A Cu film 4 as an electrode / wiring material is formed on the in-plane and on the SiO 2 film 3 by a sputtering method or the like.
【００１３】続いて、Ｃｕ膜４が成膜された前記半導体
基板１をＣＶＤ装置の反応チャンバ内にローディングし
た後、図２に示すように、還元剤としての水素（Ｈ2）
ガスを反応チャンバ内に流通させつつ、熱あるいは光等
のエネルギーを供給することによりＣｕ膜４の表面に形
成されたＣｕ2Ｏ等のＣｕ酸化膜層５を還元して、図３
に示すように酸化前のＣｕ膜の状態に復元する。Subsequently, the semiconductor substrate 1 having the Cu film 4 formed thereon is loaded into the reaction chamber of the CVD apparatus, and as shown in FIG. 2, hydrogen (H 2 ) as a reducing agent is added.
By supplying energy such as heat or light while circulating the gas in the reaction chamber, the Cu oxide film layer 5 such as Cu 2 O formed on the surface of the Cu film 4 is reduced, and FIG.
As shown in, the state of the Cu film before oxidation is restored.
【００１４】続いて、前記還元過程に連続して前記ＣＶ
Ｄ装置を用いて、還元されたＣｕ膜６上にＳiＯ2膜７を
成膜する。Subsequently, the CV is continuously supplied to the reduction process.
The SiO 2 film 7 is formed on the reduced Cu film 6 by using the D apparatus.
【００１５】[0015]
【発明の効果】以上の説明により明らかなように、本発
明による半導体装置の製造方法によれば、Ｃｕ膜の表面
に自然生成してＳiＯ2膜が剥離し易くなる要因としての
Ｃｕ酸化膜を、チャンバ内で水素ガスを用いて銅に還元
することにより、また、連続して同一チャンバ内でＳi
Ｏ2膜を形成することにより、ロードロックが不要とな
るため製造装置が複雑にならず、またエッチング法を用
いないので製造工程が複雑にならない。As is apparent from the above description, according to the method for manufacturing a semiconductor device of the present invention, a Cu oxide film is formed as a factor that is easily generated on the surface of the Cu film to easily peel off the SiO 2 film. , By reducing hydrogen to copper in the chamber and continuously in the same chamber.
By forming the O 2 film, the load lock is not required, so that the manufacturing apparatus is not complicated, and since the etching method is not used, the manufacturing process is not complicated.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明が適用された半導体装置の製造方法を図
２乃至図４と共に示す縦断面図である。FIG. 1 is a vertical cross-sectional view showing a method of manufacturing a semiconductor device to which the present invention is applied together with FIGS. 2 to 4.
【図２】本発明が適用された半導体装置の製造方法を図
１、図３及び図４と共に示す縦断面図である。FIG. 2 is a vertical cross-sectional view showing a method of manufacturing a semiconductor device to which the present invention is applied, together with FIGS. 1, 3 and 4.
【図３】本発明が適用された半導体装置の製造方法を図
１、図２及び図４と共に示す縦断面図である。FIG. 3 is a vertical cross-sectional view showing a method of manufacturing a semiconductor device to which the present invention is applied together with FIGS. 1, 2 and 4.
【図４】本発明が適用された半導体装置の製造方法を図
１乃至図３と共に示す縦断面図である。FIG. 4 is a vertical cross-sectional view showing a method of manufacturing a semiconductor device to which the present invention is applied together with FIGS.
【図５】従来の半導体装置の製造方法を図６及び図７と
共に示す縦断面図である。FIG. 5 is a vertical cross-sectional view showing a conventional method for manufacturing a semiconductor device together with FIGS. 6 and 7.
【図６】従来の半導体装置の製造方法を図５及び図７と
共に示す縦断面図である。FIG. 6 is a vertical cross-sectional view showing a conventional method for manufacturing a semiconductor device together with FIGS. 5 and 7.
【図７】従来の半導体装置の製造方法を図６及び図７と
共に示す縦断面図である。FIG. 7 is a vertical cross-sectional view showing a conventional method of manufacturing a semiconductor device together with FIGS. 6 and 7.
１ 半導体基板 ２ 開口部 ３ ＳiＯ2膜 ４ Ｃｕ膜 ５ Ｃｕ酸化膜 ６ 還元後のＣｕ膜 ７ ＳiＯ2膜1 Semiconductor Substrate 2 Opening 3 SiO 2 Film 4 Cu Film 5 Cu Oxide Film 6 Cu Film after Reduction 7 SiO 2 Film
Claims (1)
形成する過程と、前記Ｃｕ膜上に層間絶縁膜としての酸
化シリコン（ＳiＯ2）膜を形成する過程とを有する半導
体装置の製造方法に於いて、 前記Ｃｕ膜を形成した後に、ＣＶＤ装置を用いて、前記
Ｃｕ膜に水素（Ｈ2）ガス及び所定のエネルギーを供給
することにより、前記Ｃｕ膜の表面に生成した自然酸化
膜を還元する過程と、 前記還元過程に連続して、前記ＣＶＤ装置にて、前記Ｃ
ｕ膜の表面に酸化シリコン（ＳiＯ2）膜を形成する過程
とからなることを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device, comprising: a step of forming a Cu film as a wiring on a semiconductor substrate; and a step of forming a silicon oxide (SiO 2 ) film as an interlayer insulating film on the Cu film. In the above, after forming the Cu film, hydrogen (H 2 ) gas and predetermined energy are supplied to the Cu film using a CVD apparatus to reduce the natural oxide film formed on the surface of the Cu film. And the reduction process, in the CVD apparatus, the C
and a step of forming a silicon oxide (SiO 2 ) film on the surface of the u film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10518593A JP3399583B2 (en) | 1993-04-06 | 1993-04-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10518593A JP3399583B2 (en) | 1993-04-06 | 1993-04-06 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06291201A true JPH06291201A (en) | 1994-10-18 |
| JP3399583B2 JP3399583B2 (en) | 2003-04-21 |
Family
ID=14400624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10518593A Expired - Fee Related JP3399583B2 (en) | 1993-04-06 | 1993-04-06 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3399583B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6440844B1 (en) * | 1997-07-08 | 2002-08-27 | Fujitsu Limited | Semiconductor device with copper wiring and its manufacture method |
| JP2002530845A (en) * | 1998-11-17 | 2002-09-17 | アプライド マテリアルズ インコーポレイテッド | Removal of oxides or other reducible contaminants from substrates by plasma treatment |
| US8183150B2 (en) | 1998-11-17 | 2012-05-22 | Applied Materials, Inc. | Semiconductor device having silicon carbide and conductive pathway interface |
| JPWO2016157616A1 (en) * | 2015-03-27 | 2017-04-27 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
-
1993
- 1993-04-06 JP JP10518593A patent/JP3399583B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6440844B1 (en) * | 1997-07-08 | 2002-08-27 | Fujitsu Limited | Semiconductor device with copper wiring and its manufacture method |
| JP2002530845A (en) * | 1998-11-17 | 2002-09-17 | アプライド マテリアルズ インコーポレイテッド | Removal of oxides or other reducible contaminants from substrates by plasma treatment |
| US8183150B2 (en) | 1998-11-17 | 2012-05-22 | Applied Materials, Inc. | Semiconductor device having silicon carbide and conductive pathway interface |
| JPWO2016157616A1 (en) * | 2015-03-27 | 2017-04-27 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| CN107430999A (en) * | 2015-03-27 | 2017-12-01 | 三菱电机株式会社 | Semiconductor device and its manufacture method |
| US10276502B2 (en) | 2015-03-27 | 2019-04-30 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3399583B2 (en) | 2003-04-21 |
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