JPH0629749Y2 - Multicore cable delay time difference measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a multi-core cable delay time difference measuring device for simply measuring the delay time difference between a plurality of cables, and more specifically, a color video The present invention relates to a multi-core cable delay time difference measuring device that is effective when measuring the signal delay time difference of three coaxial cables that transmit signals and adjusting so as to eliminate the relative time difference.

(Prior Art) In the case of transmitting a color video signal using three coaxial cables, if a signal delay time difference exists between the three coaxial cables, a problem such as color shift occurs. .

In order to correct such a problem, it is necessary to accurately obtain the delay time difference between the three coaxial cables.

FIG. 4 is a conceptual diagram showing a case where a delay time difference of a conventional cable is measured.

The single pulse generation means PG is connected to one end of the cable to be measured, the oscilloscope OS is connected, the single pulse is applied from one end of the cable, and the pulse and the signal reflected at the other end are observed by the oscilloscope OS. By doing so, the delay time is known from the interval between both pulses.

(Problems to be solved by the invention) However, in such a measuring device, since it is necessary to repeat the same measurement for each cable and calculate the delay time difference between each cable, the measurement condition may be different, and the accurate measurement may be required. There is a problem that the delay time difference cannot be obtained and the simplicity is lacking.

The present invention has been made in view of such a problem, and an object thereof is to realize an apparatus capable of accurately measuring a delay time difference with a simple configuration.

(Means for Solving the Problems) FIG. 1 is a block diagram showing the basic configuration of the present invention. In the figure, 1 is a multi-core cable to be measured CB1 to CB
Pulse applying means 21 to 23 for simultaneously applying a single-shot pulse to one end of each of 3 is multi-core cables CB1 to C to be measured.
A plurality of time measuring means for measuring the time from applying a single pulse to one end of B3 until receiving a reflected wave from the other end in the open state, and 3 are time data from the plurality of time measuring means. The data extracting means 4 for inputting each of them and extracting the largest or smallest data of the time data calculates the delay time difference between the respective cables from the extracted data and the remaining other time data, and the calculation result. Is a calculation display means for displaying.

(Operation) The pulse from the pulse applying means 1 is applied to one end of each cable to be measured and also to each time measuring means,
Start time measurement. The pulse reflected at the other end of the cable to be measured returns to the original state and stops the time measurement of the time measuring means.

The data regarding the round-trip time of the pulse obtained by each time measuring means is applied to the data extracting means 3, and here, for example, the smallest data is extracted.

The calculation display means 4 calculates the difference based on the extracted smallest data, for example, and displays the delay time difference between them.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a configuration block diagram showing an embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals.

The pulse applying means 1 is composed of a timing generating circuit 10 and drivers 11 to 13 which input a signal from the timing generating circuit 10 and apply a drive pulse to one end of each of the cables CB1 to CB3. The timing generating circuit 10 includes a start button BT. The operation is started by pressing.

In the time measuring means 21 to 23, C1 to C3 input the reflected waves from the other ends of the cables CB1 to CB3, respectively, compare with the reference voltage Vref, and take out only pulse signals by the reflected waves, FF1 to FF1. FF3
Is a flip-flop, which is set and reset by a signal from the comparator. G1 to G3 apply the clock CLK from the timing generation circuit 10 to the counters CU1 to CU3 by the signal from the flip-flop,
It is a gate that is not applied.

Reference numeral 5 is a microprocessor for inputting data from each of the counters CU1 to CU3, and has a function as a data extraction means 3 and a calculation display means 4. Reference numerals 41 to 43 are display means whose display is controlled by the microprocessor 5, and each of the cables CB1 to C for the one having the smallest delay time.
The delay time difference of B3 is displayed.

A memory 6 is connected to the microprocessor 5, and stores a program for functioning as the data extracting means 3 and the operation display means 4, and data for operation.

The operation of the device configured as described above will be described below. Third
The figure is a time chart showing an example of the operation.

Prior to measurement, a plurality of measured cables CB1 to CB3
Is connected to the output end of the pulse applying unit 1 (driver) and the input ends of the time measuring units 21 to 23.

After connecting in this way, the start button BT is pushed as shown in (b). The timing generation circuit 10 receives the signal from the start button BT and applies a single pulse to each of the drivers 11 to 13 as shown in (a). The drive pulse simultaneously applied to one end of each of the cables CB1 to CB3 propagates inside the cable toward the other end, as shown in (d), (g), and (j). Further, this drive pulse is the flip-flop FF1 in the time measuring means.
-FF3 is set to the set state as shown in (e), (h), and (k). When the flip-flop is in the set state,
The gates G1 to G3 are opened and the counters CU1 to CU1 are opened.
The CU 3 starts counting the clock CLK from the timing generation circuit 10 as shown in (f), (i) and (l).

The drive pulse applied to one end of each cable travels inside the cable, is reflected at the other end, and eventually appears at one end.
This is detected as shown in (e), (g) and (j). These received pulses are respectively sent to the comparators C1 to C3.
Then, it is compared with the reference voltage, and the pulse such as noise is removed here, and the flip-flops FF1 to FF3 are reset.

When the flip-flop is reset, each counter CU
1 to CU3 stop counting clocks, and data corresponding to the delay time required for the drive pulse to make a round trip in each cable are obtained.

The microprocessor 5 inputs the data from each of the counters CU1 to CU3, first, the data extracting means 3 extracts, for example, the smallest one of these data, and then the arithmetic display means 4 The difference between each of the smallest data is calculated, and the result is halved.
The difference in the one-way delay times is calculated by multiplying it, and it is displayed on each display means 4
1 to 43 are displayed.

The value displayed on each display means in FIG.
The delay time of B2 is the smallest, and the difference between the delay times of the cables CB1 and CB3 is displayed.

In this embodiment, the cable having the smallest delay time is used as a reference, but the cable having the longest delay time is used as a reference to calculate and display the difference in the delay time of each cable. You may do it.

(Effect of the Invention) As described in detail above, according to the present invention, it is possible to directly know the difference in delay time of each cable by simultaneously adding a drive pulse to one end of a plurality of cables. Therefore, the difference in the delay times of the plurality of cables can be easily compensated based on this value, for example, by applying a delay line, and when measuring the delay time between the color CRT cables. Applied, there is a practical effect.

[Brief description of drawings]

FIG. 1 is a basic block diagram of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a time chart showing an example of its operation, and FIG. 4 is a conventional delay. It is a figure which shows the outline of a time measuring device. CB1 to CB3 ... Cable to be measured 1 ... Pulse applying means 21-23 ... Time measuring means 3 ... Data extracting means 4 ... Calculation display means 5 ... Microprocessor

Claims (1)

[Scope of utility model registration request] 1. A pulse applying means for simultaneously applying a single pulse to one end of a multicore cable to be measured, and a reflection from the other end in an open state after applying a single pulse to one end of the multicore cable to be measured. A plurality of time measuring means for respectively measuring the time until the wave is received, and a data extracting means for inputting time data from the plurality of time measuring means and extracting the largest or smallest of the time data A multi-core cable delay time difference measuring device comprising: a calculation display unit that calculates a delay time difference between the cables from the extracted data and the remaining other time data and displays the calculation result.