JPH0628718Y2 - Stopwatch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a stopwatch capable of setting a target split time.

[Prior Art and its Problems] In a stopwatch, a target time is set in advance, and an alarm sound is generated when a measurement time after starting matches a target time. The target time was set as follows. That is, first, the hour, minute, and second of the first split time are set, then the second hour, minute, and second are sequentially input, and then the third hour, minute, and second are sequentially input and set. . After the start, when the measurement time approaches or reaches the set split time, it sounds and informs. In addition, regardless of whether or not such a stopwatch is preferred, a warning sound is made at each split time. There was the inconvenience that all split times had to be cleared in order to prevent the sound. Further, as described above, the setting of each split time is the first hour, minute, second, second hour, minute, second, etc. The digit selection (time unit selection) and correction (selection) are performed in the same manner as normal time adjustment. Set to different units)
Since setting with and took time, the operation was troublesome. Further, when changing the set split time, the same operation as in the case of setting is required, and there is a problem that it takes time to change.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to provide a stopwatch capable of performing a switch operation that makes it extremely easy to set and change a target split time. Is what you are trying to do.

[Points of the Invention] In order to achieve the above-mentioned object, the present invention sets the first split time of a plurality of split time memory areas so that the split time of the second and subsequent split times is automatically set. The summary is that

[Embodiment] Next, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an electronic wrist watch having a stopwatch function. This electronic wrist watch operates by a micro program control system, and is a ROM serving as a control unit.
A (read-on memory) 11 stores a microprogram that controls all the operations of the electronic timepiece, and outputs microinstructions OP, AD, DA, and NA in parallel. here,
The micro instruction OP is input to the operation decoder 15 as an operation code, and the operation decoder 15 decodes the operation code and reads / reads data from the R / W input terminal of the RAM (random access memory) 13.
In addition to giving it as a write command, it also generates various control signals. Further, the micro instruction AD is RA via the data bus.
The address data is input to the Addr input terminal of M13. The micro instruction DA is output as numerical data. Further, the micro instruction NA is the next address data input to the address control unit 16, and the address data output from the address control unit 16 is stored in the ROM 11.
It is given to the Addr input terminal.

The RAM 13 is configured to have a replacement register, an arithmetic register, etc., and is used in timekeeping processing, key input processing, arithmetic processing, etc., executes data writing and reading operations under the control of the operation decoder 15, and RA
The data read from the DO output terminal of M13 is applied to the DI1 input terminal of the arithmetic unit 14 and displayed on the display unit 12. The operation unit 14 is an operation decoder 15
Various arithmetic operations are executed in accordance with the arithmetic command from, and the operation result data is given to the DI input terminal of the RAM 13 and read into the RAM 13. Also, the calculation unit 1
Reference numeral 4 outputs a signal c indicating the presence or absence of a carry and supplies it to the address control unit 16 to convert the address of the ROM 11. Further, the address control unit 16 is supplied with a clock clock of 100 Hz obtained by dividing the reference clock signal from the oscillating unit 18 by the frequency dividing circuit 19.
The clock processing is executed once every 1/100 second in accordance with the 00 Hz signal. The display unit 12 is composed of a liquid crystal display device. The key input signal output from the input unit 17 is applied to the DI1 input terminal of the calculation unit 14.

FIG. 2 shows a main part of the RAM 13, and the RAM 13 has a data memory area which can be freely written by a user in response to a key operation, in addition to the timing data, system control data and the like. That is, the RAM 1 shown in FIG.
In each row address area of No. 3, the first area T ₀ is a time register that stores the current time. In addition, the next area T
₁ is a stopwatch register, T ₂ is an auxiliary register, and T _{3 to} T _n are areas for storing a target split time. Here, hours, minutes, and seconds can be stored as the split time, and the respective split times are sequentially arranged and stored from T _{3 in} ascending order of time. Also, RA
Alarm flag memory T _2a in the register T ₂ to T _n of M13 which indicates whether mute or sound an alarm when it is the split time corresponding to each split _{time, T} 3a _...... are provided respectively (The alarm sounds when the value of the flag memory is "1", and does not sound when the value is "0").

In the last address area of the RAM 13, a mode flag register M, a setting flag register S, a measurement flag register C, a setting number register B, and an address storage register A are provided. The mode setting flag register M is the input unit 1
It is set by the mode switch 7 and when the flag is set in the mode setting flag register M (when it is "1"), it is the stopwatch mode, and when it is "0", it is the time mode. The setting flag register S is set by the switch of the input unit 17. When the setting flag register S has a content of "1", the split time is being set. The area has been cleared. Measurement flag register C is in turn measures the measurement time as a stopwatch when the measurement flag contents of the register C is "1" in what is set by the start switch of the input unit 17 in the register T _1, "0" Sometimes I don't measure. The set number register B stores the set number of split times, and the address storage register A stores the address area numbers T ₁ , T ₂ ,
T 3 one of the _...... and the like are stored.

FIG. 3 is a view showing the appearance of an electronic wrist watch incorporating the stopwatch of the present invention, and various push button switches S1 to S4 corresponding to the upper front input section 17 are arranged on the side of the watch case. . Here, S1 is a mode selector switch for switching between the time display mode and the stopwatch mode, and S2.
Is a switch for switching the time display mode of the stopwatch and the split time setting mode in the stopwatch mode, S4 is a time adjustment switch in the time display mode, and a switch for setting the split time in the stopwatch mode. S3 is a digit selection switch in the time correction mode and the split time designation mode, and the switch S1 is also used as a switch for stepping from the first switch to the second switch and the second switch to the third switch in the split time setting mode. . Further, S4 is a switch for setting whether or not to sound an alarm, that is, a switch for setting a flag for T _2a , T _3a ,. S3 is a start / stop switch for measuring the time of the stopwatch.

[Operation of Embodiment] First, the overall operation will be described with reference to the general flow of FIG. Step S1 shows a standby state until timing of timing or a key input request. When the key code corresponding to the operation key is output from the input unit 17, a key processing program corresponding to the key code is designated and the operation key is operated. In response, key processing described in detail later (step S2)
Is executed, the process returns to step S1. Also, 100Hz
When the clock signal of is output, the process proceeds to step S3 and the clock process is executed.

FIG. 5 is a flow chart showing the specific contents of the timing process of step S3 shown in FIG. First, step S5
Then, whether the flag is set in the measurement flag register C,
That is, it is determined whether or not the time of the stopwatch is being measured. If being measured to determine the time elapsed after the start by adding the data of a predetermined unit in time data stored in the address area T ₁ is a RAM13 stopwatch register proceeds to step S6. Next, in step S7, this elapsed time is stored in the area T ₂ , for example, 1
It is determined whether or not the actual split time (split time set and stored in the area T ₃ and transferred to the area T _{2 as} described later) has been reached. When it reaches the split time is determined, then the determined by examining whether to emit an alarm flag alarm flag memory T _2a (step S8). If the flag is set, an alarm is sounded at the split time in step S9. If the flag is not set, the sound is not emitted and the process proceeds directly to step S10. Here, the content of the address storage register A is incremented by 1, and the area in which the second split time is stored is stored in the address storage register A, for example. In step S11, contents of the area specified by the address storage unit register A, i.e., the second region T ₄
The actual split time is moved to the address area T ₂ , and the approach and arrival to the elapsed time are checked and prepared. Then step S
At 12, it is determined whether or not there is a clock LOCK for 1 second, and if there is, a normal time is measured, that is, + is added to the time register T ₀ .
The timekeeping process of 1 is performed (step S13), and
Display processing is performed in step S14. In this way, the split times are successively added to the address area T according to the time counting.
Is transferred to _2, is detected matches is compared with the elapsed time, inform and sound information if the setting of the flag in the alarm flag memory (T _2a).

FIG. 9 shows a display state changed by the switch operation, and FIG. 6 shows a specific example of the key processing of FIG. 4 and a flowchart when the switch S1 is operated. However, when the flag is not set in the flag register M, the time is displayed in the clock mode as shown in FIG. 9A, and when the switch S1 is operated, the step O in FIG.
In step 1, it is determined whether or not the flag is set in the flag register M. If the flag is not set, it is determined that the switch S1 is operated in the clock mode as shown in FIG. 9A.
The stopwatch mode shown in FIG. B is entered, the mode flag register M is flagged, and the current time display is cleared from the display unit 12 (step O2). When the flag is set in the flag register M in step O1, the process proceeds to step O3, and it is determined whether or not the flag is set in the setting flag register S, that is, it is in the split time setting mode. If the setting is not in progress (S = 0), the mode is returned to the time display mode shown in FIG. 9A, and the flag of the mode setting flag register M is cleared in step 04. If the split time is being set, the process proceeds to step O5 and it is determined whether or not the content of the set number register B is "0". That first split time determines whether the switch S1 in the setting of split time to the area T ₃ to be stored has been operated. The first split time, that is, the process proceeds to 1 when the switch S1 is in knots of target time setting is determined to have been operated step O6, it is determined whether the flag in the alarm flag memory T _3a is standing. That is, the alarm flag memory determines whether sounding upon reaching a split time of T _3a, not sounding RAM13 address proceeds to step O8 you are (not sound the alarm) area T ₃ and subsequent That area T ₃ all the contents of the split memory of ~T _n clear. Proceeds to if step O7 to sounding, automatically sets the RAM13 area _{T 3} and later split time. That is, as will be described in detail later, as shown in FIG. 9C, D, E, F, the first split time is designated by the switch S3, and the desired time is set at the digit designated by the switch S4. By doing so, for example, the target time of the first line can be set to 5 minutes and 30 seconds, and when the switch S1 is operated in the setting of the first line, the sixth time is set.
In step O7 of the figure, the second target time is calculated as an integral multiple of the first target × 2, the third target time is calculated as an integral multiple, and the first target time is in the region T ₃ and the second target time is calculated. After that, they are stored in the _respective areas T _{4 to} T _n .

For details of the target time storage processing in step O7, refer to Tenth
It looks like the figure.

That is, in step R1, sent from the area _{T 3} of the first run of the target time set in RAM13 in the calculation unit 13, and, at step R2, 2 numbers the operand is ROM1
It is output from 1 and sent to the calculation unit 13. Then, in step R3, the calculation of the first target time × 2 is performed, and the calculation result is transferred and stored in the area T ₄ of the RAM 13 as the second target time in step R5.

When the second target time is stored in steps R1 to R4, the storage process for the third target time is similarly performed. That is, in Step R5, 1 -th target time is sent to the arithmetic unit 13 from the area _{T 3} of the RAM 13, and, at step R6, 3 numbers as the operand is ROM1
It is output from 1 and sent to the calculation unit 13. Then, in step R3, the calculation of the first target time × 3 is performed, and the calculation result is transferred and stored in the area T ₅ of the RAM 13 as the third target time in step R7.

Hereinafter, similarly to the target time to N-th is obtained from the four first and is transferred to and stored in the area T ₄ through T _n, the target time storage processing is terminated. When this process ends, the next step O9
Then, the content of the set number register B is incremented by 1 to specify the next area, and the content (split time) of the specified area is moved to the address area T ₂ .

Therefore, the configuration was updated number register B in the next step O9 are set respectively target time in the region T ₃ through T _n by the switch S1 is operated Step O7 in the state of F in FIG. 9, the register B next target time specified in, i.e., as shown in FIG. 9 because two eye target time region T ₄ are transferred to the region T _2, in the following Figure 9 F is two-th target time 11 Minute 00 seconds (5 minutes 30 seconds x 2) is displayed.
If the switch S1 is operated while the second and subsequent target times are being displayed, the process directly proceeds from step O5 in FIG. 6 to step O9, so that only the next target time is displayed. The memory setting of the target time of step O7 is not performed.

FIG. 7 shows a flow chart when the switch S2 of the key processing of FIG. 4 is operated, and when the mode setting flag register M is flagged at step P1, it is the stopwatch mode and is set at step P2. When the flag is set in the middle flag register S, the time display mode of the stopwatch in FIG. 9B is entered, and the flag in the setting flag register S is cleared (step P3). If the flag is not set in the setting flag register S, that is, if the split time is not being set, the switch S2
Operating the a in setting or changing the split time, that changes the setting of the first run of the target time contents transferred to the address area T ₃ in the address area T ₂ (step P
4).

FIG. 8 shows a flow chart when the switch S3 of the key processing of FIG. 4 is operated. If the flag is set in the mode setting flag register M in step Q1, the stopwatch mode is set, and if the flag is set in the measurement flag register C in step Q2, the elapsed time is being measured as a stopwatch. By operating the switch S3 again, the measurement of the stopwatch is stopped, the content of the measurement flag register C becomes "0", and the number of the set number register B becomes "0" (step Q
3). If the elapsed time is not measured, proceed to step Q4,
If it is checked whether the split time is being set or not, and if the switch S3 is operated during the setting, the next digit is selected in step Q5, that is, from the hour digit to the minute digit, from the minute digit, as shown in FIG. 9C → D → E. The set digit is moved to the second digit.

After setting the second digit in FIG. 9E, as shown in FIG. 9F, the display body indicating the number of the display is selected, and in this state, the switch S4 is operated to select whether or not to sound the alarm. Then, 1 or 0 is written in the alarm flag memory T _3a . Configure the address of the address area T ₃ in the flow proceeds address memory register A step Q6 if being set in split time (step Q6).

Then transferred split time step Q7 the address area T ₃ in the address area T _2, followed becomes being measured as a stopwatch flag to the measurement flag register C is raised (step Q8).

[Effects of the Invention] As described in detail above, this invention automatically provides an integer multiple of the target time of the first and subsequent memories by providing a memory area for a plurality of target times and setting the first target time. Since the target time is set, all target times can be set with one setting, and the target time can be set easily and easily.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an electronic timepiece to which the invention is applied, FIG. 2 is a main configuration diagram of the RAM of FIG. 1, FIG. 3 is an external front view of the electronic timepiece, and FIG. FIG. 5 is a flowchart showing the specific contents of the SEC process shown in FIG. 4, and FIGS. 6 to 8 are flowcharts showing the specific contents of the key process shown in FIG. , Fig. 9 is a diagram showing the display state of each function, the first
FIG. 0 is a flow chart showing details of the processing in step O7 of FIG. 11 ... ROM, 12 ... display section, 13 ... RAM, 1
4 ... Calculation unit, 15 ... Operation decoder, 16
...... Address control unit, 17 ...... Input unit, 18 ・ ・ ・ Oscillation circuit, 19 ・ ・ ・ Division circuit.

Claims (1)

[Scope of utility model registration request] 1. A measuring means for counting time information by counting a reference signal based on a start / stop command, a plurality of storing means for storing a plurality of target times, and a first storing portion of the plurality of storing means. An input means for setting and inputting a first target time and a first target time set by this input means are calculated, and a target time which is an integral multiple of the first target time is stored in the remaining storage units of the plurality of storage means. A stopwatch provided with an arithmetic means for outputting and an alarm sound generating means for generating an alarm sound when the time information obtained by the measuring means matches each of the plurality of target times.