JPH06274240A - Clock signal supplying circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a clock signal supply circuit improved so that a clock signal can be safely supplied to a processor even when an operation of an oscillation circuit is abnormal due to some accident. A first oscillating circuit that self-oscillates at a first frequency corresponding to a level signal, a frequency / voltage converting circuit that converts the first frequency into a corresponding first voltage, and a predetermined reference voltage Comparing means for applying the first voltage to the other end of the input and comparing the magnitudes of these with each other to output as the previous level signal, and level inversion for outputting an inverted level signal obtained by inverting the previous level signal. Means, a second oscillating circuit which self-oscillates at a second frequency equivalent to the first frequency corresponding to the inverted level signal, and the first frequency and the second frequency based on the level signal. A switching circuit for switching and applying as a clock signal to the clock terminal of the processor, and a reset circuit for inputting the previous level signal and applying the reset signal to the reset terminal of the previous processor are provided, depending on the polarity of the previous level signal. The first oscillation circuit and the second oscillation circuit described above are switched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal supply circuit for supplying a clock signal to a processor of an electric device equipped with a microcomputer, and in particular, it is safe even when the operation of the oscillation circuit is abnormal due to some accident. The present invention relates to a clock signal supply circuit improved so that a clock signal can be supplied to a processor.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the configuration of a conventional clock signal supply circuit. Reference numeral 10 denotes an oscillator circuit, which is a processor 1 of an electric device equipped with a microcomputer (not shown) using a constant frequency signal f ₁ as a clock signal.
1 is applied to the clock terminal CLK.

In general, in order to supply a stable frequency signal f ₁ , the oscillator X made of crystal or ceramics is adopted in the oscillation circuit 10, and is inserted into the feedback circuit of the inverter INV1 to generate the frequency by self-excited oscillation. You are getting a signal.

[0004]

However, in the clock signal supply circuit as described above, for example, when an abnormality occurs in the vibrator X, the oscillation circuit 10 malfunctions, and one component defect causes malfunction of the processor 11. Furthermore, there is a problem that a serious accident will occur in the entire electric device equipped with the microcomputer.

[0005]

The present invention has a first structure corresponding to a level signal as a structure for solving the above problems.
A first oscillating circuit that oscillates at a frequency, a frequency / voltage converting circuit that converts the first frequency into a corresponding first voltage, and a predetermined reference voltage at one end of the input and the other end of the first
Comparing means for applying a voltage and comparing the magnitudes of these to output as a previous level signal, level inversion means for outputting an inverted level signal obtained by inverting the previous level signal, and corresponding to the previous inversion level signal. A second oscillation circuit that self-oscillates at a second frequency equivalent to the first frequency, and the first level and the second frequency are switched by the level signal and applied as a clock signal to the clock terminal of the processor. And a reset circuit that receives the previous level signal and applies the reset signal to the reset terminal of the previous processor. Depending on the polarity of the previous level signal, the first oscillator circuit and the second oscillator circuit may be provided. Is to be switched.

[0006]

[Operation] The first oscillator circuit oscillates at the first frequency in response to the level signal. The frequency / voltage conversion circuit is the first
The frequency is converted into a corresponding first voltage. The comparing means applies a predetermined reference voltage to one end of the input and the other end of the first voltage, compares the magnitudes of these, and outputs the result as a previous level signal.

The level inverting means outputs an inverted level signal obtained by inverting the previous level signal. The second oscillation circuit self-excitedly oscillates at the second frequency equivalent to the first frequency in response to the inverted level signal.

The switching circuit receives the first level signal according to the first level signal.
The frequency and the second frequency are switched and applied as a clock signal to the clock terminal of the processor. The reset circuit receives the previous level signal and applies the reset signal to the reset terminal of the previous processor.

Then, when an abnormality occurs in the first oscillator circuit,
When the frequency exceeds the normal range, the polarity of the previous level signal is inverted. Therefore, the switching circuit switches the first oscillation circuit to the second oscillation circuit and continuously supplies the clock signal to the previous processor. To do.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. The parts having the same functions as those of the conventional clock signal supply circuit shown in FIG. 3 are designated by the same reference numerals and the description thereof will be appropriately omitted.

Reference numeral 12 denotes an oscillator circuit, which is different from the oscillator circuit 10 shown in FIG. 3 in that it has a control input terminal T _c1 capable of controlling stop of oscillation. A NAND gate is used instead of the inverter INV1 of the oscillation circuit 10, and the level signal V _L1 is applied to the control input terminal T _c1 which is the other end of the input of the NAND gate.

The frequency signal f ₁ having a constant frequency generated at the output end of the oscillator circuit 12 is applied to the frequency / voltage conversion circuit 13, and the frequency / voltage conversion circuit 13 outputs the frequency signal f _1.
To a first voltage V ₁ corresponding to

Reference numeral 14 is a comparison circuit, and the first voltage V ₁ is applied to its non-inverting input terminal (+) and the reference voltage E _S1 is applied to its inverting input terminal (−). The level signal V _L1 having two values of “High” and “Low” is output to the output terminal by judging the magnitude.

This level signal V_L1Is the inverter INV
The level is inverted at 2 and the inverted level signal of the opposite polarity <V_L1
> As the control input terminal T of the oscillation circuit 15_c2Applied to.
This oscillator circuit 15 has the same structure as the oscillator circuit 12.
In the oscillation state, the frequency signal f ₂As self-excited oscillation
It

Reference numeral 16 is a switching circuit, and this switching circuit 16
Switches between the frequency signal f ₁ and the frequency signal f _{2 according} to the polarity of the level signal V _L1 and applies the clock signal f _C1 to the clock terminal CLK of the processor 11. Also, 17
Is a reset circuit, which outputs the reset signal V _R to the reset terminal RS of the processor 11 according to the polarity of the level signal V _L1 .

Next, the operation of the embodiment configured as described above.
Describe the work. Level signal V _L1Polarity is “High”
, The NAND gate is the same as the oscillation circuit 10 shown in FIG.
The same operation is performed, and the frequency signal f is output to the output terminal of the oscillation circuit 12.₁
Is output.

The frequency signal f ₁ is output to the frequency / voltage conversion circuit 13 and converted into the first voltage V ₁ here. This first voltage V ₁ is compared with the reference voltage E _S1 and
When the voltage V ₁ is higher than the reference voltage E _S1 , the level signal V _L1 having the “High” level is output to the output terminal thereof. Therefore, in this state, the oscillation circuit 12 can continue to oscillate.

However, since the level signal <V _L1 > of “Low” level is applied to the control input terminal T _c2 of the oscillation circuit 15 by the inverter INV2, the oscillation of the oscillation circuit 15 is stopped.

Here, when the oscillation of the oscillation circuit 12 is stopped due to a malfunction of the vibrator X, the first voltage V ₁ of the frequency / voltage conversion circuit 13 becomes lower than the reference voltage E _S1 ,
The level signal V _L1 appearing at the output terminal of the comparison circuit 14 is "Lo
w ”level.

In this case, the control input terminal T of the oscillation circuit 12
_{Since c1} is fixed to the “Low” level, its operation is completely stopped, but the oscillation circuit 15 oscillates because the control input terminal T _c2, which was fixed to the “Low” level, becomes the “High” level. To start.

On the other hand, the switching circuit 16 is switched from the frequency signal f ₁ to the frequency signal f ₂ by the level signal V _L1 of "Low" level and is transmitted to the clock terminal CLK of the processor 11 as a clock signal.

The reset circuit 17 is also "Low".
The reset signal V _R is output to the reset terminal RS of the processor 11 by the level signal V _L1 of the level. As described above, even when one of the oscillation circuits is stopped, the processor 11 continues to operate by receiving the clock signal from the other oscillation circuit.

FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention. Although in the embodiment of FIG. 1 taken measures for switching the oscillation circuit when the frequency signal f ₁ is lowered due to a failure of the oscillation circuit 12, the frequency signal f ₁ by the failure of the oscillation circuit 12 reversed in the embodiment of FIG. 2 Measures are also taken for switching of the oscillation circuit when the voltage becomes abnormally high.

In addition to the comparison circuit 14, a comparison circuit 18 and an AND gate 19 are provided at the output end of the frequency / voltage conversion circuit 13. The reference voltage E _S2 is applied to the non-inverting input terminal (+) of the comparator circuit 18, and the first voltage is applied to the inverting input terminal (−).
The voltage V ₁ is applied to each. In this case, the reference voltage is set so that E _S1 <E _S2 .

The comparator circuit 1 is provided at the input terminal of the AND gate 19.
4 and each output of the comparison circuit 18 are applied, and the AND gate 1
9 calculates the logical sum of these and outputs the level signal V _L2 to the output terminal thereof. Other configurations are the same as those shown in FIG.

Next, the operation of the embodiment configured as described above will be described. When the frequency signal f ₁ drops due to the failure of the oscillator circuit 12 and becomes lower than the voltage corresponding to the reference voltage E _S1 , the output of the comparison circuit 14 becomes “Low” level, and thus the level signal V _L2 also becomes “Low”. Then, the level is switched to the oscillation circuit 15 side as in the case of FIG.

On the contrary, when the frequency signal f ₁ increases due to the failure of the oscillation circuit 12 and becomes equal to or higher than the voltage corresponding to the reference voltage E _S2 , the output of the comparison circuit 18 becomes the “Low” level. The signal V _L2 also goes to the “Low” level, as shown in FIG.
Switching to the oscillation circuit 15 side is performed in the same manner as in the case of.

The voltage V ₁ is E _S2 corresponding to the frequency signal f _1>
When V ₁ > ES ₁ , the frequency signal f ₁ of the oscillation circuit 12 is in the range of the oscillation frequency which is judged to be in the normal range. In this case, the outputs of the comparison circuits 14 and 18 are both “Hig”.
Since it is at the "h" level, the level signal V _L2 is also maintained at the "High" level, and the oscillation of the oscillator circuit 12 is continued.

[0029]

As described above in detail with reference to the embodiments, according to the present invention, when an abnormality occurs in the main oscillation circuit, the sub oscillation circuit is automatically switched to a highly reliable clock. A signal supply circuit can be provided.

Further, when one of the oscillation circuits is operating, the other oscillation circuit is stopped, so that the current consumption of the circuit can be made almost the same as the conventional one.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a modified embodiment of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional clock signal supply circuit.

[Explanation of symbols]

 10, 12, 15 Oscillation circuit 11 Processor 13 Frequency / voltage conversion circuit 14, 18 Comparison circuit 16 Switching circuit 17 Reset circuit

Claims (1)

[Claims] 1. A first oscillating circuit which self-oscillates at a first frequency in response to a level signal, a frequency / voltage converting circuit which converts the first frequency into a corresponding first voltage, and a predetermined reference. Comparing means for applying the first voltage to one end of the input and applying the first voltage to the other end, comparing the magnitudes of these voltages and outputting as the level signal, and level inverting means for outputting an inverted level signal obtained by inverting the level signal. A second oscillating circuit which self-excitedly oscillates at a second frequency equivalent to the first frequency corresponding to the inverted level signal; and a processor clock by switching the first frequency and the second frequency by the level signal. A switching circuit for applying a clock signal to the terminal, and a reset circuit for receiving the level signal and applying a reset signal to the reset terminal of the processor; Ri said first oscillation circuit and the clock signal supply circuit, characterized in that for switching the second oscillating circuit.