JPH06268872A - Picture processing unit - Google Patents

Abstract

PURPOSE:To execute a dual operation by utilizing another companding processing section while one companding processing section performs processing of a binary picture in the picture processing unit provided with plural companding processing sections. CONSTITUTION:Upon receipt of another data while a management block 21-1 performs processing of data in response to a binary picture, a management block 21-n defines address data on an image bus 11 as an address signal of a storage section 54-n via an address selection circuit 52-n. On the other hand, code compression data are stored in a storage section 54-n via a data buffer 55-n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus having a plurality of compression / expansion processing units, such as a black and white image.
The present invention relates to an image processing device capable of processing a value image and a multi-tone image such as a halftone image or a color image.

[0002]

2. Description of the Related Art Conventionally, original information is read by a photoelectric conversion element such as a CCD and each pixel is read by a 1-bit "0" or "1".
2. Description of the Related Art A digital facsimile apparatus that converts the binary data into the binary data and transmits the binary data is widely used. However, in this type of device, since the reproducibility of a multi-tone image such as a photographic image is poor, attempts have been made to improve the conversion of each pixel into multi-bit image data of several bits according to shading and the like.

However, if the multi-gradation image data is transmitted as it is, a new problem arises in that not only the amount of information becomes huge and the transmission time becomes long, but also the scale of hardware becomes large.

In order to solve such a problem, for example, in Japanese Patent Laid-Open No. 62-95072, multi-gradation image data is decomposed into screens (bit planes) for each gradation bit, and the data of each bit plane is analyzed. A method of compressing and transmitting using a conventional binary data encoding method has been proposed.

[0005]

In an image processing apparatus that handles a multi-tone image, a compression / expansion processing unit is provided for each bit, and all the processing units operate when processing a multi-tone image. When processing a binary image, one processing unit and the other processing units are in a standby state.

However, in the above-mentioned prior art, the so-called dual operation is impossible because the compression / expansion processing unit in the standby state cannot be used for other functions. Specifically, one compression / expansion processing unit uses another compression / expansion processing unit while processing a binary image to accumulate received data, or decompresses accumulated coded data and outputs it. There was a problem that the device could not operate and the operating efficiency of the device was low.

An object of the present invention is to solve the above-mentioned problems of the prior art, and in an image processing apparatus having a plurality of compression / expansion processing units, one compression / decompression processing unit is processing another binary image while another image is being processed. The purpose is to enable dual operation using the compression / expansion processing unit.

[0008]

In order to achieve the above object, according to the present invention, a plurality of compression / expansion processing means and a 1-bit data string responding to a binary image are sent to any one of the compression / expansion processing means. A means for supplying and processing, a means for supplying and processing from the highest order to the lowest order of an n-bit data string in response to a multi-tone image to each compression / expansion processing means;
It is characterized in that it is provided with means for executing other data processing by using other compression / expansion processing means during processing of the bit data string.

[0009]

According to the above-mentioned structure, the one that responds to the binary image
When a bit data string is input, compression / expansion processing means other than processing the 1-bit data string is used to perform other operations such as compression / storage of received data or expansion / output of compressed data in parallel. Will be able to execute.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a schematic block diagram showing the structure of the main part of an image processing apparatus to which the present invention is applied.

The input unit 1 is, for example, an image scanner, which reads document information and converts it into image data of an electric signal, and quantizes the image data pixel by pixel to develop it into a bit data string.

The image processing unit 2 expands the bit data string input from the input unit 1 into a bit plane, encodes and compresses the bit plane, and stores the compressed data. The image processing unit 2 also expands the stored compressed data and outputs it to the output unit 3. To do. The output unit 3 prints out the image data output from the image processing unit 2 on a recording sheet.

The communication control unit 6 performs connection, disconnection, incoming call detection, etc. between the communication line network and the image processing apparatus, and at the same time, transmits image data between the image processing unit 2 and the partner station via the image bus 11. Send and receive.

The operation panel 8 has a numeric keypad, function keys, a display section, and the like. The ROM 7 stores a control program for operating this system, various basic data, and the like. The RAM 4 provides a work area and stores data set by the user from the operation panel 8. The main control unit (CPU) 5 controls the operation of this device according to a control program stored in the ROM 7.

FIG. 1 is a block diagram specifically showing the configuration of the image processing unit 2.

The image processing section 2 includes a selector section 20 and n.
It is composed of individual data management blocks 21-1 to 21-n. The selector unit 20 includes n switching units 201-
1 to 201-n, each management block 21
Are a buffer memory 211 and a compression / decompression unit 21 respectively.
2 and an image memory 213. The management blocks 21-1 to 21-n are commonly connected to each other via the image bus 11.

The reading unit 1, the port c ₁ for outputting bit data quantized (MSB) comprises to c _n a (LSB), likewise recording unit 3 also, the port c ₁ for inputting bit data (MSB) It is provided ~c _n the (LSB).

The output port c ₁ of the reading unit ₁ is connected to each switching unit 2
It is possible to connect to any of the management blocks 21-1 to 21-n through 01-1 to 01-n. Output ports c ₂ , c ₃ ... c
_n are switching units 201-2, 201-3, ... 201, respectively.
-N through each management block 21-2, 21-3, ... 2
Uniquely connected to 1-n.

On the other hand, the input port c ₁ of the recording section 3 is connected to each management block 21-1 to 21-n via each switching section 201-1 to 20n.
It is possible to connect with any of n. Input port c ₂ , c
₃ ... C _n are switching units 201-2, 201-3, ...
Each management block 21-2, 21- via 201-n
, 21-n are uniquely connected.

The operation of FIG. 1 will be described below with reference to the flow chart of FIG.

In step S10, it is determined whether or not all the management blocks 21-1 to 21-n are connected to the recording section 3, and if this determination is affirmative, step S11
Then, the operator is notified that the image data cannot be stored, and the process ends.

On the other hand, if the determination in step S10 is negative, it is determined in step S12 whether the read document is a binary image or a multi-tone image. If the image is a binary image, the process proceeds to step S13, and if it is a multi-tone image, the process proceeds to step S15.

In step S13, the CPU 5 detects the remaining memory capacity of the image memory 213 of each management block 21, and when it is determined that the remaining memory capacity of the image memory 213-1 is the largest, for example, the CPU 5 causes the switching unit 201 to operate.
-1 is controlled to connect the output port c ₁ of the reading unit ₁ to the management block 21-1.

In step S14, the document information is converted into electric signal image data by the reading unit 1, and each pixel of the image data is binarized and output from the output port c ₁ . As a result, the management block 21
The 1-bit buffer memory 211-1 sequentially stores 1-bit data corresponding to a binary image to form a bit plane. The bit plane is a compression / decompression unit 212-
After being encoded and compressed with 1, the image is stored in the image memory 213-1.

On the other hand, if it is determined in step S12 that the image is a multi-tone image, it is determined in step S15 whether all the management blocks 21 are empty. If all the management blocks 21 are empty, the process proceeds to step S16, and if any one of them is not empty, the process proceeds to step S18.

In step S16, the CPU 5 controls the switching units 201-1 to 201- _n to output the output ports c ₁ , c ₂ , ... C _{n of} the reading unit 1 and the management blocks 21-1 to 21-.
n are respectively connected. In step S17, the reading unit 1 quantizes each pixel of the image data with N bits, and outputs from the highest bit to the lowest bit of the n-bit data string in response to the multi-tone image to the output ports c ₁ , c ₂ , respectively. ... c
Output sequentially from _n . As a result, each management block 21-
Bit planes for each bit are stored in the image memories 213-1 to 21-n.

On the other hand, in step S18, the CPU 5 detects the remaining memory amount of the image memory 213 of each management block 21, and when it is determined that the remaining memory amount of the image memory 213-2 is the largest, for example, the CPU 5 switches the switching unit. 201-2 is controlled to connect the output port c ₁ of the reading unit ₁ and the management block 21-2.

In step S19, the reading unit 1 quantizes each pixel of the image data with N bits and sequentially outputs only the most significant bit (MSB) from the output port c ₁ . As a result, the image memory 21 of the management block 21-2
3-2 shows the MS of a multi-tone image quantized with N bits.
The bit plane for B is stored.

FIGS. 5, 6 and 7 are functional block diagrams for explaining the flow of data in each management block 21 in the present embodiment, and the same symbols as those used above represent the same or equivalent portions. .

When a binary image is processed by the management block 21-1, the address data and 1-bit data string output from the MSB output port C1 of the input unit 1 are compressed and expanded as shown in FIG. It is supplied to the unit 51-1 where only the 1-bit data string is encoded and compressed. Since the address selection circuit 52-1 selects the output of the compression / decompression unit 51-1 as the address data, the compression / decompression unit 51-1
The data coded and compressed in 1 is stored in the storage unit 54-1.
Is stored in the area designated by the address data.

On the other hand, in the case of processing a multi-tone image, as shown in FIG. 6, each address data and bit data output from each output port C1 to Cn of the input unit 1 is a binary image. Similarly to each of the management blocks 21-1 to 21-1
n in each of the storage units 54-1 to 54
Stored in -n.

If another data is received while the management block 21-1 is processing the data in response to the binary image, as shown in FIG. 7, for example, in the management block 21-n,
The address data on the image bus 11 becomes an address signal of the storage unit 54-n via the address selection circuit 52-n, while the encoded compressed data is stored in the data buffer 55-n.
It is stored in the storage unit 54-n via n.

As described above, in this embodiment, even when one management block 21 is used by the binary image storage operation, another data processing can be executed by using the other management block 21. Therefore, so-called dual operation is possible and the operation efficiency of the device is improved.

FIG. 2 is a block diagram showing the configuration of another embodiment of the image processing unit 2, and the same reference numerals as those used above denote the same or equivalent portions. The present embodiment is characterized in that a three-state buffer 214 is provided in parallel with the image memory 213.

The operation of this embodiment will be described below with reference to the flow chart of FIG. Note that the same or equivalent processing as that described above is executed in the steps denoted by the same reference numerals as those described above, and a description thereof will be omitted.

In this embodiment, a binary image is stored in one management block 21 (step S14a), and only the most significant bit plane of a multi-tone image is stored in one management block 21 (step S19a). ), If the memory becomes full during the accumulation, the remaining data is transferred to and stored in the image memory of another management block 21.

When it is determined in step S12 that the image is a binary image, and in step S13 the management block 21 having the largest remaining memory amount is selected, step S14 is performed.
In a, the storage of image information in the image memory of the management block 21 is started.

At this time, when the image memory 213 is in a memory full state, the 3-state buffer 214 provided in the image memory is turned on in step S21, and the subsequent data is stored in the 3-state buffer in step S22. It is stored in the image memory 213 of any other management block 21 via 214 and the image bus 11.

Similarly, when it is determined in step S12 that the image is a multi-tone image, and in step S18, the management block 21 having the largest remaining memory amount is selected, the image of the management block 21 is selected in step S19a. Accumulation of MSB in the memory is started.

At this time, when the image memory is full, the three-state buffer 214 provided in the image memory is turned on in step S23. In step S24, the subsequent data is accumulated in the image memory of any other management block 21 via the 3-state buffer 214 and the image bus 11.

FIG. 9 is a functional block diagram for explaining the flow of data in each management block 21 in this embodiment, and the same symbols as those used above represent the same or equivalent portions.

As described with reference to FIG. 5, the storage unit 54-1 is storing the bit plane corresponding to the binary image.
When the memory becomes full, as shown in FIG. 9, the address data output from the compression / expansion unit 51-1 passes through the address buffer 53-1 and the image bus 11,
For example, it is input to the management block 21-2. Similarly, the encoded compressed data output from the compression / decompression unit 51-1 is input to the management block 21-2 via the data buffer 55-1 and the image bus 11.

In the management block 21-2, the address data on the image bus 11 becomes an address signal of the storage section 54-2 via the address selection circuit 52-2, and the encoded compressed data passes through the data buffer 55-2. Storage unit 5
Since it is supplied to 4-2, the encoded compressed data is stored in the area designated by the address data in the storage unit 54-2.

According to the present embodiment, even if the image memory is in a memory full state during storage, the remaining data can be continuously stored in the other management block 21, so that a large amount of data can be reliably processed. Like

[0045]

As described above, according to the present invention, the following effects can be achieved. (1) When a 1-bit data string in response to a binary image is input, compression / expansion processing means other than processing the 1-bit data string is used to compress / store the received data or the compressed data. Other operations such as decompression and output of can be executed in parallel. (2) Even if the memory becomes full in one management block, the processing can be continued in the other management blocks, so that it is possible to reliably process a large amount of data.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of an image processing apparatus to which the present invention is applied.

FIG. 4 is a flowchart showing the operation of the first embodiment.

FIG. 5 is a block diagram for explaining the function of the first embodiment.

FIG. 6 is a block diagram for explaining the function of the first embodiment.

FIG. 7 is a block diagram for explaining the function of the first embodiment.

FIG. 8 is a flowchart showing the operation of the second embodiment.

FIG. 9 is a block diagram for explaining the function of the second embodiment.

[Explanation of symbols]

1 ... Input unit, 2 ... Image processing unit, 3 ... Output unit, 4 ... RA
M, 5 ... CPU, 6 ... Communication control section, 7 ... ROM, 8 ... Operation panel, 11 ... Image bus, 20 ... Selector section, 2
1-1 to 21-n ... Data management block, 201-1 to
201-n ... switching unit, 211-1 to 211-n ... buffer memory, 212-1 to 212-n ... compression / expansion unit, 21
3-1 to 213-n ... Image memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideyuki Hirose, 3-7-1, Fuchu, Iwatsuki City, Saitama Prefecture, Fuji Xerox Co., Ltd. (72) Susumu Yamamoto, 3-7-1, Fuchu, Iwatsuki City, Saitama Prefecture (72) Inventor Akio Tanabe 3-7-1 Fuchu, Iwatsuki City, Saitama Prefecture Fuji Xerox Co., Ltd.

Claims (2)

[Claims] 1. A first to n-th compression / expansion processing means comprising a memory for storing compressed data and mutually connected via a common bus, and a 1-bit data string responding to a binary image. Of the n-bit data sequence responding to the multi-tone image and the most significant to the least significant are supplied to the first to n-th compression / decompression processing means, respectively. And a means for causing another compression / expansion processing means to execute another data processing while one compression / expansion processing means is processing a 1-bit data string in response to a binary image. Image processing device. 2. Each of the compression / expansion processing means, when the remaining amount of memory is exhausted during storage of a 1-bit data string in response to a binary image, compresses and expands the remaining bit data string via the common bus. The image processing apparatus according to claim 1, further comprising means for transferring to the processing means.