JPH06268179A - Stacked semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [Object] To provide a laminated semiconductor integrated circuit device capable of increasing the capacity with little deterioration in device characteristics. A bit line driving MOS transistor 311 formed on the surface of the single crystal semiconductor substrate 1 and connected to a bit line, and a bit line driving MOS formed above the bit line driving MOS transistor. A memory element 111 or the like having a thin film transistor structure for controlling the gate potential of the transistor, a discharge transistor 411 or the like for discharging the charge accumulated in the gate electrode of the bit line driving MOS transistor, and a charge supply element for supplying the charge to the memory element. And a power line 41 and the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated semiconductor integrated circuit device having a thin film transistor structure.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, conventional memory elements, both NOR type shown in FIG. 16 and NAND type shown in FIG. 17, are formed on a semiconductor substrate 1. Although it is possible to improve the degree of integration of memory elements by miniaturization, it is naturally limited because it is necessary to make contacts. Further, in order to improve the degree of integration of elements on the semiconductor substrate, a three-dimensional device, that is, a laminated semiconductor integrated circuit is considered. Note that FIG.
17, (a) is a plan view, (b) is a cross-sectional view taken along the line AA ′ shown in (a), 1 is a semiconductor substrate, 2 is an N ⁺ diffusion layer, and 3 is a field. Oxide film, 4 is polysilicon, 5 is a bit line contact portion, 6 is a bit line wiring, and 8 is an insulating layer.

However, in the above laminated semiconductor integrated circuit, C
Since a polysilicon layer formed by the VD method or the like is used, a stacked semiconductor integrated circuit is generally called a leakage current generation or an ON current reduction at the time of off, compared with a device formed on a single crystal substrate. There is a problem that the device characteristics are inferior.

Writing to the conventional mask program ROM, that is, programming is performed by a field method or an ion implantation method (depletion or high Vth).
(Also referred to as conversion) or a contact method. Considering the turnaround time, the contact method has the shortest delivery time of the mask program ROM among the above methods, but the writing is performed in the contact step, and then the metal step is performed. . Considering the time margin of the program design, it is preferable that the writing process is as close to the final process as possible. or,
In the contact method, one contact hole is required for each 1-bit storage capacity, so that space is required for RO
There is a problem that it is not suitable for increasing the capacity of M.

The present invention has been made in order to solve such a problem, and provides a laminated semiconductor integrated circuit device capable of increasing the capacity with little deterioration of device characteristics despite using a thin film transistor structure. The purpose is to

[0006]

According to the present invention, a bit line driving MOS transistor formed on a single crystal semiconductor substrate and connected to a bit line, and formed above the bit line driving MOS transistor, A memory transistor having a thin film transistor structure for controlling the gate potential of the bit line driving MOS transistor, a discharging transistor for discharging the charge accumulated in the gate electrode of the bit line driving MOS transistor, and a charge supply to the memory transistor And a power line for use.

[0007]

In the conventional semiconductor memory, the charge in the memory transistor directly drives the bit line. However, by configuring as described above, the bit line driving M
The operation of the OS transistor is controlled by the charge of the memory transistor having the thin film transistor structure to drive the bit line. Therefore, the thin film transistor does not directly drive the bit line, but the leakage current at the time of off due to the thin film transistor structure is generated. Will not affect the bit line. In addition, by adopting the thin film transistor structure, the memory cells are laminated so as to increase the memory capacity.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a basic structure of a memory element formed by a laminated semiconductor integrated circuit device according to the present invention, and FIG. 3 is a plan view showing a memory element and the like actually formed on a semiconductor substrate. The same reference numerals are used to indicate each component. Note that the illustration of the insulating layer is omitted in FIG. Also, in FIG. 3, "a" or "d"
The legend showing the figure of each contact is shown in FIG.
11 to 15 show the planar shapes of the laminated constituent parts shown in FIG. In addition, FIG. 11 shows the ground (GN
D) 2 shows the shape of FIG. 12, FIG. 12 shows the shape of the gate 4,
FIG. 13 shows the shapes of the bit lines 61 and 62, and FIG.
Shows the shape of the polysilicon 7, and FIG. 15 shows the shape of the word line 24 and the like, the metal wiring 42 and the like.

In FIG. 1, 111 to 114, 12
Reference numerals 1 to 124, 211 to 214, and 221 to 224 are storage elements made up of P-channel transistors, and 411, 412, and 42.
Reference numerals 1 and 422 denote bit line driving MOS transistors 311, 312, 321 and
322 is a discharge transistor including a P-channel transistor for discharging the electric charge accumulated in the gate of 322. The constituent parts 111 to 114, 121 to 1
24, 211 to 214, and 221 to 224,
Elements 411, 412, 421, and 422 are formed as a three-dimensional device with a thin film transistor (hereinafter referred to as TFT) structure.

The source side of the transistors forming the memory elements 111 and 211 described above is connected to the power supply line 41 for supplying the charges accumulated in these memory elements, and the source side of the transistors forming the memory elements 121 and 221. Is
A power supply line 42 for supplying charges accumulated in these storage elements
Storage elements 111 to 114 are connected in series and storage elements 114, 124, 214 and 22 are connected in series.
The drain side of 4 is a discharge transistor 411,
It is grounded via 412, 421, and 422. Further, on the drain side of the memory elements 114, 124, 214, 224, bit line driving MOS transistors 311, 312, 321, 32, which are N-channel transistors, are provided.
Each of the two gates is connected. The drain side of the bit line driving MOS transistors 311 and 312 formed of N-channel transistors is the bit line 61.
The drain sides of the bit line driving MOS transistors 321 and 322 each of which is an N-channel transistor are connected to the bit line 62, and the bit line driving MOS transistors 311, 312, 321 and 32 are connected.
The source side of 2 is grounded. In addition, the storage element 11
The respective gates of 1 and the like are connected to the word line 21 and the like, and the gates of the discharging transistors 411 and 412 and the like are connected to control signal lines 51 and 52 for transmitting signals for controlling the on / off operation of the discharging transistors. It should be noted that the number of storage elements in one set is not limited to the above four, such as the storage elements 111 to 114, and
The conductivity types of various transistors are not limited to those described above.

Referring to FIG. 2, which is a sectional view taken along line AA ′ in FIG. 3, a portion of P ⁺ single crystal semiconductor substrate 1 in which N ⁺ diffusion layer 2 is not formed on the surface of P ⁺ single crystal semiconductor substrate 1. Above the line 70, the bit line driving MOS transistor 3 composed of, for example, an N-channel transistor is provided.
A gate 4 for forming 11 and the like is formed of polysilicon. Bit line wirings 61 and 62 made of tungsten are formed on the oxide film 8 covering the gate 4, and the bit line wirings 61 and the like are formed at the contact portions indicated by "a" in FIGS. It is connected to the N ⁺ diffusion layer 2 which constitutes the drain of the line driving MOS transistor 311 and the like.

On the oxide film 8 covering the bit line wirings 61 and 62, for example, polysilicon 7 having a TFT structure for forming a memory element 111 or the like including a P-channel transistor is formed. On the polysilicon 7,
Through the oxide film 8, word lines 21 to 24 and 31 to 34 which form the respective gates of the memory element 111 and the like are formed. Further, as shown in FIG. 6 showing a DD ′ cross section shown in FIG. 3, for example, the gate 4 of the bit line driving MOS transistor 311 is connected to the polysilicon 7 of the TFT structure. Incidentally, this connection point is shown by a contact indicated by "C" in FIGS. 1, 3, and 6.

Further, the source sides of the memory elements 111, 121, etc. are connected, and power supply lines 41, 42, etc. for supplying charges to the memory elements 111, etc. are formed on the polysilicon 7 via an oxide film 8. . The BB 'cross section shown in FIG. 3 is shown in FIG. 4, and the CC' cross section shown in FIG. 3 is shown in FIG.

As described above, the memory elements 114 and 124 constituted by the polysilicon 7 and the word lines 24 and 34, etc.
The electric charges held in the bit line 61 do not flow directly to the bit line 61 but to the bit line driving MOS transistor 31.
Since the bit lines 61 and the like are driven to flow to the bit lines 61 and the like via 1, 312 and the like, for example, as shown in FIGS. It can be formed above the region where the power MOS transistor 312 is formed and in a position where it is planarly overlapped with the formation region of the bit line driving MOS transistor 312, more specifically, the region of the contact “a”. . In this way, the storage elements can be integrated with higher density and the storage capacity can be increased.

Further, the charges held in the memory element 114 or the like constituted by the polysilicon 7 and the word line 24 and the like do not flow directly to the bit line 61, but via the bit line driving MOS transistor 311 and the like. Since the bit line 61 and the like are driven to flow to the memory cell 61 and the like, even if the memory element 114 and the like are deteriorated in device characteristics such as generation of a leak current at the time of off and a decrease in on-current, the deterioration is directly caused by that. The bit line 61 and the like are never driven.

A procedure for reading out the charges stored in the storage element 111 or the like in the stacked semiconductor integrated circuit thus configured will be described below by taking the storage element 112 as an example. Word lines 21-24 and 31-34 are all
A high (H) level, for example, 4 volts is set. At this time, the storage elements 111 to 114, 121 to 12
Since each of 4, 211 to 214, and 221 to 224 is configured as a P channel type, it is in an off state.

On the other hand, the control signal lines 51 and 52 are low.
(L) level, for example, 0 volt. At this time, since each of the discharging transistors 411, 412, 421, 422 is configured as a P-channel type, it is turned on and accumulated in the gate portions of the bit line driving MOS transistors 311, 312, 321, 322. Electric charge is removed and the potential of the gate is 0v-Vthp.
Can be lowered to the potential of. The Vthp means Vth (threshold voltage) of the memory element 111 or the like made of the TFT structure. For example, if Vthp is -0.6 V, the potential of the gate section is 0.6 V. .

The bit line driving transistor 31 is also provided.
Bit line driving MOS transistor 31 if 1 and the like are N-channel MOS transistors and their Vth exceeds 0.6 V, for example 1.0 V
1 etc. will be in an OFF state. The power supply lines 41 and 42 are set to 0 volt. After the above settings are completed, the bit line 61 is precharged to a potential of 2.5 volts, for example.

Next, the control signal line 51 is set to H level, for example, 4 volts, and the discharging transistors 411 and 421 are turned off. Further, the potential of the power supply line 41 is set to 4 volts. After that, the word lines 21, 23, 24 are set to L level, for example, 0 volt, and the storage elements 111, 113, 1
The 14th transistor is turned on. At this time, the memory element 112 is in the off state because the word line 22 is at the H level, and maintains the initial state. However, when data is being written to the storage element 112,
A current flows between the source and drain of the memory element 112, and the gate potential of the bit line driving MOS transistor 311 is raised to about 4 volts. As a result, the bit line driving MOS transistor 311 is turned on and the potential of the bit line 61 is lowered. Although not shown in FIG.
By connecting a sense amplifier to the bit line 61 or the like and reading the potential of the bit line 61 or the like, it can be determined whether or not data is written in the memory element 112.

The bit line driving MOS transistor 311 and the like described above may be of P-channel type. FIG. 10 shows a circuit diagram in the case of the P-channel type bit line driving MOS transistor 351 and the like. Further, in FIG. 10, the same components as those shown in FIG. 1 are designated by the same reference numerals.

Next, a procedure for writing data in the storage element 111 or the like, that is, a programming procedure will be described below with reference to FIG. As shown in FIG. 7A, the bit line wiring 6
The channel portion formed in the thin film 7 is determined by disposing the resist 10 on the thin film 7 of P-type polysilicon for the TFT structure formed on the upper surface of the oxide film. At this time, the entire area of the memory element for writing data is covered with the resist 10. As described above, the storage element 11
If data is written in 2, the resist 10 covers the entire portion corresponding to the memory element 112.

Next, by injecting BF ₂ using the resist 10 thus arranged as a cover, an N ⁺ portion is formed in the thin film 7 as shown in FIG. 7B, and the resist 10 is removed. After that, a gate oxide film is grown, gate polysilicon 8 is formed, and a TFT is formed.

As a result, the memory elements 111, 113, 11
Although 4 is formed as a TFT, in a region corresponding to the memory element 112 in the written state, the channel portion becomes a continuous P ⁺ region, which is a short state, that is, is always on. In this way, writing to the memory element is performed.

As shown in FIG. 9, the steps of forming the polysilicon thin film 7 and forming the gate polysilicon 8 are performed in reverse, that is, after forming the polysilicon 11 for word lines, Polysilicon thin film 7 for TFT construction
To form. By taking such a process order, only the metal wirings 41 and 42 of the power source line are formed on the upper layer of the polysilicon thin film 7, and as shown in FIG.
The channel portion of T and the metal wirings 41 and 42 do not overlap in a plane. Therefore, a laminated integrated circuit in which the steps of forming the metal wirings 41 and 42 are completed is produced in advance,
After receiving the order, write the memory element in response to the user's request,
That is, the wafer process can be completed by executing the program and then forming the protective layer. Therefore, the turnaround time of the wafer process can be shortened.

In the above-mentioned embodiment, the TFT structure portion has one layer, but in principle it can be composed of a plurality of layers as shown in FIG.

[0026]

As described in detail above, according to the present invention, the bit line driving MOS transistor drives the bit line by being controlled in operation by the charge of the memory transistor having the thin film transistor structure. It is possible to prevent the bit line from being affected by, for example, the generation of a leak current at the time of off due to the thin film transistor structure, instead of driving. Further, by adopting the thin film transistor structure, the memory cells can be stacked to increase the memory capacity.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration in one embodiment of a laminated semiconductor integrated circuit device of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ shown in FIG. 3, showing the structure of the laminated semiconductor integrated circuit device of the present invention.

FIG. 3 is a plan view showing a structure of a laminated semiconductor integrated circuit device of the present invention.

FIG. 4 is a cross-sectional view taken along the line BB ′ shown in FIG. 3, showing the structure of the laminated semiconductor integrated circuit device of the present invention.

5 is a cross-sectional view taken along the line CC 'shown in FIG. 3, showing the structure of the laminated semiconductor integrated circuit device of the present invention.

FIG. 6 is a cross-sectional view taken along the line DD ′ shown in FIG. 3, showing the structure of the stacked semiconductor integrated circuit device of the present invention.

FIG. 7 is a diagram showing a procedure for writing to a memory element of a stacked semiconductor integrated circuit device.

FIG. 8 is a circuit diagram showing a case where the memory element portion in the laminated semiconductor integrated circuit device of the present invention has a plurality of layers.

FIG. 9 is a diagram showing another example of the procedure for writing to the memory element of the stacked semiconductor integrated circuit device.

10 is a circuit diagram showing a configuration of a stacked semiconductor integrated circuit device in which the conductivity type of a transistor formed in the stacked semiconductor integrated circuit device of the present invention shown in FIG. 1 is reversed.

11 is a plan view of the ground (GND) 2 shown in FIG.

12 is a plan view of the gate 4 shown in FIG.

13 is a plan view of the bit lines 61 and 62 shown in FIG.

14 is a plan view of the polysilicon 7 shown in FIG.

15 is a plan view of the word line 24 and the like, the metal wiring 42 and the like shown in FIG.

16A and 16B are a plan view and a cross-sectional view showing a form of a memory element formed on a conventional semiconductor substrate.

17A and 17B are a plan view and a cross-sectional view showing a form of a memory element formed on a conventional semiconductor substrate.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 7 ... Polysilicon for forming thin film transistors, 21 to 24, 31 to 34 ... Word lines, 41, 42 ... Power supply lines, 51, 52 ... Control lines, 61,
62 ... Bit lines, 111 to 114, 121 to 124, 211 to 214, 221 to 224 ...
Storage element having thin film transistor structure, 311, 31
2, 321, 322 ... MOS transistors for driving bit lines, 411, 412, 421, 422 ... Transistors for discharging.

Claims (3)

[Claims] 1. A bit line driving MOS transistor formed on a single crystal semiconductor substrate and connected to a bit line, and a bit line driving MOS transistor formed in a layer above the bit line driving MOS transistor. A memory transistor having a thin film transistor structure for controlling the gate potential; a discharging transistor for discharging the electric charge accumulated in the gate electrode of the bit line driving MOS transistor; and a power line for supplying electric charge to the memory transistor. A laminated semiconductor integrated circuit device characterized by the above. 2. The stacked semiconductor integrated circuit device according to claim 1, wherein the bit line driving MOS transistor is an N-channel or P-channel type transistor. 3. The stacked semiconductor integrated circuit device according to claim 1, wherein at least one of the memory elements is formed at a position which overlaps with a formation region of the bit line driving MOS transistor in plan view.