JPH06268158A - Hybrid integrated circuit device and its manufacture - Google Patents

Abstract

(57) [Abstract] [Purpose] A hybrid integrated circuit device and a manufacturing method thereof,
A hybrid integrated circuit device is realized in a small number of steps without using the selective epitaxial growth method. [Structure] An emitter cap layer 22 is laminated on a substrate 21, an emitter layer 23 and a base layer 24 are laminated on a bipolar transistor region (BT region) and a high electron mobility transistor region (HEMT region), and a base of the BT region is laminated. The collector layer 25A is formed on the layer 24, and the channel layer 25 formed on the same layer as the collector layer 25A is formed on the base layer 24 in the HEMT region.
B is laminated, the carrier supply layer 26 is laminated on the channel layer 25B, the collector electrode 27 is formed on the collector layer 25A, and the gate electrode 28 is formed on the carrier supply layer 26 by the same film, and the base layer 24 in the BT region is formed. A base electrode 29 is formed, an emitter electrode 30 is formed on the emitter cap layer 22 in the BT region, and a source electrode 31 is formed on the carrier supply layer 26.
And the drain electrode 32 are formed of the same film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor such as a heterojunction bipolar transistor on the same substrate.
Transistor (HBT) and high electron mobility transistor (high electron mobility)
The present invention relates to an improved hybrid integrated circuit device in which a power transistor (HEMT) is created and a manufacturing method thereof.

At present, a hybrid integrated circuit device in which HBT and HEMT are formed on the same substrate is researched in order to construct one circuit by utilizing the characteristics of each of HBT and HEMT.
While it is being developed, there are still many problems that need to be resolved before it can be put to practical use.

[0003]

2. Description of the Related Art HBTs made of compound semiconductors have both excellent high-speed operability and high current drive capability, and
It has low phase noise characteristics (if necessary, it can be
house, Inc. Published by Fazal Ali, Adi
tya Gapta and other work "HEMTs and
HBTs: devices, fabrication;
(See Table 1.7 in "and circuits"), and is expected to be applied to digital and analog applications in the fields of ultra-high-speed operation and ultra-high frequency.

HEMT has low power consumption,
It has a low high-frequency noise characteristic and is excellent in high-speed operability, but it has drawbacks that it has a small current driving capability and a large phase noise.

Therefore, in order to make up for the drawbacks of the HBT and the HEMT with each other and to take advantage of their advantages, research and development of a hybrid integrated circuit device of the HBT and the HEMT are being actively conducted.

FIG. 11 is an HBT for explaining the conventional technique.
FIG. 3 is a cutaway side view of an essential part showing a hybrid integrated circuit device of HEMT and HEMT.

In the figure, 1 is a semi-insulating GaAs substrate,
2 is an n ⁺ -GaAs sub-collector layer, 3 is n-GaA
s collector layer, 4 is p ⁺ -GaAs base layer, 5 is n-
AlGaAs emitter layer, 6 n ⁺ -GaAs cap layer, 7 emitter electrode, 8 base electrode, 9 collector electrode, 11 undoped GaAs channel layer, 12 n
⁺ -AlGaAs carrier supply layer, 13 is a source electrode,
Reference numeral 14 is a drain electrode, and 15 is a gate electrode.

In this hybrid integrated circuit device, in the HBT region, by applying the selective epitaxial growth method, the sub-collector layer 2, the collector layer 3,
After the base layer 4, the emitter layer 5, and the cap layer 6 are grown, the emitter electrode 7 is formed, and the stepwise mesa etching is performed to form and complete the base electrode 8 and the collector electrode 9, and then the HEMT is completed. In the region, the channel layer 11 and the carrier supply layer 12 are grown on the substrate 1 by applying the selective epitaxial growth method, and then the source electrode 13 and the drain electrode 14 are formed and the gate electrode 15 is formed. Has been completed.

[0009]

The hybrid integrated circuit device described with reference to FIG. 11 merely forms the HBT and the HEMT separately on the same substrate.
Share both HBT and HEMT members, or
Since no consideration has been given to making the manufacturing processes of the various parts common to both, a process that adds the manufacturing process of the HBT and the manufacturing process of the HEMT is almost necessary, and the work is also troublesome. In addition, the manufacturing yield is extremely low.

As described above, since the HBT and the HEMT are produced independently, the growth of the semiconductor layer forming each device must depend on the selective epitaxial growth method,
In that case, it is difficult to grow a fine shape and the dimensional variation of each element becomes large, so that it is difficult to increase the degree of integration.

According to the present invention, the HBT and the HEM can be manufactured in a small number of steps without using the selective epitaxial growth method.
An attempt is made to realize a hybrid integrated circuit device made of T.

[0012]

According to the present invention, the characteristics of the semiconductor layer forming the HBT, the semiconductor layer forming the HEMT, and the electrodes forming the HBT and the electrode forming the HEMT are not adversely affected. Research was added to the device structure so that it could be shared in the range.

FIG. 1 is a cutaway side view of a main part of a hybrid integrated circuit device for explaining the principle of the present invention. In the figure, 21 is a substrate, 22 is an emitter cap layer, 23 is an emitter layer, 24 is a base layer, 25A is a collector layer, 2
5B is a channel layer, 26 is a carrier supply layer, 27 is a collector electrode, 28 is a gate electrode, 29 is a base electrode, 30
Is an emitter electrode, 31 is a source electrode, 32 is a drain electrode, and 33 is an element isolation region.

Further, (A) is an energy band diagram of a main part at the time of thermal equilibrium of HBT, and (B) is HEM.
Respective energy band diagrams at the time of thermal equilibrium of T are shown, E _V is the top of the valence band, E _C is the bottom of the conduction band, E _F is the Fermi level, 2DEG is the two-dimensional carrier gas layer. Shown respectively.

In the hybrid integrated circuit device shown in the figure, the collector layer 25A and the channel layer 25B are shared, and the entire structure is formed without using the selective epitaxial growth method.

Further, the collector electrode 27 and the gate electrode 28
Are made of the same material at the same time, and the emitter electrode 30, the source electrode 31, and the drain electrode 32 are made of the same material at the same time.

In the illustrated hybrid integrated circuit device, the base layer 24, the emitter layer 23 and the emitter cap layer 22 which are indispensable for the HBT region are also present in the HEMT region, but these semiconductor layers are HEMT. Since the channel layer 25B in the region, that is, the i-semiconductor layer is formed thickly, it has no influence on the operation of the HEMT. This is, for example, the energy band
It is also clear from the fact that the bending of the band does not occur as seen in the diagrams (A) and (B).

The collector layer 25A is the channel layer 25.
Although non-doped GaAs, which is a material common to B, is used, even if the collector layer 25A is non-doped, carriers crossing the base layer 24 do not pose any problem.
You can pour into 7.

FIG. 2 shows the energy in the vicinity of the collector layer when n-type, non-doped (i-type) and p-type materials are used.
It is a band diagram, and the same symbols as those used in FIG. 1 represent the same parts or have the same meanings. Base-collector voltage V when this data is obtained
_cb is -0.4 [V], and it can be seen from the figure that electrons injected from the emitter and traversing the base layer can reach the collector electrode by using any collector layer. .

Further, the collector electrode 27 is in Schottky contact with the collector layer 25A because it is formed simultaneously with the gate electrode 28 by using the same material. Like the transistor, the current flows in the direction in which it is drawn to the collector electrode 27, and since the direction is the direction in which the Schottky barrier has no rectifying property, no problem occurs.

From the above, in the hybrid integrated circuit device and the manufacturing method thereof according to the present invention, (1) a semi-insulating compound semiconductor substrate (for example, a semi-insulating GaAs substrate 2)
1) a one-conductivity type compound semiconductor emitter cap layer (for example, n ⁺ -GaAs emitter cap layer 22) laminated on the above, a bipolar transistor region and high electrons on the one-conductivity type compound semiconductor emitter cap layer. One conductivity type compound semiconductor emitter layer (for example, n-GaAs emitter layer 2) stacked in the mobility transistor region.
3), an opposite conductivity type compound semiconductor base layer (for example, p ⁺ -GaAs base layer 24) laminated in the bipolar transistor region and the high electron mobility transistor region on the one conductivity type compound semiconductor emitter layer, and A non-doped compound semiconductor collector layer (for example, a non-doped GaAs collector layer 25) laminated on the opposite conductivity type compound semiconductor base layer in the bipolar transistor region.
A) and a non-doped compound semiconductor channel layer (for example, a non-doped GaAs channel layer) which is formed in the same layer as the non-doped compound semiconductor collector layer and laminated on the opposite conductivity type compound semiconductor base layer in the high electron mobility transistor region. 25B), one conductivity type compound semiconductor carrier supply layer (for example, n ⁺ -AlGaAs carrier supply layer 26) laminated on the non-doped compound semiconductor channel layer, and the same film (for example, WSi film) as the non-doped compound semiconductor. A collector electrode (for example, collector electrode 27) formed on a collector layer and a gate electrode (for example, gate electrode 28) formed on the one conductivity type compound semiconductor carrier supply layer, and an opposite conductivity type compound for the bipolar transistor region. Base formed on the semiconductor base layer Pole (e.g. CrAu base electrode 2
9) and an emitter electrode (for example, an emitter electrode 30) formed on the same conductivity type compound semiconductor emitter cap layer made of the same film (for example, an AuGe / Au film) and the one conductivity type compound semiconductor. A source electrode (for example, a source electrode 31) and a drain electrode (for example, a drain electrode 32) which are separately formed on both sides of a gate electrode on the carrier supply layer, or

(2) One conductivity type compound semiconductor emitter cap layer (eg n ⁺ -GaAs emitter cap layer 22) and one conductivity type compound semiconductor on the semi-insulating compound semiconductor substrate (eg, semi-insulating GaAs substrate 21) An emitter layer (for example, n-GaAs emitter layer 23), an opposite conductivity type compound semiconductor base layer (for example, p ⁺ -GaAs base layer 24), a non-doped compound semiconductor collector layer / channel layer (for example, non-doped GaAs collector layer / channel layer 25), and A step of stacking and forming a one-conductivity type compound semiconductor carrier supply layer (for example, n ⁺ -AlGaAs carrier supply layer 26), and then removing the one-conductivity type compound semiconductor carrier supply layer other than the high electron mobility transistor region. Non-doped at least in the bipolar transistor area A step of thinning so that the compound semiconductor collector layer and the channel layer collector transit time of the carrier is the thickness to be optimized, then the bipolar
A collector electrode (for example, collector electrode 2) is formed on the non-doped compound semiconductor collector layer / channel layer in the transistor region.
7) and simultaneously forming a gate electrode (eg, gate electrode 28) of the same film (eg, WSi film) on the one conductivity type compound semiconductor carrier supply layer, and then forming the non-doped compound semiconductor collector layer / channel layer. Separating into a non-doped compound semiconductor collector layer (eg non-doped GaAs collector layer 25A) in the bipolar transistor region and a non-doped compound semiconductor channel layer (eg non-doped GaAs channel layer 25B) in the high electron mobility transistor region; Then, a base electrode (eg, Cr) is formed on the opposite conductivity type compound semiconductor base layer in the bipolar transistor region.
And then separating the opposite conductivity type compound semiconductor base layer and the one conductivity type compound semiconductor emitter layer into the bipolar transistor region and the high electron mobility transistor region. Exposing a portion of the conductive compound semiconductor emitter cap layer, and then forming an emitter electrode (eg, emitter electrode 30) on the conductive compound semiconductor emitter cap layer of the bipolar transistor region and the conductive layer. Forming a source electrode (for example, the source electrode 31) and a drain electrode (for example, the drain electrode 32) on the type compound semiconductor carrier supply layer by sandwiching the gate electrode and simultaneously forming them all with the same film (for example, AuGe / Au film). It is characterized by being included.

[0023]

By adopting the above means, in the hybrid integrated circuit device of the present invention, the collector layer in the HBT region and the channel layer in the HEMT region can be shared, and therefore, the selective epitaxial growth method is used for the growth of each semiconductor layer. Since it is not necessary to use, it becomes possible to precisely form a fine shape, and therefore high integration is facilitated.

Further, the collector electrode in the HBT region and the HEM
The gate electrodes in the T region are made of the same material at the same time, and HB
Since the emitter electrode in the T region and the source electrode and drain electrode in the HEMT region can be simultaneously formed of the same material, the number of manufacturing steps can be reduced.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 3 to 10 are cross-sectional side views of essential parts showing a hybrid integrated circuit device in a process step for explaining one embodiment of the present invention. Hereinafter, with reference to these drawings, FIG. The details will be described.

See FIG. 3 3- (1) For example, molecular beam epitaxial growth (molecule)
r beam epitaxy (MBE) method to apply the emitter cap layer 22 on the substrate 21,
The emitter layer 23, the base layer 24, the collector / channel layer 25, and the carrier supply layer 26 are grown in this order. The semiconductor crystal epitaxial growth technique applied here is metalorganic chemical vapor deposition.
chemical vapor depositi
It goes without saying that the on: MOCVD) method may be substituted.

The main data regarding the substrate 21 and each of the grown semiconductor layers used here are exemplified as follows. Substrate 21 Material: Semi-insulating GaAs Emitter cap layer 22 Material: n ⁺ -GaAs Impurity concentration: 5 × 10 ¹⁸ [cm ⁻³ ] Thickness: 500 [nm]

Regarding Emitter Layer 23 Material: n-AlGaAs Impurity Concentration: 5 × 10 ¹⁷ [cm ⁻³ ] Thickness: 150 [nm] Regarding Base Layer 24 Material: p ⁺ −GaAs Impurity Concentration: 4 × 10 ¹⁹ [cm ^-3 ] Thickness: 70 [nm]

Regarding collector / channel layer 25 Material: non-doped GaAs Thickness: 800 [nm] Carrier supply layer 26 Material: n ⁺ -AlGaAs Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ] Thickness: 300 [nm ]

Dopant n-type: Si p-type: C In the case of this embodiment, the carrier is an electron, and therefore,
The carrier supply layer 26 is an electron supply layer.

See FIG. 4. 4- (1) By applying a resist process in the lithography technique, a resist film covering the HEMT formation planned region is formed.

4- (2) Wet using an etchant of phosphoric acid type as an etchant
By applying the etching method, the above step 3-
Etching is performed from the surface of the carrier supply layer 26 to reach the inside of the collector / channel layer 25 using the resist film formed in (1) as a mask. Due to this etching, HB
The thickness of the collector layer / channel layer 25 left in the T formation scheduled region is selected so that the carrier transit time of carriers is optimum, and is set to 400 [nm], for example.

4- (3) The above-mentioned step 4-by immersing in a resist stripping solution such as acetone
The resist film formed in (1) is removed.

See FIG. 5 5- (1) By applying the sputtering method, a WSi film having a thickness of, for example, 500 [μm] is formed. 5- (2) Plasma Chemical Vapor Deposition (plasma chemicala)
l vapor deposition (PCVD) method, the thickness is, for example, 500 [nm].
Forming a SiON film.

5- (3) Resist process in lithography technology, and
By applying a dry etching method using CHF ₃ as an etching gas, the SiON film formed in the step 5- (2) is etched to form a collector electrode pattern in the HBT formation planned region. In the HEMT formation planned region, the gate electrode pattern is used. 5- (4) The resist film used as the etching mask when the SiON film is patterned in the step 5- (3) is removed.

5- (5) By applying a dry etching method using a mixed gas of CH ₄ + O ₂ as an etching gas, the above step 5-
The WSi film formed in the step 5- (1) is etched using the patterned SiON film as a mask in (3) to collect the collector electrode 27 in the HBT formation planned region.
And the gate electrode 28 is formed in the HEMT formation planned region. 5- (6) The SiON film used as a mask when forming the collector electrode 27 and the gate electrode 28 is removed.

See FIG. 6 6- (1) By applying a resist process in the lithography technique, a resist film covering the HEMT formation planned region is formed.

6- (2) Reactive ion beam etching using Cl-based gas as etching gas
by using the collector electrode 27 and the resist film formed in the step 6- (1) as a mask by applying the etching method (RIBE) method until a part of the surface of the base layer 24 is exposed. 25 is etched to form a collector layer 25A and a channel layer 25B.

The etching here was carried out under the conditions that the flow rate of the Cl-based gas was 6 [ccm], the ion acceleration voltage was 200 [V], and the microwave power was 100 [W]. 6- (3) The resist film used as a mask when the collector layer / channel layer 25 is etched is removed.

See FIG. 7 7- (1) By applying a resist process in the lithography technique, a resist film having an opening in the base electrode formation planned region in the HBT formation planned region is formed.

7- (2) By applying the vacuum deposition method, the thickness is, for example, 10
A CrAu film of [nm] / 150 [nm] is formed. 7- (3) By applying the lift-off method of dissolving and removing the resist film formed in the step 7- (1), the step 7-
The CrAu film formed in (2) is patterned to form the base electrode 29.

See FIG. 8 8- (1) A resist film covering the HBT formation scheduled region and the HEMT formation scheduled region is formed by applying a resist process in the lithography technique.

8- (2) By applying the RIBE method using Cl gas as an etching gas, one of the exposed base layer 24 is masked with the resist film formed in the step 8- (1). Etching is performed to reach the surface of the emitter cap layer 22 from the surface of the portion.

See FIG. 9 9- (1) By applying a resist process in the lithography technique, a collector electrode formation planned region in the HBT formation planned region and a source electrode in the HEMT formation planned region A resist film having an opening is formed in each of the regions where the drain electrode is to be formed.

9- (2) By applying the vacuum deposition method, the thickness is, for example, 20.
An AuGe / Au film of [nm] / 330 [nm] is formed.

9- (3) By applying the lift-off method of dissolving and removing the resist film formed in 9- (1) above, the step 9-
The AuGe / Au film formed in (2) is patterned to form the collector electrode 30, the source electrode 31, and the drain electrode 32. With this, HB is formed in the HBT formation planned area.
T is completed, and HEMT is completed in the HEMT formation planned region.

See FIG. 10 10- (1) By applying a resist process in the lithography technique, a resist film having an opening is formed at a portion between the HBT and HEMT where an element isolation region is to be formed.

10- (2) The dose amount is set to 2 × 1 by applying the ion implantation method.
0 ¹³ [cm ⁻² ], the ion acceleration energy is 150 [eV], and O ions are implanted to reach the inside of the substrate 21 from the surface of the emitter cap layer 22.
To form.

In the hybrid integrated circuit device completed as described above, the base layer 2 which is indispensable for the HBT.
4, the emitter layer 23, and the emitter cap layer 22 are also present in the HEMT, but this does not affect the operation of the HEMT as described with reference to FIG.

Although the collector layer 25A is made of non-doped GaAs, which is a material common to the channel layer 25B in the HEMT region, as described with reference to FIG. 2, even if it is non-doped, it traverses the base layer 24. The carriers can flow into the collector electrode 27 without any problem.

Furthermore, the collector electrode 27 is in Schottky contact with the collector layer 25A, but the operation of the HBT is that current flows in the direction of being drawn by the collector electrode 27, as in a normal bipolar transistor. There is no problem because the Schottky barrier has no rectifying property.

The present invention is not limited to the embodiment described above, and many other modifications can be realized. For example, a normal bipolar transistor may be formed by replacing the material of the emitter layer 23 in the HBT region with n-AlGaAs instead of n-GaAs.

Further, between the electrode and the semiconductor layer, for example, an electrode contact layer, a spike prevention layer, a buffer layer, etc. may be appropriately interposed in addition to the structure shown in the drawings.

[0054]

In the hybrid integrated circuit device and the manufacturing method thereof according to the present invention, one conductivity type compound semiconductor emitter / cap layer is laminated on a semi-insulating compound semiconductor substrate to form one conductivity type compound semiconductor emitter. .A one conductivity type compound semiconductor emitter layer and an opposite conductivity type compound semiconductor base layer are sequentially stacked in the bipolar transistor area and the high electron mobility transistor area on the cap layer, and an opposite conductivity type compound semiconductor base layer is formed in the bipolar transistor area. A non-doped compound semiconductor collector layer is formed on the upper layer, and a non-doped compound semiconductor channel layer, which is the same layer as the non-doped compound semiconductor collector layer, is formed on the opposite conductivity type compound semiconductor base layer in the high electron mobility transistor region. One conductivity type compound semiconductor carrier on the channel layer Supply layers are laminated to form a collector electrode on the non-doped compound semiconductor collector layer and a gate electrode on the one-conductivity type compound semiconductor carrier supply layer in the same film. A base electrode is formed on the type compound semiconductor base layer, and an emitter electrode is placed on the one conductivity type compound semiconductor emitter cap layer and a gate electrode is placed on the one conductivity type compound semiconductor carrier supply layer. Then, the source electrode and the drain electrode are formed of the same film.

By adopting the above structure, in the hybrid integrated circuit device of the present invention, the collector layer of the HBT region and the HEMT are formed.
Since it can be shared with the channel layer of the region, and therefore it is not necessary to use the selective epitaxial growth method for growing each semiconductor layer, it is possible to precisely form a fine shape, and therefore, it is easy to achieve high integration. become.

The collector electrode in the HBT region and the HEM
The gate electrodes in the T region are made of the same material at the same time, and HB
Since the emitter electrode in the T region and the source electrode and drain electrode in the HEMT region can be simultaneously formed of the same material, the number of manufacturing steps can be reduced.

[Brief description of drawings]

FIG. 1 is a cutaway side view of a main part of a hybrid integrated circuit device for explaining the principle of the present invention.

FIG. 2 is an energy band diagram showing the vicinity of a collector layer when n-type, non-doped (i-type) and p-type materials are used.

FIG. 3 is a cutaway side view of a main part showing a hybrid integrated circuit device in a process main part for explaining an embodiment of the present invention.

FIG. 4 is a side sectional view showing a main part of a hybrid integrated circuit device in a process main part for explaining one embodiment of the present invention.

FIG. 5 is a cutaway side view of a main part showing a hybrid integrated circuit device in a process main part for explaining one embodiment of the present invention.

FIG. 6 is a fragmentary side view showing a main part of a hybrid integrated circuit device in a process main part for explaining an embodiment of the present invention.

FIG. 7 is a side sectional view showing a main part of a hybrid integrated circuit device in a process main part for explaining an embodiment of the present invention.

FIG. 8 is a cutaway side view of a main part showing a hybrid integrated circuit device in a process main part for explaining one embodiment of the present invention.

FIG. 9 is a side sectional view showing a main part of a hybrid integrated circuit device in a process main part for explaining an embodiment of the present invention.

FIG. 10 is a side sectional view showing a main part of a hybrid integrated circuit device in a process main part for explaining an embodiment of the present invention.

FIG. 11: HBT and HEMT for explaining conventional technology
FIG. 4 is a cutaway side view of an essential part showing the hybrid integrated circuit device of FIG.

[Explanation of symbols]

 21 substrate 22 emitter cap layer 23 emitter layer 24 base layer 25A collector layer 25B channel layer 26 carrier supply layer 27 collector electrode 28 gate electrode 29 base electrode 30 emitter electrode 31 source electrode 32 drain electrode 33 element isolation region

Claims (2)

[Claims] 1. A one conductivity type compound semiconductor emitter cap layer laminated on a semi-insulating compound semiconductor substrate, a bipolar transistor region and a high electron mobility transistor on the one conductivity type compound semiconductor emitter cap layer. A one-conductivity-type compound semiconductor emitter layer laminated on the region, and a bipolar layer on the one-conductivity-type compound semiconductor emitter layer.
An opposite conductivity type compound semiconductor base layer laminated on the transistor region and the high electron mobility transistor region; and a non-doped compound semiconductor collector layer laminated on the opposite conductivity type compound semiconductor base layer of the bipolar transistor region, A non-doped compound semiconductor channel layer that is the same layer as the non-doped compound semiconductor collector layer and is laminated on the opposite conductivity type compound semiconductor base layer of the high electron mobility transistor region; and on the non-doped compound semiconductor channel layer. A laminated one-conductivity type compound semiconductor carrier supply layer, a collector electrode formed of the same film on the non-doped compound semiconductor collector layer, and a gate electrode formed on the one-conductivity type compound semiconductor carrier supply layer, The bipolar transistor A base electrode formed on a semiconductor base layer of opposite conductivity type of the region, and an emitter electrode formed on the same conductivity type compound semiconductor emitter cap layer of the bipolar transistor region and the one conductivity type compound A hybrid integrated circuit device comprising: a source electrode and a drain electrode, which are separately formed by sandwiching a gate electrode on a semiconductor carrier supply layer. 2. A one-conductivity type compound semiconductor emitter / cap layer, a one-conductivity type compound semiconductor emitter layer, an opposite-conductivity type compound semiconductor base layer, a non-doped compound semiconductor collector layer / channel layer, and a one-conductivity layer on a semi-insulating compound semiconductor substrate. A step of stacking a type compound semiconductor carrier supply layer, and then removing one conductivity type compound semiconductor carrier supply layer existing in a region other than the high electron mobility transistor region and at least a non-doped compound semiconductor collector layer existing in the bipolar transistor region. Thinning the dual channel layer to a thickness that optimizes the carrier transit time of carriers, and then forming a collector electrode on the non-doped compound semiconductor collector layer / channel layer in the bipolar transistor region and the one conductive layer. Type compound semiconductor on the carrier supply layer Simultaneously forming a gate electrode in the same film, and then separating the non-doped compound semiconductor collector layer / channel layer into a non-doped compound semiconductor collector layer in the bipolar transistor region and a non-doped compound in the high electron mobility transistor region. Forming a compound semiconductor channel layer, then forming a base electrode on the opposite conductivity type compound semiconductor base layer in the bipolar transistor region, and then forming the opposite conductivity type compound semiconductor base layer and one conductivity type Separating a compound semiconductor emitter layer into the bipolar transistor region and the high electron mobility transistor region to expose a part of the one conductivity type compound semiconductor emitter cap layer; and then, the bipolar transistor region. One conductivity type compound semiconductor Forming a source electrode and a drain electrode at the same time by dividing an emitter electrode on the cap / cap layer and a gate electrode on the one-conductivity-type compound semiconductor carrier supply layer so as to form them all at the same time. And a method for manufacturing a hybrid integrated circuit device.