JPH06267200A - Magnetic recording signal processor - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide an optimum data discrimination method for a magnetic head having a non-linear characteristic. [Structure] A zero-cross point detection circuit for an equalized waveform, a PLL that receives the zero-cross timing as an input and generates a clock twice the baud rate, and divides the output of the PLL by two to generate two baud rate clocks with different phases. And a circuit for selecting one clock from the above two clocks using the received waveform and connecting it to the identification and decoding circuit. Further, it has a table capable of variably outputting the branch metric, and adaptively controls the value of the branch metric by using the output of the A / D converter or the internal data of the branch metric table or its output. According to the present invention, magnetic recording information read by a magnetic head having a non-linear characteristic can be reproduced with a low error rate. Therefore, the reliability of the magnetic recording device can be dramatically improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device adaptable to signal reproduction of a magnetic recording device. In particular, it provides an optimum method for reproducing a signal obtained from a magnetoresistive head.

[0002]

2. Description of the Related Art An example of a signal obtained from a signal reading head of a magnetic recording device is shown in FIG. This signal is for the head to detect the magnitude of the change in the magnetic field and output it as a voltage. Normally, at the time of recording, the magnetization is reversed with data 1.
In order to prevent magnetization reversal at data 0, a large change in magnetic field is detected at data 1 at the time of reading. Therefore, the output voltage has a large peak on the positive side or the negative side. In addition, the reversal of the magnetic field is performed from the N pole to the S pole
Since they are alternately inverted from the pole to the N pole, the peaks on the positive side and the negative side are also alternated. Now, the read signal is distorted due to the frequency characteristics of the electromagnetic conversion system and noise superposition. Further, when the data 1 is continuous, the peak position moves due to intersymbol interference, which causes a peak shift, further increasing the distortion. At the time of signal reproduction, it is necessary to extract a data identification timing clock from such a signal without error and to distinguish between data 1 and data 0.

By the way, a partial response code, which is coded by adding correlation with past data to binary data,
It can be applied to a magnetic recording device. As a conventional example of a method for discriminating data from a partial response code, a method called Viterbi decoding is used to estimate a reception sequence that most matches a coding rule from received data of several bits or tens of bits, instead of discriminating bit by bit. There is a way. At this time, the probability that the reception level to which distortion and noise are added corresponds to a certain logical value is calculated, and this value is called a branch metric. By accumulating this branch metric,
The sequence with the highest probability of being received is selected from the many sequences that may have been received. This branch metric is realized by a logic circuit with fixed noise distribution and signal level.

[0004]

There are two problems in applying the partial response code to the magnetic recording device.

The first problem is a method of extracting the identification timing clock. As shown in FIG. 2, the read waveform is a ternary waveform, and the zero cross point that coincides with the data identification point,
Both zero-cross points with half clock phase shifts occur. For this reason, it is difficult to extract the timing clock that matches only the data identification point with the conventionally used zero-cross detection method. A first object of the present invention is to provide a method for extracting an identification timing from a ternary waveform by a simple method.

The second problem is to correct the non-linearity of the characteristics of the magnetic head. As shown in FIG. 2, the output voltage obtained with respect to the change in the magnetic field is asymmetric on the positive side (+1) and the negative side (-1). Moreover, this distortion varies greatly from head to head. Therefore, the conventional Viterbi decoder based on the fixed branch metric calculation cannot handle this. A second object of the present invention is to provide a Viterbi decoding method applied to a signal having a non-linear distortion with large variations.

[0007]

In order to achieve the above-mentioned first object, a zero-cross point detection circuit for an equalized waveform, and a PLL for inputting the zero-cross timing and generating a clock twice the baud rate, A frequency divider that divides the output of the PLL by 2 to generate two baud rate clocks with different phases, and 1 using the received waveform from the two clocks.
A circuit is provided for selecting one clock and connecting it to the identification and decoding circuit. The details of this structure are described in Japanese Patent Application No. 1-14101.
6 and 2-658.

In order to achieve the above-mentioned second object, the branch metric generation circuit constituting the Viterbi decoder is replaced with a circuit capable of varying the value of the branch metric output by external control. Further, a control unit for estimating signal distortion from the received signal and optimally rewriting the branch metric value is provided.

[0009]

In the first means, the PLL first extracts a clock having twice the baud rate synchronized with all zero-cross points and divides the clock to generate two baud rate clocks having different phases. One of the two clocks is a correct clock that is in phase with the identification point, and the other is a clock that is 180 degrees out of phase. There are a plurality of methods for selecting a clock that matches the identification point using the received signal, and the details are described in the above-mentioned known document.

In the second means, the control unit measures the reception frequency of the level of the reception signal, regards the three levels with the highest reception frequency as +1, 0, -1, and determines the maximum branch metric value. assign. If measurement is performed for a long time, the frequency of each level can be directly regarded as the noise distribution. Based on this information, the branch metric is set to be large for a high frequency level and small for a low frequency level, and the branch metric value is controlled periodically or at the time of initial startup.

Here, the control unit comprises a reception level measuring unit, a reference table, and a comparing circuit for both.

The received signal is converted into a word having a length of several bits by an analog-digital converter (hereinafter abbreviated as A / D). A counter is provided for each word, and the counter is incremented each time a word, that is, a reception level is detected. In this way, the reception level frequency can be measured. On the other hand, the reference table has a function of associating the level frequency with the branch metric. The reference table contains initial values such as no non-linear distortion and noise of 2
The detection frequency of each word in the case of power distribution is recorded, and by comparing this value with the corresponding counter value,
Determine the branch metric value to be rewritten.

[0013]

EXAMPLE FIG. 9 shows an example of system configuration in an example of the present invention. In this configuration example, a magnetic recording medium 101, a magnetic reading head 102, an equalizer 1, and a timing extraction unit 10 are provided.
3, a discriminator 104, and a decoding unit 105. The signal recorded on the magnetic recording medium 101 is converted into an electric signal by the magnetic reading head 102, the waveform distortion is corrected by the equalizer 1, and the identification clock is extracted by the timing extraction unit 103 from the equalized signal, The discriminator 104 discriminates data from the equalized waveform using the discrimination clock, and the decoding unit 10
Binary data is obtained from the data encoded and recorded in 5. Furthermore, the timing extraction unit 103
Zero-cross detector 106, PLL 107, frequency divider 10
8 and a selection unit 109. The PLL 107 receives the zero-cross detector 106 as an input, and outputs a clock that is twice the baud rate synchronized with all zero-cross points. The clock is divided by the frequency divider 108 to generate two baud rate clocks having different phases. One of the two clocks is a correct clock that is in phase with the identification point, and the other is a clock that is 180 degrees out of phase. The selection unit 109 uses the received signal to select a clock that matches the identification point. There are several possible selection methods, and the details are described in the above-mentioned publicly known documents.

An embodiment of the decoding unit 105 will be described below in detail. FIG. 1 shows a first embodiment of the decoding unit 105. This embodiment comprises an equalizer 1, an A / D 2, a branch metric control unit 3, a Viterbi decoder 4, and a timing extraction unit 103. Here, the A / D 2 is the discriminator 1 in FIG.
04, the branch metric control unit 3 and the Viterbi decoder 4 correspond to the decoding unit 105, respectively. In addition, the Viterbi decoder 4 includes a branch metric table 5, an add
It comprises a compare / select circuit 6 (hereinafter abbreviated as ACS) and a path memory 7. The received signal is converted into a digital word having a length of several bits by the A / D 2 after the linear intersymbol interference is removed by the equalizer 1. The branch metric control unit 3 measures the reception frequency of the level of the reception signal, and the three levels with the highest reception frequency are +1, 0, -1.
And assign the maximum branch metric value. If the measurement is performed for a long time, the frequency of each level can be regarded as it is as a noise distribution. On the basis of this information, the branch metric is set to be large for a high frequency level and small for a low frequency level, and the value of the branch metric table 5 is rewritten periodically or at the time of initial startup. This branch metric is integrated in the ACS 6, and the series having the highest probability of being received is selected from the path memory 7 from the plurality of series that may have been received.

FIG. 3 shows an embodiment of the branch metric control in the embodiment of FIG. The branch metric control unit 3 includes a reception level distribution measuring unit 11, a normal distribution table 12, and comparators 13.1-13. The reception level distribution measuring unit 11 includes a decoder 14 and counters 15.1-15.n. n. Further, the normal distribution table 12 is a frequency table 16.1-16. n. On the other hand, the branch metric table includes the decoder 14 and the branch metric storage circuit 17.1-1.
7. n, selector 18.

The received signal converted into a digital word of several bits length by the A / D 2 is input to the decoder 14 in the branch metric control unit 3, and the corresponding word, that is, the corresponding reception level counter 15 is incremented. In this way, the reception level frequency can be measured.
On the other hand, the reference table 12 has a function of associating the level frequency with the branch metric. Frequency table 16.1
-16. The initial value of n is, for example, non-linear distortion, and noise is 2
The detection frequency of each word in the case of the power distribution is recorded, and the counters 15.1-15.
n values are compared to determine the optimum branch metric value, and the branch metric storage table 17.1-17.
Rewrite the value of n. These storage tables can be configured by RAM, or can be realized by a method of switching some tables formed by random logic.

On the other hand, the received signal is input to the same decoder 14 as the decoder 14 in the branch metric control unit 3, and the corresponding word, that is, the output of the branch metric storage table 17 of the corresponding received level is output through the selector 18. . By this operation, maximum likelihood decoding is possible by reflecting the non-linearity of +1, 0, −1 levels shown in FIG. 2 and the deviation of the noise distribution depending on the level from the normal distribution.

FIG. 4 shows another embodiment of the branch metric control in the embodiment of FIG. The branch metric control unit 3 includes a reception level distribution measuring unit 11, a reference distribution table 20, and comparators 13.1-13. n,
The reception level distribution measuring unit 11 includes a decoder 14 and counters 15.1-15. n. Further, the reference distribution table 20 is a variable frequency table 20.1-20. n
Composed of. On the other hand, the branch metric table includes the decoder 14 and the branch metric storage circuit 1.
7.1-17. n, selector 18.

The difference from the embodiment shown in FIG. 3 is that the contents of the reference table 20 are not fixed values, but the values are updated according to the output of the reception level frequency measuring section 11. the first,
Variable frequency table 21.1-21. The detection frequency of each word when noise is square-distributed is recorded in n, and the counters 15.1-15.
The value of n is compared by the comparator 13.1-n to determine the optimum value of the branch metric, and then the branch metric storage table 17.1-17.n. The value of the variable frequency table is rewritten together with the value of n.

On the other hand, the received signal is input to the same decoder 14 as the decoder 14 in the branch metric control unit 3, and the corresponding word, that is, the output of the branch metric storage table 17 of the corresponding received level is output through the selector 18. . The operation of this portion is exactly the same as that of the embodiment shown in FIG. If an attempt is made to increase the accuracy of control by lengthening the level frequency measurement time, a large-capacity counter 15 is required and the hardware amount of the circuit is increased. By finely adjusting the contents of the frequency table 21 using the output, highly accurate control is possible even with a relatively small table capacity.

FIG. 5 shows a third embodiment of the branch metric control in the embodiment of FIG. The branch metric control unit 3 includes a reception level distribution measuring unit 11, a reference distribution table 20, and comparators 13.1-13. n, and the reception level distribution measuring unit 11 includes a switch decoder 2
2 and counter 15.1-15. n. Further, the reference distribution table 20 is the variable frequency table 20.
1-20. n. On the other hand, the branch metric table includes the switch decoder 22, the branch metric storage circuits 17.1-17. n, selector 18.

The difference from the embodiment shown in FIG. 4 is that the branch metric storage table 17.1-17. The content of n is a fixed value, and the variable function is the branch metric memory circuit 1.
7.1-17. It is realized by changing the correspondence between n and the digital word indicating the received amplitude. The received signal converted into a digital word of several bits length by the A / D 2 is input to the switch decoder 20 in the branch metric control unit 3, and the corresponding word, that is, the corresponding reception level counter 15 is incremented. In this way, the reception level frequency can be measured.
Then, the variable frequency tables 21.1-21. In n, the detection frequency of each word when noise is squared is recorded. The counter 15.1 corresponding to this value is recorded.
15. The value of n is compared by the comparator 13.1-n to determine the optimum value of the branch metric, and then the branch metric storage table 17.1-17.n. The value of the variable frequency table is rewritten together with the value of n. On the other hand, on the other hand, the received signal is input to the same switch decoder 20 as the switch decoder 20 in the branch metric control unit 3, and the corresponding word, that is, the output of the branch metric storage table 17 of the corresponding received level is the selector 1.
It is output through 8. In the present embodiment, the content itself of the branch metric storage circuit 17 is not rewritten, but only the correspondence between the reception amplitude and the metric is changed by switching.

FIG. 6 shows a second embodiment of the decoding unit 105. In this embodiment, the equalizer 1, the A / D 2, the correction circuit 40,
The branch metric control unit 3 and the Viterbi decoder 4 timing extraction unit 103 are included. Also, the Viterbi decoder 4
Is composed of a branch metric table 5, an ACS 6, and a path memory 7. The difference from the embodiment shown in FIG. 1 is that branch metric control is performed in a feedback loop using the output of the branch metric table 5. The branch metric control unit 3 uses the output of the branch metric table 5 to detect a non-linear error corresponding to each level of +1, 0, and -1, and the correction circuit 40 performs this correction. By using the feedback type, it is possible to perform correction with a small error with a small control amount.

FIG. 7 shows an embodiment of the branch metric control unit 3 and the correction circuit 40 in the embodiment of FIG. The correction circuit 31 includes an adder 41, a selector 42, and a determiner 43. The control unit 30 uses the minimum value detection circuit 4
4, a mask circuit 45, an averaging circuit 46, a square root output circuit 47, and a multiplier 48.

From the branch metric table 5, the square of the error between the reception level and +1, 0, -1 is output as a branch metric. Maximum value detection circuit 4
4 compares the three error values and regards the smallest one as an equalization error and opens the corresponding gate circuit 45. Thus, only the +1 squared equalization error is input to the averaging circuit 46a and only the −1 squared equalization error is input to the averaging circuit 46b, so that the mean squared error is obtained by integration. In addition, the square root calculation circuit 47 outputs 2 corresponding to +1, 0, −1.
A zero-level correction value can be obtained by calculating the square root for all the power errors and then averaging them. By multiplying this correction value by a square error of +/- 1 in the multiplier 48, a correction value of +/- 1 can also be obtained. The selector 42 follows the rough judgment of the judging device 43 to obtain +1, 0, −.
Any one of the correction values 1 is selected, and the adder 41 subtracts the correction value to correct the nonlinear error.

FIG. 8 shows a third embodiment of the decoding unit 105. This embodiment includes an equalizer 1, an A / D 2, a control unit 30, a Viterbi decoder 4, and a timing extraction unit 103. The Viterbi decoder 4 is composed of a branch metric table 5, ACS 6, and path memory 7. The difference from the embodiment shown in FIG. 1 is that the control unit 3 reads or writes the intermediate calculation result in the branch metric table, whereby the feed-forward type control and the feedback type control already described are possible. Therefore, the control unit 30 is suitable for being realized by a microcomputer. At that time, since the input / output speed of the microcomputer is not necessarily high, the branch metric table 5 is equipped with a high-speed RAM so that the data read from the disk medium is temporarily stored in the RAM.
It is necessary to transfer it to the control unit 30 with a low-speed clock after storing it in the memory. Branch metric table 5 at the same time
Is a provisional metric until the control of the control unit 30 is started.
Output to CS6. All calculations required for the non-linearity correction may be performed in the microcomputer, or may be performed using a computer connected to an external interface together. This method is especially useful when the level reception frequency is measured and the optimum metric value is calculated at the time of adjustment before shipment or when the power supply of the device is turned on, and when the normal operation is limited to the minute adaptive operation or the switching operation of multiple prepared metrics. It is valid.

[0027]

According to the present invention, the magnetic recording information read by the magnetic head having the nonlinear characteristic can be reproduced with a low error rate. Therefore, the reliability of the magnetic recording device can be dramatically improved.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a diagram showing characteristics of a magnetic head and a signal amplitude distribution.

FIG. 3 is an example of branch metric control in the first example.

FIG. 4 is a second example of the branch metric control in the first example.

FIG. 5 is a third example of the branch metric control according to the first example.

FIG. 6 is a second embodiment.

FIG. 7 is an example of control according to the second embodiment.

FIG. 8 is a third embodiment of the present invention.

FIG. 9 is a system configuration example to which the present invention is applied.

[Explanation of symbols]

1 ... Equalizer, 2 ... AD converter, 3 ... Branch metric control part, 4 ... Viterbi decoder, 5 ... Branch metric table, 6 ... ACS, 7 ... Path memory, 11 ...
Reception level frequency measuring unit, 12 ... Normal distribution table, 13
... comparator, 14 ... decoder, 15 ... counter, 16
... frequency table, 17 ... branch metric storage circuit,
18 ... Selector, 19 ... Timer, 20 ... Reference table, 21 ... Variable frequency table, 22 ... Switch decoder, 30 ... Control section, 31 ... Correction circuit, 41 ... Adder, 4
2 ... Selector, 43 ... Judgment device, 44 ... Minimum value detection circuit, 45 ... Mask circuit, 46 ... Averaging circuit, 47 ... Square root output circuit, 48 ... Multiplier, 101 ... Magnetic recording medium, 1
02 ... magnetic head, 103 ... timing extraction unit, 104
Identification circuit, 105 decoding unit, 106 zero cross detection unit, 107 PLL, 108 frequency divider, 109 selection unit.

Claims (4)

[Claims] 1. A magnetic recording medium, a magnetic head for reading a signal from the medium, an equalizer for processing the read signal, a detection circuit for a zero cross point of an equalized waveform, and the zero cross timing as an input. A PLL that generates a clock with twice the baud rate, a frequency divider that divides the output of the PLL by two to generate baud rate clocks with two different phases, and one clock using the received waveform from the two clocks. A magnetic recording signal processing apparatus comprising a circuit for selecting and connecting to an identification and decoding circuit and a circuit for identifying digital data from an equalized waveform, wherein the selected clock is used as an identification clock of the identification circuit. . 2. A magnetic recording medium, a magnetic head for reading a signal from the medium, an equalizer for processing the read signal, and a signal processing device equipped with Viterbi decoding, which are controlled by an external control circuit. A magnetic recording signal processing device comprising a branch metric calculation circuit with variable output, wherein the control circuit determines a control amount according to an input signal of the branch metric calculation circuit. 3. The magnetic recording signal processing device according to claim 2, wherein the control circuit determines the control amount by using the output of the branch metric calculation circuit. 4. A signal processing apparatus according to claim 2, wherein said control circuit determines a control amount by using internal data of a branch metric calculation circuit.