JPH06232930A - Clock recovery circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Detect demodulation timing points in a short time,
An object of the present invention is to provide a clock recovery device of a digital demodulation device capable of obtaining a good demodulation signal. In a clock reproducing device of a digital demodulating device for detecting a modulated wave by a predetermined detecting means, a signal in the demodulating process is sampled at a plurality of preset extraction points for each unit data period (symbol period). , Correlation detection means for detecting the correlation between two adjacent extraction points, and correlation determination means for comparing the magnitudes of the correlations detected by the correlation detection means to determine the maximum extraction point pair. The timing clock signal is generated at the extraction point exhibiting the maximum correlation based on the judgment of the correlation judging means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for demodulating a modulated wave modulated by a digital signal, and in particular, for clock recovery in a digital demodulator for asynchronously demodulating an angle modulated wave modulated by differential encoding. Regarding the circuit.

[0002]

2. Description of the Related Art As a modulation / demodulation system for digital signals,
Amplitude modulation methods that change the amplitude of a carrier wave according to the state value of a digital signal and so-called angle modulation methods that change the phase or frequency are well known.In the field of digital mobile communication, the effect of amplitude distortion in the transmission line is known. It is common to use an angle modulation method that is less susceptible to noise.

First, the angle modulation will be briefly described by taking as an example a π / 4 shift four-phase phase modulation (π / 4 shift QPSK) system excellent in distortion resistance and suitable for mobile communication. FIG. 6 is a block diagram showing the basic configuration of a π / 4 shift QPSK modulator. The serial / parallel converter 1 converts the input digital binary data string into unit data (X, Y) having a set of 2 bits. This unit data is generally referred to as one symbol, and the process proceeds with this as one cycle. The differential encoding circuit 2 receives (X,
The baseband signal composed of the I channel and the Q channel carrying the information of Y) is generated, and the baseband signal is band-limited by the low pass filters (LPF) 3 and 4. Thus, the in-phase and quadrature components of the carrier wave ω _C are respectively amplitude-modulated by multiplying the band-limited baseband signal, and then both are combined to obtain a modulated wave.

In the π / 4 shift QPSK system, the amplitudes “A” and “-A” are assigned according to the binary signals “1” and “0”, and four signal point data (I, Q) is given and the phase modulation is performed based on this, and it is based on a four-phase phase modulation (QPSK) system. That is, as shown in FIG. 7A showing the signal point arrangement of I and Q, the signal point arrangement of QPSK indicated by a black dot in the figure for each symbol and the signal point indicated by a white dot in the figure obtained by π / 4 shifting the signal point arrangement. This is a method of performing phase modulation by alternately using arrangement and. Therefore, the phase difference ΔΦ with the preceding symbol is always an odd multiple of π / 4, and the relationship with the input unit data (X, Y) is shown in FIG.
It can be expressed by (b).

The angle modulation has been briefly described above.
As a method of demodulating a modulated wave, a synchronous detection method and a differential detection method are well known. Theoretically, the synchronous detection method has better characteristics, but it is rather disadvantageous under the condition that high-speed fading is likely to occur, and especially in the digital mobile communication where rapid phase fluctuation is likely to occur A differential detection method that exhibits better characteristics than the method is suitable. Since the differential detection is to detect the next modulated wave with reference to the modulated wave delayed by the delay circuit having a predetermined delay time, the modulated wave modulated with the differentially encoded signal as described above. It is necessary to be. Further, since carrier wave reproduction is not required and the configuration is simpler than that of synchronous detection, it is suitable for mobile communication.

For example, in the case of the above-mentioned π / 4 shift QPSK, the phase difference ΔΦ between the two is found by detecting the next modulated wave with reference to the phase of the modulated wave preceding by one symbol, and this is shown in FIG. ). FIG. 8 is a block diagram showing an example of a conventional digital demodulation device for demodulating a π / 4 shift QPSK modulated wave by using differential detection. The phase-modulated wave becomes a baseband signal of the I channel and the Q channel, respectively, by a signal having a frequency equal to that of the carrier wave ω _C and a signal obtained by shifting it by π / 2. This I
The signal and the Q signal are digitized by analog / digital converters (A / D) 7 and 8 via low-pass filters 5 and 6, respectively. The differential detection circuit 9 detects the signal point arrangement difference between the digitized signals I and Q and the signal preceding by one symbol, that is, the phase difference ΔΦ, and detects X based on the relationship shown in FIG. 7B. Decrypt to Y. Delay detection circuit 9
The detection signal from is output to the data identification units 11 and 12 and the clock recovery circuit 13. Clock recovery circuit 13
Determines a timing point, which will be described later, and supplies a timing clock signal to the data identifying units 11 and 12 for each symbol period based on the timing point. Data identification section 11, 12
Determines basic data (X, Y) from the detection signal based on the timing clock signal, and the basic data (X, Y)
Is demodulated by the parallel / serial converter 14 into a binary data string signal before modulation. FIG. 9 shows an eye pattern obtained by overwriting the detection signal from the X-side output end of the differential detection circuit 9 a plurality of times, and shows the most open eye of the binary signal (X =) 1 or 0. It is common to identify the signal level at the point (timing point) 10 as the demodulated data of each symbol.

An extremely important point in the above demodulation processing is how to determine the timing point,
A conventional clock recovery circuit determines the timing point and generates a timing clock signal, but a zero-cross detection method is generally used as a method for obtaining the timing point, and a detection signal is output from one output end of the delay detection circuit 9. Is taken out, and the point where it crosses zero (a predetermined level located almost in the middle of the binary level), that is, 1 in FIG.
The zero cross point indicated by 5 is detected, the position 10 shifted by 1/2 symbol period from the zero cross point 15 is obtained, and this is output to the data identifying units 11 and 12 as a timing point signal.

However, as is clear from the shape of the eye pattern of FIG. 9, the clock recovery circuit for detecting the timing point using the zero cross point as described above actually has a point where the data crosses zero in the figure. Since it is distributed over a wide range as shown by the arrow Δt, it was difficult to find an accurate zero cross point. That is, if the timing point is simply a position shifted by 1/2 symbol cycle from the zero-cross point, the most open point of the eye deviates from the desired position, and the rate of bit error occurrence becomes large. Although many zero-cross points were read and the median value was calculated and this was made into the true zero-cross point, there was a defect that it took time to determine this. In particular, in a system that requires frequent switching of communication channels and setting of the timing point each time, such as a digitized system for wireless communication which is to be implemented in recent years, this is an extremely serious drawback.

On the other hand, in Japanese Patent Laid-Open No. 3-205940 proposed with digital radio in mind, I, which is a baseband signal obtained by quasi-coherent detection of a preceding modulated wave,
Where each of the Q signal points is located on the I and Q coordinate axes, and if the signal points deviate from the predetermined signal point arrangement, the original position is predicted and corrected.
A method of performing synchronization correction by changing the delay time of the detection circuit and shifting the phase has been proposed. For example, if the detected signal point is located at the position indicated by x in FIG. 10, the x point is located at the P point closest to the x point in the predetermined signal point arrangement indicated by black dots in the figure. And the amount of phase shift is determined. However, if the initial timing point shift is significant in this method,
There is a possibility that incorrect correction will be repeated each time one symbol is detected, and it takes a long time to complete the synchronization pull-in.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the defect of the clock recovery circuit of the conventional digital demodulation apparatus as described above, and detects a demodulation timing point in an extremely short time to obtain a good demodulation signal. It is an object of the present invention to provide a clock recovery device for a digital demodulation device capable of obtaining the above.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention provides a clock regenerating device of a digital demodulating device for detecting a modulated wave by a predetermined detecting means, wherein a signal in a demodulating process is unit data period (symbol period). The maximum value is obtained by comparing the magnitude of the correlation detected by the correlation detection means with the correlation detection means for detecting the correlation between two adjacent extraction points by sampling at a plurality of preset extraction points. Correlation determining means for determining a pair of extraction points is provided, and the correlation determining means generates a timing clock signal at the extraction point exhibiting the maximum correlation based on the determination.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. As is clear from the eye pattern shown in FIG. 9, at the timing point 10 where the eye is most opened, the level of the detection signal becomes a or -a (X = 1 or 0) where the concentration is relatively high. In the vicinity, the level is almost the same as the timing point 10 in most cases. On the contrary, as the distance from the timing point 10 approaches and the zero cross point 15 approaches, the probability that the levels do not match increases. That is, when a plurality of extraction points are set for the detection signal for one symbol period, the signal levels at the extraction points are sampled, and the signal levels of two adjacent extraction points are correlated with each other, The correlation becomes large in the vicinity of the coincident timing point, and becomes small when the signal levels of the two extraction points are different. In other words, the correlation of the sampling value at the point 10 in FIG. 9 becomes large, but it becomes small at the point 15 in FIG.

The present invention focuses on this point, detects a correlation, and compares the magnitudes of these to detect a timing point. Specifically, as shown in FIG. 11, the signal level is sampled at predetermined extraction points (8 points per symbol in the figure) for each symbol period, and sampling data of adjacent extraction points is sampled. comrades, after detecting the sequential correlation mutual P ₁ and P _2, P ₂ and P ₃ · · ·, at the extraction point pair (the diagram the correlation is the maximum by comparing the magnitudes of the correlation data P
The pair of ₄ and P ₅ or the pair of P ₅ and P ₆ is obtained), and one of the pair of extraction points is set as a timing point.

FIG. 1 is a block diagram showing the configuration when an embodiment of the clock recovery circuit according to the present invention is applied to a digital demodulator. The clock recovery circuit 16 includes a correlation detection circuit 17 and a correlation determination circuit 18. Consists of. The correlation detection circuit 17 samples the levels of the detection signals X and Y output from the differential detection circuit 9 at a plurality of preset extraction points for each symbol period, and at the same time, samples the two adjacent signals. Correlation determination circuit 1 detects the correlation between signals sampled with one set of extraction points, adds the detected correlations for each set of corresponding extraction points for each of X and Y, and accumulates each for the number of reciprocal symbols.
8 is output. FIG. 2 is a block diagram showing a specific configuration example of the correlation detection circuit 17. In the figure,
The delay circuits 19 and 20 both have a delay time τ corresponding to the interval of the extraction points, and are directly connected to one input terminal of the XOR (exclusive OR) gates 21 and 22 and to the other input terminals thereof. The detection signals X and Y are transmitted via the delay circuits 19 and 20.
By inputting, the correlation with the immediately preceding extraction point is detected. Then, both correlation data are added and output to a plurality of counters 24 via a multiplexer 23 which distributes the data at a period τ, and the counter 24 accumulates a predetermined plurality of symbols of correlation data.

The correlation decision circuit 18 compares the magnitudes of the correlation data accumulated in the counter 24 to detect the set of extraction points having the largest correlation, decides one of the extraction points as a timing point, and determines the timing. A timing clock signal is generated based on the points.
As is well known, since the XOR gate has the input / output characteristics shown in FIG. 3, when the correlation is large (when the input levels match), “0” is small (when the input levels do not match). Outputs "1". Therefore, the closer the numerical value stored in the counter is to 0, the greater the correlation. Therefore, the correlation determination circuit 18 in the next stage may be configured to obtain the minimum value from a plurality of inputs. On the other hand, the detection signals X and Y output from the differential detection circuit 9 are input to the data identification units 11 and 12, and the data identification units 11 and 12 are input.
Decodes the detection signals X and Y based on the timing clock signal generated by the correlation determination circuit 18. The decoded signal is demodulated by the parallel / serial converter 14 into a data string.

As described above, by configuring the clock recovery circuit 16, the correlation distribution is detected for each symbol,
Based on this, the timing point can be determined. That is, in the past, the timing point was predicted based on an unstable point such as a zero cross point, whereas the present invention directly determines the timing point at which the eye of the eye pattern, which is a relatively stable point, is the most open. This is a requirement, and is strong against a rapid phase shift due to fading or the like, and it is also possible to determine a timing point in a short time for a large phase shift.

FIG. 4 is a block diagram showing the configuration of the second embodiment in which the function of the data discriminating section is included in the clock recovery circuit according to the present invention. The phase modulated wave converted into the intermediate frequency (IF) is shown in FIG. The present invention is applied to a digital demodulation device that demodulates. The phase modulation wave has its amplitude value adjusted by passing through the limiter circuit 25, and is phase quantized by the phase quantization circuit 26. The phase quantized signal is delayed by a delay circuit 27 having a delay time of 1 symbol period to obtain a difference from the signal preceding by 1 symbol to obtain a phase difference ΔΦ.
Is obtained as a quantized signal.

For example, the IF frequency is 450 kHz, the symbol period (frequency) is 21 kHz, and a pulse signal of 12.6 MHz from the clock 28 to the phase quantization circuit 26, which is divided by 1/75 by the frequency divider 29. Went around 168k
When a Hz pulse signal is input, the phase-modulated wave is divided into eight elements per symbol by the pulse signal from the frequency divider 29, and each element is clocked according to the phase.
Is quantized by the pulse signal from. Based on the frequency ratio between the IF and the pulse signal of the clock 28, each element is output in a form in which the phase is expressed by 0 to 27 pulse signals and the phase difference ΔΦ is quantized by 0 to 27 pulse signals.
The relationship between the phase difference ΔΦ and the number of pulses can be expressed by dividing the coordinates into 28 as shown in FIG. The decoding circuit 30 calculates the phase difference ΔΦ from the number of pulses of each input element according to the quadrant on the coordinate of FIG. 5A.
It is determined based on (b) and is decoded into digital signals X and Y according to FIG. 7 (b). Since each of the digital signals X and Y forms eight data strings per symbol period, they are parallelized by the serial / parallel converters 31 and 32, respectively, and are latched by the latch circuits 33 and 34 at each symbol period. Latched on. With respect to the outputs of the latch circuits 33 and 34, a pair of adjacent bits are input to an XOR gate to detect a correlation, and the output is added for each corresponding set for each of X and Y, and accumulated for a predetermined number of symbols in a counter. To do. The correlation determination circuit 35 that has taken in the data of the counter determines the minimum set, that is, the point at which the correlation is maximum, and generates the timing clock signal. The phase shifter 36 shifts the timing at which the latch circuits 33 and 34 latch data based on the timing clock signal so that the point determined by the correlation determination circuit 35 is output from the fourth bit at the output ends of the latch circuits 33 and 34. As a result, the latch circuit 33, 34 outputs 4
The signals extracted from the bit position are signals X and Y at the timing points, respectively, and these may be demodulated by the parallel / serial converter 14 into a data string. Here, 37 in FIG. 4 is a frequency divider for supplying one symbol period which is a latch timing, and a frequency divider 38 is for further dividing this frequency and supplying the number of count symbols of the counter.

As described above, since the clock recovery circuit of the present invention performs a predetermined sampling on the decoded digital signal and takes the correlation between adjacent data, it is possible to obtain the timing point in a short time. It is extremely effective when Further, since the clock recovery circuit of the present invention directly captures the point where the eye of the eye pattern is most opened, it is less susceptible to noise near the zero cross, and the timing point is updated every time one symbol of the modulated wave is demodulated. Follows the phase shift due to fading at high speed.

Although the present invention has been described above by taking an apparatus for demodulating a modulated wave obtained by phase-modulating a digital signal by using differential detection, the present invention is not limited to this, and a digital signal is modulated and demodulated. It will be apparent that any system may be used as long as it is a demodulator used in the system, and it can be applied to a demodulator of a frequency modulation system or an amplitude modulation system, for example. In the demodulator, any method can be applied to the process from the modulated wave to the decoding. For example, the present invention may be applied to complement the phase shift between the preceding preamble signal and the next arriving preamble signal in the demodulator of the synchronous detection system. Further, in the embodiment, the XOR gate is used as a means for detecting the correlation, but other means such as an NXOR gate may be used as long as it distinguishes the case where the two input values are matched and the case where they are not matched. It may be configured by a circuit. Furthermore, in the embodiment, the timing point is determined by detecting the correlation between the detected and decoded digital signals (X, Y). For example, in FIG. 1, the signals passing through the LPFs 5 and 6 are delayed. When the configuration is such that A / D conversion is performed after detection, correlation may be detected for signals that have not been digitized and subjected to differential detection. In this case, the magnitude of the result obtained by multiplying the sampling data for each extraction point is different. Since it corresponds to that of the correlation, a multiplier may be used as the correlation detecting means. Therefore, it will be apparent that in the synchronous detection method, the correlation may be detected for the baseband signal (I, Q, ΔΦ) or the signal obtained by digitizing the baseband signal (multilevel digital signal).

[0021]

Since the present invention is configured as described above, it becomes possible to detect the demodulation timing point in a short time, and the timing point is the point at which the eye of the eye pattern is most opened. Will follow
It also has a remarkable effect in limiting the occurrence of bit errors even with respect to phase shift due to noise or fading near zero cross.

[0022]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration when an embodiment of a clock recovery circuit according to the present invention is applied to a digital demodulator.

FIG. 2 is a diagram showing a configuration of a correlation detection circuit.

FIG. 3 is a diagram showing input / output characteristics of an XOR gate.

FIG. 4 is a block diagram showing a configuration when a second embodiment of the clock recovery circuit according to the present invention is applied to a digital demodulation device.

5A and 5B are diagrams for explaining the operation of the phase quantization circuit.

FIG. 6 is a block diagram showing the basic configuration of a π / 4 shift QPSK modulator.

7A and 7B are diagrams illustrating a π / 4 shift QPSK modulation method.

FIG. 8 is a block diagram showing the basic configuration of a conventional demodulation device.

FIG. 9 is an eye pattern diagram of a detection signal.

FIG. 10 is a diagram illustrating a conventional phase shift predicting unit.

FIG. 11 is a diagram illustrating a relationship between an eye pattern of a detection signal and an extraction point.

[Explanation of symbols]

 9 ... Delay detection circuit 10 ... Timing point 11, 12 ... Data identification section 13 ... Clock recovery circuit (conventional) 15 ... Zero cross point 16 ... Clock recovery circuit (present invention) 17 ... Correlation detection circuit 18, 35 ... Correlation determination circuit 21 ... XOR gate 24 ... Counter 36 ... Phase shifter

Claims (4)

[Claims] 1. A clock recovery circuit of a digital demodulating device for detecting a modulated wave by a predetermined detecting means, wherein a signal in a demodulating process is preset at a plurality of extraction points for each unit data cycle (symbol cycle). Correlation detection means for sampling and detecting a correlation between every two adjacent extraction points, and correlation determination means for comparing the magnitude of the correlation detected by the correlation detection means and determining the maximum extraction point pair A clock recovery circuit, wherein the correlation determining means generates a timing clock signal based on the determination. 2. A detection signal obtained by detecting a modulated wave by a predetermined detection means is sampled at a plurality of preset extraction points for each unit data cycle (symbol cycle) to extract a timing clock signal and a predetermined one extraction point. In the clock recovery circuit of the digital demodulation device, which shifts the sampling period so that the points coincide with each other, and uses the data sampled at the one extraction point as a demodulation signal, the correlation of the sampling data for every two adjacent extraction points And a correlation determining means for determining the maximum extraction point pair by comparing the magnitude of the correlation detected by the correlation detecting means, and the maximum correlation based on the determination by the correlation determining means. A clock recovery circuit characterized by generating a timing clock signal at an extraction point exhibiting correlation. 3. A baseband signal is sampled at a plurality of preset extraction points for each unit data period (symbol period), and the sampling period is shifted so that the timing clock signal and one predetermined extraction point coincide with each other. In the clock recovery circuit of the digital demodulator that detects the data sampled at the one extraction point and uses it as a demodulation signal, the correlation detection means for detecting the correlation of the sampling data at every two adjacent extraction points. A correlation determining means for comparing the magnitudes of the correlations detected by the correlation detecting means to determine the maximum extraction point pair, and the extraction point exhibiting the maximum correlation based on the determination of the correlation determining means. A clock recovery circuit characterized by generating a timing clock signal. 4. Correlation accumulating means for accumulating correlation data for a plurality of symbol periods is provided for each output of the correlation detecting means, and the correlation data accumulated by the correlation accumulating means are compared to determine the maximum. 4. The clock recovery circuit according to claim 1, wherein the correlation determining means is configured to detect a pair of extraction points that are