JPH06232169A - Semiconductor device and its manufacture - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce variations in characteristics in the manufacturing process of Schottky gate field effect transistors,
Good control of ET characteristics. A high-concentration impurity region 2 is formed in a surface region of a semi-insulating GaAs substrate 1, and then a recess groove 4 is formed from the surface of the impurity region 2 to reach the region of the substrate 1, and the center of the bottom surface of the recess groove 4 is formed. To form a channel portion 1a by forming a low-concentration impurity region 5 in a recessed portion and intermediate-concentration impurity regions 6a in both end portions and side portions of the bottom surface of the recess groove 4 and forming a gate electrode 8 on the center portion of the bottom surface of the recess groove 4. The source and drain electrodes 9 and 10 are arranged on the high-concentration impurity regions 2 on both sides of the recess groove 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure for improving the gate breakdown voltage and transistor characteristics of a Schottky gate field effect transistor, and for stabilizing characteristic control in the manufacturing process. Method.

[0002]

2. Description of the Related Art An example of a conventional Schottky gate type field effect transistor using GaAs as a semiconductor material will be described below. BACKGROUND ART Conventionally, a Schottky gate type field effect transistor (hereinafter also referred to as MESFET) using GaAs as a semiconductor material has been widely used as an active element constituting an amplifier in a microwave region, and this GaAs MESFET is usually a source resistance. In order to reduce the above, a structure in which a gate electrode is arranged at the bottom of a recessed groove portion (hereinafter referred to as a recess groove) called a recess formed on a GaAs substrate is adopted.

FIG. 4 shows such a conventional recess type MES.
FIG. 4 is a cross-sectional view for explaining the structure and manufacturing method of the FET, in which 200 is the recess type MESFET.
An n-type GaAs layer 15 having a recess groove 15a on its surface is formed on the semi-insulating GaAs substrate 1, and the portion of the n-type GaAs layer 15 below the recess groove 15a is a channel portion. It is 1a. Further, the n-type Ga
The gate electrode 8 is arranged on the center of the bottom surface of the recess groove 15a of the As layer 15, and the n-type G on both sides of the recess groove 15a is arranged.
A source electrode 9 and a drain electrode 10 are formed on the aAs layer 15.
Are arranged.

Reference numeral 16 is a Schottky metal layer for forming the gate electrode 8, and 25 is a photoresist film for forming the recess groove portion 15a on the surface of the n-type GaAs layer 15.

Next, the manufacturing method will be described. First, as shown in FIG. 4A, an n-type GaAs layer 15 is formed on the surface of the semi-insulating GaAs substrate 1 by ion implantation, and a photoresist film 25 is formed on the n-type GaAs layer 15.
And a resist opening 25a is formed in the portion where the gate electrode is to be formed (FIG. 4 (b)).

Next, the n-type GaAs layer 15 is etched by using the photoresist film 25 as a mask to form the recess groove 15
a is formed. At the same time, an n-type GaAs channel region 1a is formed below the recess groove 15a (FIG. 4 (c)).
).

After that, the Schottky metal film 16 is vapor-deposited on the entire surface (FIG. 4 (d)), and the photoresist film 25 is removed with an organic solvent such as acetone to lift off the Schottky metal film 16 thereon, and n-type GaAs layer 15
The gate electrode 8 is formed on the center of the bottom surface of the recess groove 15a.

Finally, in the n-type GaAs layer 15,
The source electrode 9 and the drain electrode 10 are formed on both sides of the recess groove 15a to complete the MESFET 200 (FIG. 4 (f)).

[0009]

However, the conventional Ga
In the AsMESFET, if the concentration of the n-type GaAs layer 15 is increased to reduce the resistance in the channel portion 1a in order to improve the transistor performance, the gate breakdown voltage is deteriorated, and conversely, the gate breakdown voltage is increased. When the concentration of the n-type GaAs layer 15 is reduced, the transistor performance deteriorates. As described above, in the conventional MESFET structure, there is a trade-off relationship between the high breakdown voltage of the gate and the improvement of the transistor performance, and it is difficult to obtain an MESFET having a sufficient gate breakdown voltage and high transistor performance.

Further, in the conventional method of manufacturing a GaAs MESFET, the channel portion 1a of the MESFET is formed into an n-type GaA.
Since the s layer 15 is formed by etching, the FET characteristics vary due to variations in the etching depth, and it is difficult to perform good controllability of the characteristics in the manufacturing process of the MESFET. There was a point.

The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor device having a high gate breakdown voltage and excellent transistor performance.

Another object of the present invention is to obtain a method of manufacturing a semiconductor device capable of reducing characteristic variations in the manufacturing process of a Schottky gate type field effect transistor and stably controlling characteristics.

[0013]

According to another aspect of the present invention, there is provided a semiconductor device comprising: a gate electrode arranged in a central portion of a bottom surface of a recess groove formed in a predetermined region of a semiconductor substrate; The semiconductor device includes a source electrode and a drain electrode arranged on both sides thereof, and both side portions of the recess groove on the surface of the semiconductor substrate are formed by high-concentration impurity regions. It is constituted by a low-concentration impurity region forming a junction, and both end portions and side surfaces of the recess groove are constituted by intermediate-concentration impurity regions connected to the low-concentration and high-concentration impurity regions.

Further, according to the present invention, in the above semiconductor device, an impurity region having a conductivity type different from that of the low concentration impurity region is formed in the semiconductor substrate immediately below the low concentration impurity region.

Further, in the method of manufacturing a semiconductor device according to the present invention, after forming a recess groove deeper than the thickness of the high concentration impurity region in a predetermined portion of the semiconductor substrate having the high concentration impurity region on the surface thereof, the recess is formed. A low-concentration impurity region is formed on the bottom surface of the groove by ion implantation, and the low-concentration and high-concentration regions are formed on both end portions and side surfaces of the recess groove by ion implantation at an implantation angle of 35 to 45 degrees with respect to the semiconductor substrate surface. A middle-concentration impurity region connected to the high-concentration impurity region is formed, a gate electrode forming a Schottky junction with the low-concentration impurity region is formed on the center of the bottom surface of the recess groove, and a source is formed on the high-concentration impurity regions on both sides of the recess groove. , To form the drain electrode.

In the method of manufacturing a semiconductor device according to the present invention, instead of forming the intermediate-concentration impurity region by ion implantation, the high-concentration impurity is formed so as to cover the side surfaces of the recess groove on both ends of the bottom surface of the recess groove. A side surface thin film containing impurities of the same conductivity type as that of the region is formed, and an intermediate concentration impurity region is formed at both end portions and side surface portions of the recess groove by diffusion of impurities from the side surface thin film.

A method of manufacturing a semiconductor device according to the present invention is
After the formation of the recessed groove, an intermediate concentration impurity region is formed by solid phase diffusion of impurities in the bottom surface portion and the side surface portion of the recessed groove, and the recessed groove side surface is further coated on both bottom end portions of the recessed groove, An insulating thin film is formed, and then, a conductive type impurity different from that of the intermediate concentration impurity region is selectively ion-implanted into the central portion of the bottom surface of the recess groove surrounded by the insulating thin film to obtain the intermediate concentration. A portion of the impurity region located at the center of the bottom surface of the recess groove is defined as a low-concentration impurity region, and an impurity region of a conductivity type different from that of the low-concentration impurity region is formed immediately below the low-concentration impurity region. The Schottky gate electrode is formed on the center of the bottom surface of the recess groove, and the source and drain electrodes are formed on the high-concentration impurity regions on both sides of the recess groove.

[0018]

In the present invention, the central portion of the bottom surface of the recess groove formed on the semiconductor substrate, on which the gate electrode is arranged, is formed of the low-concentration impurity region, and both end portions and side surface portions of the bottom surface of the recess groove are formed into the lower portion. Since it is composed of the intermediate-concentration impurity region connected to the high-concentration impurity region and the high-concentration impurity region of the source and drain, only the region directly below the gate electrode that determines the gate breakdown voltage is reduced in the channel portion along the bottom surface of the recess groove. As a result, the gate breakdown voltage can be increased without impairing the transistor performance.

Further, in the present invention, since the impurity region having a conductivity type different from that of the low concentration impurity region forming the central portion of the bottom surface of the recess groove is formed, the impurity region having a conductivity type different from that of the source region is formed. A barrier formed by a PN junction is formed in the path of the leak current flowing under the low-concentration impurity region and flowing into the intermediate-concentration impurity region on the drain side, thereby reducing the leak current between the source and drain. You can

In the present invention, after forming the recess groove for arranging the gate electrode in the predetermined region of the semiconductor substrate, the impurity region to be the channel is formed in the bottom surface and the side surface of the recess groove. , The thickness of the channel portion along the bottom surface of the recess groove is accurately controlled by the impurity implantation conditions regardless of the variation in the etching depth of the recess groove. The controllability can be improved.

Further, in the present invention, after the low-concentration impurity region is formed by ion implantation in the bottom surface of the recess groove, impurities from an insulating thin film formed on both end portions of the bottom surface of the recess groove so as to cover the side surface thereof are removed. Since the intermediate concentration impurity regions are formed at the bottom end portions and side face portions of the recess groove by diffusion, the semiconductor device having high gate breakdown voltage and excellent transistor performance as described above is ion-implanted into the intermediate concentration impurity region. It can be manufactured relatively easily as compared with the one formed by.

[0022]

EXAMPLES Example 1. 1 (a) to 1 (h) are cross-sectional views for explaining a structure of a Schottky gate field effect transistor according to a first embodiment of the present invention and a manufacturing process thereof. In the figure, 101 is the MESFET of this embodiment.
Then, a recess groove 4 is formed in a predetermined region of the surface of the semi-insulating GaAs substrate (hereinafter also referred to as a wafer) 1,
High-concentration impurity regions 2 are formed on both sides of the recess groove 4 of the substrate 1, and source and drain ohmic electrodes 9 and 10 are arranged on the high-concentration impurity regions 2, respectively. The center of the bottom surface of the recess groove 4 is composed of a low-concentration impurity region 5, and both sides and side surfaces of the bottom surface are composed of an intermediate-concentration impurity region 6a. 8 are arranged. Reference numeral 3 denotes an etching mask for forming the recessed groove 4 by etching, which is made of a SiO2 film. Reference numeral 18 is a resist mask for patterning the etching mask 3, and 7 is a side surface SiO2 film formed on the side surface of the recess groove 4 for forming the T-shaped gate electrode 8.

Next, the manufacturing method flow will be described. First, as shown in FIG. 1 (a), ²⁹ Si ⁺ is accelerated in a semi-insulating GaAs substrate (hereinafter also referred to as a wafer) 1 with an acceleration energy of 6
Ion implantation is performed under the conditions of 0 keV and an implantation amount of about 3 × 10 ¹³ cm ^-2, and a high concentration impurity region 2 for making ohmic contact with the source electrode 9 and the drain electrode 10 is formed on the surface portion of the substrate 1.

Next, an SiO 2 film 3 is formed on the entire surface of the GaAs substrate 1 in which the high concentration impurity region 2 is formed by plasma CV.
It is formed to a thickness of about 300 nm by the D method, a photoresist 18 is formed on the SiO2 film 3 by coating, and then the gate electrode 8 is formed.
A resist opening 18a having a width of about 0.6 .mu.m is formed by photolithography in the portion where the mask is formed (FIG. 1 (b)).

Next, using the photoresist 18 as a mask, the SiO2 film 3 is dry-etched using CF4 gas or the like to form an SiO2 film opening 3a, and this S
Using the iO2 film 3 as a mask, for example, chlorine gas,
The recess groove 4 is formed by dry etching, for example, about 200 nm from the surface of the high concentration impurity region 2 to the GaAs substrate 1 (FIG. 1 (c)).

Then, after removing the photoresist 18, ²⁹ Si ⁺ is accelerated from the upper surface of the wafer with an acceleration energy of 50 ke.
V, ion implantation under the conditions of an implantation amount of 2 × 10 ¹² cm ^-2 ,
A low-concentration impurity region 5 is formed in a portion 1a which serves as a channel at the bottom of the recess groove 4 (FIG. 1 (d)). Then ²⁹ Si
⁺ Angle of incidence on the wafer surface 40 °, acceleration energy 8
Ion implantation is performed under the conditions of 0 keV and an implantation dose of 5 × 10 ¹² cm ^-2 . At this time, due to the masking effect of the SiO2 film 3, intermediate concentration impurity regions 6a connected to the high concentration impurity regions 2 and the low concentration impurity regions 5 are formed at both end portions of the bottom surface of the recess groove 4 and side surface portions thereof (see FIG. 1 (e)).

Next, an annealing process for activating the implanted impurities is performed under the processing conditions of a temperature of 800 ° C. and a time of about 30 minutes, and then a SiO 2 film (not shown) having a thickness of about 200 nm is formed on the substrate surface. It is formed on the entire surface and is dry-etched using CF4 gas or the like to form a side surface SiO2 film 7 having a thickness of about 150 nm on the side surface of the recess groove 4.

In this state, the opening width of the recess groove 4 is 0.
It is about 3 μm (Fig. 1 (f)).

Next, a tungsten silicide film (hereinafter referred to as a WSi film) having a thickness of about 300 nm that forms a Schottky junction with n-type GaAs by a sputtering method (not shown).
Is formed on the entire surface of the substrate, and a photoresist 19 having a width of about 1 μm is left on the recess groove 4 by photolithography. Then, using the photoresist 19 as a mask, the WSi film is dry-etched using CF4 gas or the like to form the gate electrode 8 (FIG. 1 (g)).
).

Finally, after the photoresist 19 is removed, the SiO2 films 3 and 7 are removed by etching with hydrofluoric acid or the like, and further photolithography, vapor deposition of ohmic electrode material and lift-off are performed to form the source electrode 9
And the drain electrode 10 are formed, and the MESFET 101 is formed.
Is completed (Fig. 1 (h)).

In this way, the MESFET 101 of this embodiment is
Then, the recess groove 4 formed on the semi-insulating GaAs substrate 1
The central portion of the bottom surface where the gate electrode 8 is arranged is constituted by the low-concentration impurity region 5, and both ends and side surfaces of the bottom surface of the recess groove 4 are connected to the low-concentration impurity region 5 and the source,
Since it is composed of the intermediate-concentration impurity region 6a connected to the drain high-concentration impurity region 2, only the region directly below the gate electrode 8 that determines the gate breakdown voltage is reduced in the channel portion 1a along the bottom surface of the recess groove. Therefore, the gate breakdown voltage can be increased without deteriorating the transistor performance.

Further, in the method for manufacturing the MESFET of this embodiment, after forming the recess groove 4 for disposing the gate electrode 8 in a predetermined region of the semi-insulating GaAs substrate 1, the bottom surface portion of the recess groove 4 and the recess groove 4 are formed. Since the low-concentration and intermediate-concentration impurity regions 5 and 6a to be the channel portion 1a are formed on the side surface portion, the thickness of the channel portion 1a along the bottom surface of the recess groove is irrespective of variations in the etching depth of the recess groove 4. Therefore, it is possible to accurately control the impurity injection conditions, and thus it is possible to improve the controllability of the element characteristics in the manufacturing process of the MESFET 101.

Further, since the low-concentration and intermediate-concentration impurity regions 5 and 6a are formed by ion implantation, the depth and the impurity concentration can be accurately controlled.

Example 2. 2 (a) to 2 (f) are cross-sectional views for explaining the structure of the Schottky gate field effect transistor and the manufacturing method thereof according to the second embodiment of the present invention, in which 102 is the present embodiment. Example MESFET
The same reference numerals as those in FIG. 1 denote the MESFET 1 of the first embodiment.
It is the same as 01. 11 is the recess groove 4
Sidewall SiOx films (X <2) and 6b for positioning the gate electrode 8 are formed on both side surfaces and side surfaces of the recess groove 4 by diffusion of the constituent element Si from the sidewall SiOx film 11. The intermediate concentration impurity region is connected to the low concentration impurity region 5 and the high concentration impurity region 2.

Next, the manufacturing method will be described. First above
Similar to the embodiment, after forming the high-concentration impurity layer 2 and the SiO2 film 3 on the semi-insulating GaAs substrate 1, the recess groove 4 is formed (FIGS. 2 (a) and 2 (b)), and the bottom surface portion thereof is formed. The low-concentration impurity region 5 is formed in the portion 1a serving as the channel of the
(c)).

Thereafter, a SiOx film (X <2) (not shown) having a thickness of about 200 nm is formed on the entire surface of the substrate, and CF is formed.
Dry etching using a gas such as 4 to form a side surface SiOx film 1 with a thickness of about 150 nm on the side surface of the recess groove 4
1 is formed. At this time, the opening width of the recess groove 4 is 0.
It will be about 3 μm.

Next, the substrate was heated to 950 ° C. for 13 hours.
Heat treatment is performed for about 20 seconds. At this time, Si in the SiOx film is diffused into the GaAs substrate 1 and the intermediate concentration impurity region 6b connecting the high concentration impurity region 2 and the low concentration impurity region 5 from the side surface portion to the bottom end portion of the recess groove 4 is formed.
Is formed. At the same time as this heat treatment, the implanted impurities in the high concentration impurity region 2 and the low concentration impurity region 5 are activated (FIG. 2 (d)).

Thereafter, as in the first embodiment, a WSi film having a thickness of about 300 nm for forming a Schottky junction with n-type GaAs is formed on the entire surface of the substrate by the sputtering method.
This is patterned by using the photolithography technique to form the gate electrode 8 (FIG. 2 (e)). Finally, after the SiO2 film 3 and the SiOx film 11 are removed by etching with hydrofluoric acid or the like, the source electrode 9 and the drain electrode 10 are formed by photolithography, vapor deposition of ohmic electrode material, and lift-off, and the MESFE is formed.
T102 is completed (Fig. 2 (f)).

In the MESFET 102 of this embodiment, the low-concentration impurity region 5 is formed on the bottom surface of the recess groove 4 by ion implantation, and then the insulating property is formed on both end portions of the bottom surface of the recess groove 4 so as to cover the side surface thereof. Since the intermediate-concentration impurity regions 6b are formed at both end portions and side surface portions of the recess groove 4 by diffusing impurities from the thin film 11, the semiconductor device 10 having a high gate breakdown voltage and excellent transistor performance.
2 can be manufactured more easily than the one in which the intermediate concentration impurity region is formed by ion implantation as in the first embodiment.

Example 3. 3 (a) to 3 (g) are cross-sectional views illustrating a structure of a Schottky gate field effect transistor and a method of manufacturing the Schottky gate field effect transistor according to a third embodiment of the present invention. In the figure, 103 is the MESFET of this embodiment.
The same reference numerals as those in FIG. 1 denote the MESFET 1 of the first embodiment.
It is the same as 01. And 12 is the semi-insulating G
The etching mask used for forming the recessed groove 4 in the aAs substrate 1 is made of a SiN film. Further, 6c is an SiO2 film 13 with tin added to the bottom surface and the side surface of the recess groove 4.
The intermediate-concentration impurity regions 5a formed by diffusing the impurities from are formed by injecting p-type impurities into the central portion of the bottom surface of the recess groove 4 of the intermediate-concentration impurity regions 6c to reduce the n-type impurity concentration. The low-concentration impurity region 14 is a p-type impurity region formed in the semi-insulating GaAs substrate 1 below the low-concentration impurity region 5a by implanting the p-type impurity.

Next, the manufacturing flow will be described. First,
As in the first embodiment, the semi-insulating GaAs substrate 1 has ²⁹
Si ⁺ acceleration energy 60 keV, injection amount 3 × 10 ¹³
Ions are implanted under the condition of cm ⁻² to form a high concentration impurity region 2 for forming ohmic contact with the source electrode and the drain electrode (FIG. 3 (a)).

Next, a SiN film 12 having a thickness of about 300 nm is formed by plasma CVD on the entire surface of the GaAs substrate on which the high concentration impurity region 2 is formed, and a photoresist (not shown) is formed on the SiN film 12. Is applied, and a resist opening having a width of about 0.6 μm is formed by photolithography in the portion where the gate electrode is formed. Then, using this photoresist as a mask, the SiN film 12 is dry-etched using CF4 gas or the like to form the SiN film opening 12a. Next, using the SiN film 12 as a mask, dry etching is performed by, for example, about 200 nm from the surface of the high-concentration impurity region 2 to the GaAs substrate 1 by using, for example, chlorine gas to form the recess groove 4, and The resist is removed (Fig. 3 (b)).

Thereafter, a glass coating solution containing tin (Sn) is applied to the entire surface of the wafer and dried to form a SiOx film 13, and then the substrate 1 is heated to a temperature of 850.
Heat treatment is performed at a temperature of 30 to 60 minutes. At this time,
Sn in the SiOx film 13 diffuses into the GaAs substrate 1 to form an intermediate concentration impurity region 6c from the bottom surface to the side surface of the recess groove 4. At the same time as this heat treatment, the implanted impurities in the high concentration impurity region 2 are activated (FIG. 3 (c)).

Further, with hydrofluoric acid or the like, SiO
After the x film 13 is removed by etching, a SiO2 film (not shown) having a thickness of about 200 nm is formed on the entire surface of the substrate, and this is dry-etched with CF4 gas or the like to form 150 nm on the side surface of the recess groove 4. A side surface SiO2 film 7 having a thickness of about 3 is formed. At this time, the width of the opening 4a of the recess groove 4 is about 0.3 μm (FIG. 3 (d)).

Next, ²⁵ Mg ⁺ was ion-implanted from the upper surface of the wafer under the conditions of an acceleration energy of 200 keV and an implantation amount of 5 × 10 ¹² cm ^-2 , and then, an implantation impurity under the processing conditions of a temperature of 800 ° C. and a time of about 30 minutes. Annealing treatment for activating is performed. During this ion implantation, the SiN film 12 and SiO
2 Due to the masking effect of the film 7, the n-type intermediate concentration impurity region 6c at the center of the bottom surface of the recess groove 4 becomes the low-concentration impurity region 5a because its n-type conductivity due to Si is compensated by p-type Mg. A p-type impurity region 14 made of Mg is formed below the region 5a (FIG. 3 (e)).

Thereafter, as in the first embodiment, a WSi film having a thickness of about 300 nm for forming a Schottky junction with n-type GaAs is formed on the entire surface of the substrate by the sputtering method.
This is patterned by using the photolithography technique to form the gate electrode 8 (FIG. 3 (f)). Finally, the SiN film 12 and the SiO2 film 7 are removed by etching with hydrofluoric acid or the like, and then the source electrode 9 is formed by photolithography, vapor deposition of ohmic electrode material, and lift-off.
And the drain electrode 10 are formed, and the MESFET 10 is formed.
Complete 3 (Fig. 3 (g)).

In the MESFET 103 according to the third embodiment, the impurity region 14 having a conductivity type different from that of the low concentration impurity region 5a forming the central portion of the bottom surface of the recess groove 4 is formed. A barrier due to the PN junction is formed in the path of the leak current that flows from the intermediate concentration impurity region 6c on the side of the drain to the lower side of the low concentration impurity region 5a and flows into the intermediate concentration impurity region 6c on the drain side. The leakage current between the drains can be reduced.

Further, in the method for manufacturing the MESFET of this embodiment, the channel portion 1a is formed as in the first embodiment.
Since the impurity regions 5a and 6c are formed after the recess groove 4 is formed, it is possible to reduce the fluctuation of the FET characteristics due to the fluctuation of the etching depth of the recess groove 4, and to improve the controllability of the FET characteristics in the manufacturing process. it can.

Although the MESFET using GaAs as a semiconductor material has been described as an example of the semiconductor device in the above embodiment, the semiconductor material is not limited to GaAs but may be another compound semiconductor such as InP or AlGaAs. Also, the device is not limited to the MESFET described above, and other devices such as a high electron mobility transistor (HEMT) may be used, and the same effect as that of the above-described embodiment can be obtained.

[0050]

As described above, according to the semiconductor device of the present invention, the central portion of the bottom surface of the recess groove formed on the semiconductor substrate in which the gate electrode is arranged is formed of the low concentration impurity region, and the recess is formed. Since both end portions and side surfaces of the groove bottom surface are composed of the intermediate-concentration impurity regions connected to the low-concentration impurity region and the source / drain high-concentration impurity regions, the gate breakdown voltage of the channel portion along the recess groove bottom surface is determined. The concentration is lowered only in the region directly below the gate electrode, which has the effect of increasing the gate breakdown voltage without degrading the transistor performance.

Further, according to the present invention, in the semiconductor device, the impurity region having a conductivity type different from that of the low concentration impurity region forming the central portion of the bottom surface of the recess groove is formed. In the path of the leakage current that flows from the intermediate concentration impurity region to the lower side of the low concentration impurity region and flows into the intermediate concentration impurity region on the drain side,
Since a barrier is formed by the PN junction, there is an effect that the leak current between the source and the drain can be reduced.

According to the method of manufacturing a semiconductor device of the present invention, after forming a recess groove for arranging a gate electrode in a predetermined region of a semiconductor substrate, a channel is formed in a bottom surface portion and a side surface portion of the recess groove. Since the impurity region to be formed is formed, the thickness of the channel portion along the bottom surface of the recess groove is accurately controlled by the impurity implantation conditions regardless of the variation in the etching depth of the recess groove. It is possible to improve controllability of element characteristics in the element manufacturing process. As a result, there is an effect that the manufacturing yield of the semiconductor device can be improved and the cost can be reduced.

Further, according to the present invention, in the method of manufacturing a semiconductor device described above, a low concentration impurity region is formed by ion implantation in the bottom surface of the recess groove, and then the side surface of the recess groove is formed so as to cover the side surface thereof. Since the intermediate concentration impurity regions are formed at the bottom end portions and side face portions of the recess groove by diffusing impurities from the insulating thin film, a semiconductor device having high gate breakdown voltage and excellent transistor performance as described above is provided. There is an effect that the intermediate-concentration impurity region can be easily manufactured as compared with a case where the intermediate-concentration impurity region is formed by ion implantation.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a structure of a Schottky gate field effect transistor and a manufacturing method thereof according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining the structure and manufacturing method of the Schottky gate field effect transistor according to the second embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining the structure of a Schottky gate field effect transistor and a method for manufacturing the same according to a third embodiment of the present invention.

FIG. 4 is a process sectional view for explaining a structure and a manufacturing method of a conventional recess type Schottky gate field effect transistor.

[Explanation of symbols]

 1 Semi-Insulating GaAs Substrate 1a Channel Part 2 High Concentration Impurity Region 3 SiO2 Film 4 Recess Grooves 5, 5a Low Concentration Impurity Region 6a, 6b, 6c Intermediate Concentration Impurity Region 7 Side SiO2 Film 8 Gate Electrode 9 Source Electrode 10 Drain Electrode 11 Side SiOx film 12 SiN film 13 Tin-added SiO2 film 14 P-type impurity region 18 Resist film 18a Resist opening 19 Photoresist 101, 102, 103 MESFET

Claims (5)

[Claims] 1. A gate electrode arranged on a central portion of a bottom surface of a recess groove formed in a predetermined region of a semiconductor substrate surface, and a source and a drain arranged on portions of the semiconductor substrate surface on both sides of the recess groove. In a semiconductor device including an electrode, a high-concentration impurity region formed on a surface of the semiconductor substrate where source and drain electrodes are arranged, and a bottom of the recess groove where a gate electrode is arranged, An intermediate concentration impurity region that forms a Schottky junction with the electrode, a portion of the bottom surface of the recess groove on both sides of the gate electrode and a side surface portion of the recess groove, and connects the low concentration impurity region and the high concentration impurity region. A semiconductor device comprising: a region. 2. The semiconductor device according to claim 1, wherein an impurity region of a conductivity type different from that of the low concentration impurity region is formed in a region of the semiconductor substrate immediately below the low concentration impurity region. Characteristic semiconductor device. 3. A step of forming a high-concentration impurity region on a surface of a semiconductor substrate, a step of forming a recess groove deeper than a thickness of the high-concentration impurity region in a predetermined portion of the surface of the semiconductor substrate, and a bottom surface of the recess groove. Forming a low-concentration impurity region by selective ion implantation in a portion, and forming an intermediate-concentration impurity region in both end portions and side portions of the recess groove by ion implantation at an implantation angle of 35 to 45 degrees with respect to the semiconductor substrate surface. Forming step, forming a gate electrode forming a Schottky junction with the low concentration impurity region at the center of the bottom surface of the recess groove, and forming source and drain electrodes on the high concentration impurity regions on both sides of the recess groove. And a step of forming a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein instead of the step of forming the intermediate-concentration impurity region, the high concentration is formed so as to cover the side surfaces of the recess groove on both end portions of the bottom surface of the recess groove. A step of forming a side surface thin film containing impurities of the same conductivity type as that of the impurity region; and a step of forming an intermediate concentration impurity region at both bottom end portions and side surface portions of the recess groove by impurity diffusion from the side surface thin film. A method for manufacturing a characteristic semiconductor device. 5. A step of forming a high-concentration impurity region on the surface of a semiconductor substrate, a step of forming a recess groove deeper than the thickness of the high-concentration impurity region in a predetermined portion of the surface of the semiconductor substrate, and a bottom surface of the recess groove. Forming an intermediate concentration impurity region on the side and side surfaces by solid phase diffusion of impurities; forming an insulating thin film on both end portions of the bottom surface of the recess groove so as to cover the side surface of the recess groove; In the central portion of the groove bottom surface surrounded by the insulating thin film, an impurity of a conductivity type different from that of the intermediate concentration impurity region is selectively ion-implanted, and the central portion of the bottom surface of the recess groove of the intermediate concentration impurity region. As a low-concentration impurity region, and a step of forming an impurity region of a conductivity type different from that of the low-concentration impurity region immediately below the low-concentration impurity region, and a bottom surface of the recess groove. A semiconductor including a step of forming a gate electrode forming a Schottky junction with the low-concentration impurity region on the central portion, and a step of forming source and drain electrodes on the high-concentration impurity regions on both sides of the recess groove. Device manufacturing method.