JPH06237497A - Atm cell exchange switch - Google Patents

Abstract

PURPOSE:To obtain the ATM cell exchange switch in which the line utility rate of an incoming line is improved and future requirements of communication quality of a high level are satisfied. CONSTITUTION:In an ATm exchange plural input cell buffers 10-13 equipped at every incoming line are divided into plural groups and are arranged with cell switch sections 20, 21 in which an exchange network circuit 24 and a cell contention circuit 25 are equipped at every group to make independent cell competition control processing and cell transmission processing after the competition control processing at every group of input cell buffers 10-13. Then cells outputted from the exchange network circuit 24 of each group are outputted in multiplex to an outgoing line by output cell buffers 15-18 in multi-input and one-output form.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM cell switching switch for sending cells input from a plurality of incoming lines in an ATM switch to a predetermined outgoing line targeted by each cell.

[0002]

2. Description of the Related Art An ATM cell exchange switch has been used as an ATM cell exchange switch for sending cells input from a plurality of incoming lines to an intended outgoing line of each cell in an ATM exchange.
A plurality of input cell buffers are provided for each incoming line accommodated by the TM switch and temporarily hold cells input from the corresponding incoming line, and a plurality of input cell buffers are provided for each outgoing line accommodated by the ATM switch, respectively. A plurality of output cell buffers for controlling cell transmission to the line, and one cell switch unit for transmitting the cells held in each of the input cell buffers described above to a predetermined output cell buffer for the intended output line of each cell. A configuration having and has been proposed.

Here, the cell switching section sends a cell output from each input cell buffer to a predetermined output cell buffer for a target output line of each cell, and a plurality of switch network circuits in which the target output line competes. Cell competition circuit that selects cells to be output to the switching network circuit from cells held in the input cell buffer so that the cells are not simultaneously output to the same switching network circuit.

The cell competing circuit in the cell switch section corresponds to the root network in the following document 1.

[Reference 1] SE87-132 "Study on high-speed packet switching switch" A supplementary explanation of the cell competing circuit of the cell switch section used in the above-mentioned conventional method is as follows.

The cell contention circuit is composed of a batcher network with a survival report function and a survival report circuit. In the batcher network with a survival report function, the cell to be output next from each input cell buffer is The header (destined destination (outgoing line number) is described) is synchronously transmitted. In the batcher network with a survival report function that receives headers from each input cell buffer, the received plurality of headers are sorted in order of destinations and passed to the award report circuit. This residual report circuit has header arrival terminals for the number of outgoing lines accommodated in the ATM switch,
Receiving headers sorted in order of destination by each header arrival terminal, and comparing the destinations of the headers between adjacent arrival terminals, and if they are different from each other, the batcher with the survival report function that the header has passed through. The route in the network is traced back and "remaining" is reported to the corresponding input cell buffer. If the destination of the header is the same between adjacent arrival terminals, only one of them will be "winning".
To report.

Each input cell buffer sends one header to the cell contention circuit, and it is set as one cycle until the presence or absence of the "winning" report for the header is determined from the cell contention circuit, and the same processing is repeated an appropriate number of times. Be done.

However, in the next cycle, the input cell buffer which has received the victory report sends the same header as the previous time, but the input cell buffer which has not received the victory report is stored in the buffer. The cell header will be sent to the cell contention circuit. The header that has won once has the mechanism to survive the next cycle and beyond.

By repeating the selection process by the cell competition circuit as many times as necessary, it is possible to avoid the duplication of the destinations of the cells output from the respective input cell buffers to the switching network circuit. Then, more cells having different destinations can be collectively sent to the switching network circuit.

[0010]

By the way, the recent improvement of digital communication technology is remarkable, and the data transmission speed may be further improved in the future due to the spread of the technology such as ATM (asynchronous transfer mode). for that purpose,
There is also a demand for development of an ATM cell exchange switch or the like which efficiently processes a larger number of cells to a predetermined destination in a shorter time.

From the above viewpoint, in the above-mentioned conventional ATM cell exchange switch, when the cell discard rate in the cell contention circuit is 10 ^-10 or less, the line utilization rate of the incoming line is 80% at maximum. There is a problem in that the level can be increased only to a certain degree, and the level required in the future (for example, increasing the line utilization rate of the incoming line to 90% or more) cannot be satisfied.

The present invention has been made in view of the above circumstances, and can improve the line utilization rate of incoming lines to 95% or more, and can also satisfy future high-level communication quality requirements. It is an object to provide an ATM cell switching switch.

[0013]

SUMMARY OF THE INVENTION An ATM cell exchange switch according to the present invention comprises a plurality of input cell buffers which are provided for each incoming line accommodated in an ATM switch and temporarily hold cells input from the corresponding incoming line. And a plurality of output cell buffers provided for each outgoing line accommodated in the ATM switch and controlling cell transmission to the corresponding outgoing line, and the cells output from the respective input cell buffers are aimed by the respective cells. From the cells held in the input cell buffer so that the switching network circuit that sends to the specified output cell buffer for the outgoing line and the cells that compete for the desired outgoing line are not output to the same switching network circuit at the same time With a cell contention circuit for selecting cells to be output to the switching network circuit,
It controls the input and output of cells in the ATM switch.

However, as a means for solving the problem, a plurality of input cell buffers provided for each incoming line are divided into a plurality of groups. Then, by arranging a cell switch unit equipped with the switching network circuit and the cell competition circuit for each group of the input cell buffer, the competition control processing by the cell competition circuit and the cell transmission processing by the switching network circuit are performed. Are independently executed for each group of the input cell buffers.

Further, the output cell buffer provided for each outgoing line is a multi-input for receiving cell inputs from each switching network circuit provided for each group of input cell buffers, multiplexing them, and outputting them. A one-output type cell buffer circuit is used.

[0016]

The ATM cell exchange switch according to the present invention divides the input cell buffer into a plurality of groups, and performs the competition control processing by the cell competition circuit for avoiding the duplication of cell destinations and the switching network after the competition control processing. The process of sending cells to a predetermined destination by the circuit is executed independently for each group,
The output from the switching network circuit of each group is multiplexed and output by the multi-input one-output type cell buffer provided for each outgoing line. The cell competition circuit is reduced by the number of destination competitors due to grouping. The number of discarded cells due to duplication of destinations in halved.

Therefore, when considering the line utilization rate of the incoming line under the condition that the cell discard rate is kept at a constant value in the entire ATM cell switching switch, the contention control of the cells of all input cell buffers is controlled by a single cell contention circuit. The line utilization rate of the incoming line can be greatly improved, in other words, the cell loss rate characteristic can be greatly improved, and the demand for high-level communication quality in the future can be improved. Can be fully supported.

[0018]

1 shows an embodiment of an ATM cell exchange switch according to the present invention. AT of this embodiment
The M cell exchange switch is used when the number of inputs N is 4
The four incoming lines ip0 to ip3 accommodated by the exchange and the four input cell buffers 10, 11, 12, 13 which are provided for each incoming line and temporarily hold (store) cells input from the corresponding incoming lines. And the four incoming lines ip0
Four output lines op0 to op3 accommodated in the ATM switch corresponding to ip3, and four output cell buffers 15 and 16 provided for each of these output lines and controlling cell transmission to the corresponding output lines. , 17, 18 and the cells held in the input cell buffers 10, 11, 12, 13 described above are sent to the output cell buffers 15, 16, 17, 18 for the destinations (outgoing lines) of the respective cells. It is configured to include two cell switch units 20 and 21 that operate.

In this embodiment, the four input cell buffers 10, 11, 12, 13 provided for each of the above-mentioned incoming lines are used.
Input cell buffers 10 and 11 and input cell buffer 1
It is divided into two groups of 2, 13.

In addition, the above-mentioned two cell switch units 20,
Reference numeral 21 denotes a switching network circuit 24 for sending cells output from four input cell buffers to an output cell buffer for each cell's intended destination by a predetermined routing process, and a plurality of competing destinations. In order to prevent cells from being output to the same switching network circuit 24 at the same time, a cell contention circuit 25 for selecting a cell to be output to the switching network circuit 24 from the cells held in the controlled input cell buffer is provided. is there.

Since the number of inputs N is 4 in this embodiment, the switching network circuit 24 has four cell input ports SRD0 to SRD3 and four cell output ports SS.
D0 to SSD3 are provided, and the cells selected in any cell input port can be sent to the cell output port corresponding to the destination by the multi-staged route selection switches.

The cell competing circuit 25 corresponds to the routing network described in the conventional example, and the header of the cell to be output next from the input cell buffer (destined destination (outgoing line number) is described. 4 header input terminals NRD0 to NRD3, and a batcher network with a survival report function (not shown) that sorts the four headers received by these header input terminals NRD0 to NRD3 in order of destination. With respect to the four headers rearranged in order of destination by the batcher network with a survival report function, a survival report circuit (not shown) for performing selection processing for avoiding the existence of a plurality of headers having the same destination. It is provided with a configuration.

The win / loss report circuit is provided with four header arrival terminals for receiving the headers rearranged in order of destination by the batcher network with win / win report function, and the destinations of the headers are arranged between adjacent arrival terminals. In comparison, if they are different from each other, the route is traced back to the route in the batcher network with a win / loss report function that the header has passed, and the "win / win" is reported to the corresponding input cell buffer. When the destinations of the headers are the same between the adjacent arrival terminals, only one of them is reported as "win".

Of the above two cell switch sections 20 and 21, one cell switch section 20 is the input cell buffer 1
The processing of the cells held by 0 and 11 is shared, and the cell switching unit 21 on the other side is shared of the processing of the cells held by the input cell buffers 12 and 13.

That is, the cell switch unit 20 performs a process of transmitting the cells held in the input cell buffers 10 and 11 to the output cell buffers 15, 16, 17 and 18 targeted by the respective cells, and the other cell switch units. Reference numeral 21 performs a process of transmitting the cells held in the input cell buffers 12 and 13 to the output cell buffers 15, 16, 17 and 18 targeted by the respective cells.

Each input cell buffer 10, 11, 12, 1
The connection relationship between 3 and the two cell switch units 20 and 21 is as follows.

The input cell buffer 10 which receives a cell input from the incoming line ip0 includes a header input terminal NRD0 of the cell contention circuit 25 of the cell switch section 20 and a cell switch section 2 of the cell switch section 20.
0 is connected to the cell input port SRD0 of the switching network circuit 24, the header describing the destination data of the held cell is sent to the header input terminal NRD0, and a predetermined value in the cell contention circuit 25. After the selection process (competition control process) of 1 is completed, the cells that survive the selection process are sent to the cell input port SR0.

The input cell buffer 11 which receives a cell input from the incoming line ip1 has a header input terminal NRD1 of the cell contention circuit 25 of the cell switch unit 20 and a cell input port SRD1 of the switching network circuit 24 of the cell switch unit 20. Is connected to and is sent to the header input terminal NRD1 in which the destination data of the held cell is described, and after the predetermined selection processing (contention control processing) in the cell contention circuit 25 is completed. , The cells that survive the selection process are sent to the cell input port SR1.

The input cell buffer 12 that receives a cell input from the incoming line ip2 has the header input terminal NRD0 of the cell contention circuit 25 of the cell switch unit 21 and the cell input port SRD0 of the switching network circuit 24 of the cell switch unit 21. Is connected to and is sent to the header input terminal NRD0 in which the destination data of the held cell is described, and after the predetermined selection processing (contention control processing) in the cell contention circuit 25 is completed. , The cells that have survived the selection process are sent to the cell input port SR0.

The input cell buffer 13 that receives a cell input from the incoming line ip3 has a header input terminal NRD1 of the cell contention circuit 25 of the cell switch unit 21 and a cell input port SRD1 of the switching network circuit 24 of the cell switch unit 21. Is connected to and is sent to the header input terminal NRD1 in which the destination data of the held cell is described, and after the predetermined selection processing (contention control processing) in the cell contention circuit 25 is completed. , The cells that survive the selection process are sent to the cell input port SR1.

Each of the cell switch units 20 and 21 has header input terminals NRD2 and NDR in the cell contention circuit 25.
3 and the cell input port SR in the switching network circuit 24
D2 and SRD3 are empty and nothing is input.

Further, the four output cell buffers 15, 16, 17, provided for each of the outgoing lines op0 to op3 described above,
As shown in FIG. 2, reference numeral 18 denotes two cell input sections A and B using a FiFo memory, and cells output from these two cell input sections A and B are multiplexed to output an output line. A two-input one-output type cell buffer including a multiplexing output circuit 27 for
Cell input is received from each of the switching network circuits 0 and 21. The FiFo memory used for the cell input sections A and B has a capacity capable of holding data of several tens to several hundreds of cells in this embodiment, and each FiFo memory is multiplexed when empty. An EMP signal indicating that the signal is empty is output to the digitized output circuit 27. The multiplexing output circuit 27, based on the EMP signal from each FiFo memory,
Read cells from memory. The operation of this 2-input 1-output cell buffer is shown in (a), (b) and (c) of FIG.
As shown in.

As shown in FIG. 3A, the cell input section A
When cells are stored in both the cell input section B and the cell input section B,
The cells are read from each cell input section alternately.
Further, as shown in FIG. 3B, one cell input unit A
If cells are stored only in the cell, cells are continuously read from the cell input section A, and an empty slot is not inserted in the output. As shown in (c) of FIG. 3, when cells are stored only in the other cell input section B, similarly, cell reading is continuously performed from the cell input section B, and an empty cell is output. Do not insert slot.

Each of the above output cell buffers 15, 16, 1
The connection between 7, 18 and each switching network circuit 24 of the two cell switch units 20, 21 is as follows.

The cell output port SSD0 of the switching network circuit 24 of the cell switching section 20 and the cell output port SSD0 of the switching network circuit 24 of the cell switching section 21 are input to the output cell buffer 15 connected to the output line op0. And are connected.

Then, as an input of the output cell buffer 16 connected to the output line op1, the cell switch unit 2 is used.
0, the cell output port SSD1 of the switching network circuit 24 and the cell output port SS of the switching network circuit 24 of the cell switch unit 21.
D1 is connected.

As an input of the output cell buffer 17 connected to the output line op2, the cell switch section 20 is used.
Cell output port SSD2 of the switching network circuit 24 and the cell output port SSD of the switching network circuit 24 of the cell switch unit 21
2 and are connected.

The cell switch unit 20 is used as an input of the output cell buffer 18 connected to the output line op3.
Cell output port SSD3 of the switching network circuit 24 and the cell output port SSD of the switching network circuit 24 of the cell switch unit 21
3 and 3 are connected.

In the ATM cell exchange switch of the above embodiment, the cells input to the input cell buffers 10 and 11 are
Eventually, it will be sent to the output cell buffer for the intended destination by the switching network circuit 24 of the cell switching unit 20, but in order to eliminate the collision of cells on the switching network circuit 24 of the cell switching unit 20. In addition, contention control is performed in advance by the cell contention circuit 25 of the cell switch unit 20 so that the destinations do not overlap.

On the other hand, the cells input to the input cell buffers 12 and 13 are finally sent to the output cell buffer for the intended destination by the switching network circuit 24 of the cell switch unit 21, but the cells are Switch part 21
In order to eliminate the collision of cells on the switching network circuit 24, the contention control is performed in advance by the cell contention circuit 25 of the cell switch unit 21 so that the destinations do not overlap.

Although not described in detail, the contention control processing of the cell contention circuit 25 in the cell switch units 20 and 21 is based on the rooting network disclosed in Document 1 shown in the section of the conventional example.

In this way, when the contention control is individually performed for each group of the input cell buffers divided into two groups, the switching network circuit 2 in each cell contention circuit 25.
As a result, only half of the switch size in 4 will be subject to contention control, the number of cell discards due to duplication of destinations will be halved, and the ATM cell switching switch as a whole can maintain a constant cell discard rate. When considering the line utilization rate of the incoming line, comparing with the conventional method in which the contention control of the cells of all input cell buffers is performed by a single cell contention circuit,
It is possible to significantly improve the line utilization rate of incoming lines.

When the inventors of the present application actually performed simulation, the input cell buffer was set to 2 as in one embodiment.
When contention control is performed separately for each group, as shown in FIG. 4B, for example, even if the cell discard rate in the cell contention circuit is 10 ⁻¹⁰ or less, the line utilization rate of the incoming line is 95%. It was confirmed that it could be improved to more than 100%, and it was confirmed that it could sufficiently meet the future demand for high level communication quality. It should be noted that FIG. 4A shows a conventional discard rate characteristic for comparison.

In the above embodiment, the input cell buffer provided for each incoming line is divided into two groups, and the cell switch section having the switching network circuit 24 and the cell competition circuit 25 is provided for each group. I decided to equip it. However, the number of input cell buffers to be grouped is 2 in the first embodiment.
It is not limited to one. Divide into three or more groups and equip each group with a cell switch part,
Further, by equipping the multi-input one-output cell buffer according to the number of divided groups as the output cell buffer, it can be expected that the line utilization rate of the incoming line is further improved.

Further, in the case of one embodiment, the number of inputs N is 4 and the switch size of the circuit equipped in the cell switch units 20 and 21 is 4 × 4, but the present invention is applied to any number of inputs. It goes without saying that it is possible to do.

[0046]

As is apparent from the above description, the ATM cell exchange switch according to the present invention uses the cell contention circuit for dividing the input cell buffer into a plurality of groups and avoiding the duplication of cell destinations. The contention control processing and the cell transmission processing to the predetermined destination by the switching network circuit after the contention control processing are executed independently for each group, and by the multi-input one-output type cell buffer provided for each outgoing line. The output from the switching network circuit of each group is multiplexed and output.
The number of cells discarded due to duplication of destinations in the cell competition circuit is reduced by half by the number of destination competitors reduced by grouping.

Therefore, when considering the line utilization rate of the incoming line under the condition that the cell discard rate is kept at a constant value for the entire ATM cell switching switch, the contention control of the cells of all the input cell buffers is performed by a single cell contention circuit. The line utilization rate of the incoming line can be greatly improved, in other words, the cell loss rate characteristic can be greatly improved, and the demand for high-level communication quality in the future can be improved. Can be fully supported.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of an output cell buffer according to an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of an output cell buffer according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of effects of one embodiment of the present invention.

[Explanation of Codes] ip0 to ip3 Incoming line 10, 11, 12, 13 Input cell buffer 15, 16, 17, 18 Output cell buffer 20, 21 Cell switch unit 24 Switching network circuit 25 Cell competing circuit A, B Cell input unit 27 Multiplexed output circuit

Claims (1)

[Claims] 1. A plurality of input cell buffers, which are provided for each incoming line accommodated in an ATM exchange and temporarily hold cells input from the corresponding incoming line, and are provided for each outgoing line accommodated in the ATM exchange. A plurality of output cell buffers for controlling cell transmission to the corresponding output lines, and a switching network for transmitting the cells output from each input cell buffer to a predetermined output cell buffer for the output line targeted by each cell. Cell competition that selects the cell to be output to the switching network circuit from the cells held in the input cell buffer so that multiple cells that conflict with the circuit and the target outgoing line do not output to the same switching network circuit at the same time An ATM cell exchange switch for controlling cell input / output in an ATM switch, comprising a plurality of circuits, the plurality of input cells being provided for each incoming line. Buffers are divided into a plurality of groups, and a cell switch unit equipped with the switching network circuit and the cell contention circuit is provided for each group of the input cell buffers, thereby exchanging contention control processing by the cell contention circuit. The cell transmission processing by the network circuit is executed independently for each group of the input cell buffers, and the output cell buffers provided for each output line are provided for each group of input cell buffers. An ATM cell exchange switch characterized by using a multi-input one-output type cell buffer circuit that receives cell inputs from each switching network circuit, multiplexes them, and outputs them.