JPH06237027A - Magnetoelectric transducer - Google Patents

Abstract

(57) [Summary] [Purpose] In a Hall element comprising a Ga _x In _1-x As / InP heterojunction, the mixed crystal ratio of the Ga _x In _1-x As layer constituting the hetero interface ( By adjusting x), it is possible to provide an unprecedented highly sensitive Hall element. A heterojunction composed of indium phosphide (InP) and gallium indium arsenide (Ga _x In _1-x As) having a mixed crystal ratio x of 0.37 or more and 0.57 or less is provided. The mixed crystal ratio x is changed in the magnetoelectric conversion element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetoelectric conversion element using a compound semiconductor material, and more particularly to a new high performance Hall element having a heterojunction of GaInAs mixed crystal and InP.

[0002]

2. Description of the Related Art Hall (Ha) is one of so-called magneto-electric conversion elements for detecting a magnetic field and converting its intensity into an electric signal.
11) elements are known. The Hall element is a kind of magnetic sensor that utilizes the Hall voltage generated by the movement of electrons in the semiconductor when a magnetic field is applied, and is already widely used in industry such as rotation detection.

In addition to simple semiconductors such as Si and Ge, III-V group compound semiconductors such as InSb, InAs and GaAs are also used for Hall elements. A semiconductor suitable for a Hall element is required to have a physical property of outputting a large Hall voltage in order to detect a weak magnetic field with high sensitivity.
The Hall voltage depends on the Hall coefficient, and the Hall coefficient increases in proportion to the electron mobility. Therefore, to obtain a so-called highly sensitive Hall element that generates a high Hall voltage,
Semiconductor materials and the like that exhibit high electron mobility are mainly used.

Conventionally, as a highly sensitive Hall element, one using an InSb or InAs semiconductor material has been proposed (see, for example, JP-A-59-13385).
Also, as a highly reliable Hall element whose element characteristics change little with temperature and which has high reliability, it is known to use GaAs having a large band gap (for example, JP-A-53-207).
82). Furthermore, ternary mixed crystals of InAsSb, InGaAs, etc., which have high electron mobility and relatively large band gap.
It has also been proposed to apply a III-V group compound semiconductor to a material of a Hall element which has a small temperature dependency of characteristics and high sensitivity (for example, see JP-A-61-2378).

In recent years, precise rotation control of automobile engines,
There is a growing need for sensing technology in a high temperature environment such as detection, and there is a demand for a high-performance Hall element that has a high Hall output voltage and has little change in element characteristics due to temperature. However, InSb and InAs, which have been conventionally applied to Hall elements, have a drawback that they are not reliable in use in an environment where the band gap is small, the temperature dependence is large, and the temperature is high, such as in an automobile engine room. It was On the other hand, a conventional GaAs Hall element having a relatively large bandgap and a small temperature dependency of element characteristics has a difficulty in achieving high sensitivity because of low electron mobility and low Hall voltage.

Recently, gallium indium arsenide (Ga _x In _1-x As: x represents a mixed crystal ratio) composed of three kinds of elements even in the same III-V group compound semiconductor as in the past.
So-called GaInAs / InP having a heterojunction composed of a ternary mixed crystal and indium phosphide (InP)
Heterojunction Hall devices have been reported (for example, Shinobu Okuyama et al., Proceedings of the 53rd Autumn Meeting of the Japan Society of Applied Physics No. 3, 1992, Lecture No. 16a-).
SZC-16, p. 1078). This GaInAs / In
The P-heterojunction Hall element is considered to be a new Hall element having excellent sensitivity because the characteristic temperature change is relatively small and the room temperature electron mobility is extremely high.

Certainly, it has been recently reported that the heterojunction system of Ga _x In _1-x As and InP exhibits high electron mobility at room temperature (for example, Kenjiro Konuma et al.
Proceedings of the 53rd Autumn Meeting of Japan Society of Applied Physics
1, 1992, Lecture No. 18a-ZE-3, 283
Page, or Hilde Hardtdegen et al., J. Am.
Crystal Growth, Vol. 116, 19
92, p. p. 521-523. ), Is attracting attention as a new material for obtaining a highly sensitive Hall element.

In the GaInAs Hall element, as in the case of the conventional Hall element such as GaAs or InSb, a terminal for connection through the element manufacturing process, for example, the input and output ohmic electrode forming step. It is mounted on a frame equipped with a frame, and after electrically connecting the terminals of the frame and the input / output electrodes of the Hall element, a part of the frame is made of resin such as epoxy resin for sealing the semiconductor element. The Hall element mounted on the frame is surrounded and surrounded by a mold (mol
d) It becomes a product.

[0009]

However, the physical properties of the interface of the heterojunction influence the device characteristics of GaInA.
In the s Hall element, for example, the characteristics of the Hall element may change after the ohmic electrode forming step, the encapsulation resin encapsulation, and the heating step such as the molding step. Are known. This change in characteristics appears as an increase in the unbalance ratio, which is one of the important characteristics of the Hall element, and a deterioration in product sensitivity, and there is a conventional defect that the original characteristics of the GaInAs Hall element are impaired. there were.

[0010]

In view of the drawbacks of the prior art, the present inventor has found that InP and GaInAs are heterogeneous.
When the junction is used as the magnetic sensing part of a Hall element, it is possible to output a high Hall voltage, so it is considered to provide a new Hall element with high sensitivity and high reliability with little temperature change in characteristics. Added. As a result, In
When forming a heterojunction between the P epitaxial growth layer and the Ga _x In _1-x As epitaxial growth layer, Ga _x I having a mixed crystal ratio (x) in a specific range at the hetero interface is formed.
by interposing an n _1-x As layer, and also
As a result of paying attention to the mixed crystal ratio x of the aInAs layer, the inventors have found that the above object can be achieved, and have reached the present invention.

That is, according to one aspect of the present invention, Ga _x In having a mixed crystal ratio of 0.37 ≦ x ≦ 0.57 provided on an InP substrate.
_1-x formed by including an As layer at the GaInAs heterojunction Hall element, by the Ga _x an In _1-x As layer of mixed crystal ratio x is different from the multilayer laminated structure to one another, device functional magnetically sensitive portion It is intended to provide a new method for relaxing and absorbing thermal strain and the like applied to a region in a device forming process, particularly a process involving heating therein, thereby contributing to stable supply of high-quality GaInAs Hall devices. Furthermore, when the mixed crystal ratio x with indium phosphide (InP) is 0.37 or more,
Gallium indium arsenide (Ga) in the range of 57 or less
_x In _1-x As) is a magnetoelectric conversion element comprising a heterojunction composed of Ga _x In _1-x As and the Ga _x In _1-x As layers are Ga _x In _1-x As multilayers having different mixed crystal ratios x. Ga _x In composed of a laminated body and also in direct contact with the InP layer
The _1-x As layer of Ga mole fraction x, be characterized by being provided with a heterojunction is made smaller than the Ga mole fraction Ga _x In _1-x As layer constituting the multi-layered otherwise Thus, it is intended to provide a magnetoelectric conversion element having a high performance that has never been obtained. In another invention, the Ga _x In _1-x As layer forming the heterojunction is composed of a composition change layer in which the Ga mixed crystal ratio x is continuously and gradually increased from the InP side.

Usually, in forming the Ga _x In _{1 -x} As / InP heterojunction in consideration of application to a Hall element, a high-resistance InP single crystal substrate having a semi-insulating property is used. Practically, In having a specific resistance of 10 ⁴ Ω · cm or more
It is common to use a substrate of P single crystal. These crystals can be easily manufactured by a liquid-encapsulated Czochralski (LEC) method or, recently, a vertical Bridgman method called VB method, etc., and a hole provided with a GaInAs / InP heterojunction as in the present invention is formed. For the device, there is no fear that the growth method of the InP single crystal substrate, which is the base material of the device, will be a manufacturing constraint.

When forming a heterojunction on the InP single crystal substrate by the InP epitaxial layer and the Ga _x In _1-x As epitaxial layer, the InP layer and the Ga _x I layer are formed.
The stacking order with the n _{1- x} As layer is not particularly limited, but in order to obtain a high quality Ga _x In _1-x As layer, first, an InP epitaxial layer is deposited as a buffer layer on the InP substrate,
After that, it is common to grow the Ga _x In _1-x As layer epitaxially. By providing this buffer layer, it is possible to obtain the effect of suppressing the diffusion of impurities such as Fe from the substrate into the epitaxial growth layer. In addition, since the effect of suppressing the propagation of crystal defects existing in the substrate to the epitaxial growth layer is produced, the electron mobility is improved and the sensitivity of the Hall element is increased. Of course, it goes without saying that the buffer layer may be omitted.

There is no particular limitation on the epitaxial growth method for the InP layer and the Ga _x In _1-x As layer that form the above-mentioned heterojunction, and there is no limitation to the liquid phase epitaxial growth method (LPE).
Method), a molecular beam epitaxial growth method (MBE method), a metalorganic pyrolysis vapor phase epitaxy method (so-called MOCVD method or MOVPE method), and an MO / MBE method that combines both the MBE method and the MOCVD method. However, at present, the MOCVD method is mainly used for the growth of InP, and in particular, cyclopentadienylindium (C ₅ H ₅ In) having a monovalent valence is used as a starting material for In at atmospheric pressure (atmospheric pressure). ) The MOCVD method makes it possible to obtain high-quality epitaxial growth layers of InP and GaInAs. Further, there is no problem even if the growth methods are different between the two, such as growing the InP layer by MOCVD and growing the Ga _x In _1-x As layer by the MBE method. Needless to say, even in the case of depositing the Ga _x In _1-x As multi-stack, it is not necessary to provide the multi-stack with only one growth method, and the effect of the present invention can be obtained even if the growth method is different for each layer .

The mixed crystal ratio x of the Ga _x In _1-x As layer is 0.37≤x≤0.57, preferably 0.45≤x≤0.50. Because the composition is I
As the mixed crystal ratio x = 0.47 that is lattice-matched to nP, the difference in lattice constant between GaInAs and InP, that is, the lattice mismatch becomes remarkable, which induces a large amount of crystal defects and the like, which lowers the electron mobility. As a result, the characteristics of the Hall element greatly hinder the improvement of the product sensitivity. The range of mixed crystal ratio was limited from the allowable limit of lattice mismatch.

Further, the present inventor diligently studied the structure of a heterojunction of Ga _x In _1-x As and InP having a mixed crystal ratio within the above defined range. As a result, InP
The Ga _x In _1-x As epitaxial film with a different mixed crystal ratio x is formed as compared with the case where a single layer of Ga _x In _1-x As having a specific mixed crystal ratio x is deposited on the layer to form a heterojunction. It has been found that the electron mobility can be further improved by depositing layers to form a heterojunction. In that case, the Ga _x In _1-x As layer may have a multi-layer structure having different mixed crystal ratios x, or may have a structure in which the mixed crystal ratios x continuously change.

When a multi-layer structure having different mixed crystal ratios is used, two layers having different mixed crystal ratios, a Ga _y In _1-y As layer and a Ga layer, are formed.
_{The z} In _{1 -z} As layers (where y ≠ z) may be alternately repeated, or layers having different mixed crystal ratios x may be randomly arranged.

When the two layers are alternately laminated, the mixed crystal ratios y and z of the two layers must be 0.90≤y + z≤1.0. This is because the mixed crystal ratio of the GaInAs layer approaches 0.47 on average, which facilitates lattice matching with InP that is the substrate. The same applies to the case of a multi-layer structure, so that the mixed crystal ratio of each layer approaches the lattice constant of InP on average, that is, 0.45 ≦ (x ₁ + x ₂ + ... + x _n ) × 1 / n ≦ 0.50 (1) should be satisfied.

In the case of a multi-layered structure, if the mixed crystal ratio of the (n) th deposited layer is xn, the (n) th layer is the (n + 1) th layer to be deposited. So that the mixed crystal ratio x _{n + 1} satisfies the following relational expression (2) x _n ≤x _{n + 1} (2) where (n) is a positive positive number. Increasing Ga _xn In
By providing _1-xn As, the mobility is remarkably increased. The number of layers is usually 2 to 5 layers. Further, the same effect can be obtained by using a composition change layer in which the mixed crystal ratio x of the Ga _x In _1-x As layer is gradually increased from the InP side instead of the multilayer structure as described above. Further, when such a Ga _x In _1-x As layer having a different mixed crystal ratio is provided, the mixed crystal ratio of the Ga _x In _1-x As layer in a portion in direct contact with the InP layer is set to 0.
There is an important significance in getting closer to 47.

Further, according to the present invention, the above Ga _x In
There is no particular limitation on the film thickness of the _1-x As layer. However,
In the actual fabrication of Hall elements, a process called mesa etching for removing the crystal layer in a specific region is adopted to electrically insulate the elements, but at this time, it is removed by etching for the insulation between elements. The thickness of the conductive layer,
If the total thickness of the epitaxial growth layer is increased, the time required for etching is inevitably increased, and a significant difference occurs in the etching amount and etching shape due to the crystal orientation. This leads to an increase in the unbalance ratio, which is one of the important characteristics of the Hall element, which hinders the improvement of the element characteristics and lowers the yield of non-defective elements. Further, if the thickness of the Ga _x In _1-x As layer is simply increased, the crystallinity will be deteriorated when, for example, an InP layer or a Ga _x In _1-x As layer is provided on the layer. It can be done. Therefore, in constructing the structure described in the present invention, each of the constituent elements, Ga _x In
The thickness of the _1-x As layer is preferably about 0.5 nm to about 20 nm, and the Ga _x In _1-x A according to the present invention is preferably used.
The total thickness of the s-layer stack is about 100 nm to about 500 n
Good results are obtained with m.

As described above, according to the present invention, using a crystal substrate that is easily available, the mixed crystal ratio x in direct contact with the InP layer is minimized, and the mixed crystal ratio x is gradually increased to increase Ga _x In.
By constructing a heterojunction such as by providing a _1-x As layer, a magnetoelectric conversion element having unprecedented high sensitivity characteristics can be obtained, which will bring further advances in high-precision sensing technology in industry. Bring effect.

[0022]

The present invention is based on Ga _x forming a heterojunction with InP.
By changing the Ga mixed crystal ratio x of the In _1-x As layer, the electron confinement effect is utilized to increase the electron mobility.

[0023]

EXAMPLES The present invention will be specifically described below with reference to four examples. (Embodiment 1) FIG. 1 is a sectional view showing an example of a heterostructure according to the present invention. (101) in FIG. 1 is a semi-insulating InP single crystal having a plane orientation (100) formed by adding iron (Fe) used as a substrate for forming the heterojunction. In this example, a crystal having a specific resistance of about 10 ⁷ Ω · cm was used, but the plane orientation and the specific resistance of the above-mentioned crystal are appropriately selected in consideration of the Hall element manufacturing process, the crystal layer growth method, and the like. Just do it. In the figure, (102) is a crystal substrate (10
1) MOCVD under atmospheric pressure using C ₅ H ₅ In as an In source
It is a non-doped (undoped) InP epitaxial crystal layer having a film thickness of about 100 nm grown by the method. Furthermore, InP
A Ga _0.42 In _0.58 As epitaxial layer (10) having a mixed crystal ratio of 0.42 and a film thickness of about 20 nm is formed on the layer (102).
3-1) was provided by the above atmospheric pressure MOCVD growth method. Next, a Ga _0.47 In _0.53 As epitaxial layer (103-2) with a mixed crystal ratio of 0.47 was grown to a thickness of 400 nm, and a heterojunction was formed with a total of two GaInAs layers and InP layers with different mixed crystal ratios. did. The epitaxial layer (102-
All of the films 103) were grown by MOCVD, but as described above, either normal pressure method or reduced pressure method may be used, and the In source may be C ₅ H.
Not only ₅ In, but other growth methods such as MBE and MO / MBE can be adopted without any problem. The wafer having such a structure was appropriately processed by a well-known photolithography method and etching method to obtain a Hall element. Then, a gold-germanium (Au-Ge) alloy containing germanium in an amount of about 13% by weight was vacuum-deposited to form an input electrode and an output electrode, and then the wafer on which the electrode material was deposited was heated to a temperature of 420. ℃
Then, heat treatment was performed for 3 minutes, and the electrode was used as an ohmic electrode (104). In this example, Au containing 13 wt% of Ge as the ohmic electrode material was used as described above.
-Ge alloy was used, but of course Au-Ge
The Ge content of the alloy is not limited to the above content, and a metal material other than Au-Ge may be used.

(Comparative Example) Further, in order to compare the electric characteristics, a simple GaInA from the conventional method was prepared by the same method as described above.
A wafer having a structure having an s / InP heterojunction was also manufactured. FIG. 2 schematically shows a sectional view of the structure. In FIG. 2, (201) is the InP single crystal substrate used as the substrate. The specifications of the same substrate are the same as those in the first embodiment. First, on this substrate (201), similarly to the above, undoped InP
The epitaxial layer (202) was grown. After that, a Ga _0.47 In _0.53 As epitaxial layer (203) having a constant mixed crystal ratio of 0.47 is deposited to form a heterojunction with the InP layer (202) and a GaInAs layer having a single mixed crystal ratio. did. (204) is the outermost GaInAs layer (20
3-2) Shows an input / output ohmic electrode formed above. Both the film thickness and the carrier concentration were the same as those in the case of having the structure according to the present invention of the first embodiment within a measurement error range of about ± 5%.

The Hall element produced as described above was subjected to electrical characteristic evaluation. Table 1 shows the evaluated items and characteristic values in comparison with the case of the present invention and the conventional example.

[0026]

[Table 1]

As shown in Table 1, in the case of the present invention, both the input resistance and the output resistance are lower than those of the Hall element due to the structure of the conventional example. Further, the electron mobility measured in the device state was further improved by about 20% by the present invention. As a result, as shown in Table 1, the product sensitivity of the device was improved by approximately 1.2 to 1.4 times in proportion to the increase in mobility, and the effect of the present invention was clearly manifested. ing.

(Embodiment 2) InP as in Embodiment 1 above
Example 2 is a second example of the characteristics of the Hall element in the case where the number of GaInAs layers deposited is different, although the single crystal substrate is used. FIG. 3 is a diagram schematically showing a cross section of the heterojunction structure according to the second embodiment. In the figure (301), the specific resistance obtained by adding Fe used as the substrate is about 10 ⁷ Ω ・
cm high resistance InP single crystal substrate. The plane orientation is (100) as in the first embodiment, but as described above,
The specific resistance is not limited to this. This substrate (301) has a film thickness of about 100 nm and a carrier concentration of 2 ×
An undoped InP layer (302) of 10 ¹⁵ cm ^-3 was grown. Up to this point, the process is the same as in the first embodiment. After that, a Ga _0.42 In _0.58 As layer (303-1) having a mixed crystal ratio of 0.42 was grown over a thickness of about 20 nm. Next, a Ga of about 10 nm with a mixed crystal ratio of 0.44
_{The 0.44} In _0.56 As layer (303-2) was continuously formed with Ga _0.46 In _0.54 As having a mixed crystal ratio of 0.46 and a thickness of about 10 nm.
Layers (303-3) were sequentially deposited. Further, as the uppermost layer, Ga _0.47 In _0.53 having the mixed crystal ratio of 0.47 described in Example 1 was _used.
The As layer (303-4) was provided with the same film thickness and carrier concentration as in Example 1, and the InP layer (302) was changed to Ga.
_The mixed crystal ratio was gradually and continuously changed gradually until reaching the _0.47 In _0.53 As layer (303-4).

The outermost surface of the wafer having the above-mentioned heterostructure is subjected to desired processing by known photolithography method and etching method, and then the above-mentioned Au-Ge alloy is deposited by the vacuum deposition method. Was heat-treated to form ohmic input / output electrodes (304). The heat treatment conditions for ohmicizing the Au—Ge alloy are not limited to the temperature and time conditions described in this example.

Using this wafer as a base material, a hole element having a chip size of 350 μm was prepared. 50 mm diameter
Approximately 12,000 elements could be formed on the circular wafer of No. 3, but non-defective chips were selected from these and subjected to electrical characteristic evaluation. Table 2 lists the characteristic values of the non-defective Hall element having the heterostructure according to the second embodiment. In addition, the same table shows the characteristic values of the Hall element composed of the conventional simple heterojunction described above.

[0031]

[Table 2]

As can be clearly seen from the characteristic values listed in Table 2, the product sensitivity, which greatly affects the characteristics of the Hall element, is obviously improved by providing the heterojunction according to the present invention.

(Embodiment 3) In this embodiment, InP layer and G
An example will be described in which a Ga _x In _1-x As layer having a mixed crystal ratio continuously changed is formed in forming a heterojunction with the aInAs layer. FIG. 4 schematically shows a cross section of the structure.
(401) is a semi-insulating InP single crystal having a specific resistance of about 10 ⁷ Ω · cm, which is formed by adding Fe and is used as a substrate.
On the substrate (401), undoped I having a film thickness of about 100 nm
The nP layer P (402) was grown. Next, the InP layer (4
_{02) Ga x In 1-x} As layer of mixed crystal ratio in the growth direction until leading from 0.42 to 0.47 is continuously changed over (40
3-1) was deposited to a film thickness of about 400 nm. Then, Ga _0.47 In _0.53 As (403-2) having a mixed crystal ratio x of 0.47
Were grown under exactly the same conditions as in Example 1.

Ga _0.47 In _{0.53 was prepared} by the procedure described above.
On the As layer (403-2), ohmic input / output electrodes (4
04) was formed, a Hall element was prototyped, and the characteristics were compared with the Hall element according to the conventional example. As with the previous example, it is about 2
An improvement in electron mobility of 0% was observed, and as a result, the product sensitivity was improved by about 1.2 times as compared with the conventional Hall element. It should be noted that there was no significant difference in the main characteristics such that the input / output resistance was slightly reduced as compared with the conventional Hall element.

(Embodiment 4) FIG. 5 shows GaI according to the present invention.
An example of the typical top view of a nAs hall element is shown. FIG. 6 is a schematic view of a cross section taken along the broken line AA ′ of the Hall element shown in FIG. (101) of FIG. 6 is a semi-insulating InP single crystal having a plane orientation of (100), which is formed by adding iron (Fe) used as a substrate in forming the base material for the Hall element. The thickness of the substrate crystal is about 3
It was 50 μm. In this embodiment, the specific resistance is about 10 ⁷ Ω.
A cm crystal was used.

In the figure, (602) is a Ga _0.04 In _0.96 As layer with a mixed crystal ratio of 0.04 grown on the crystal substrate (101) by MOCVD method using C ₅ H ₅ In as an In source at atmospheric pressure. Is. The film thickness of this layer (602) was about 8 nm. The carrier concentration was ≦ 10 ¹⁶ cm ⁻³ . On the same layer (102), Ga _0.90 In _0.10 As with a mixed crystal ratio of 0.90 was formed.
(603) was deposited. When the carrier concentration in the same layer was determined by the Hall effect measurement method, it was ≦ 10 ¹⁵ cm ⁻³ . The film thickness was 9 nm. A laminated structure composed of these combinations was deposited for two cycles to form a laminated structure.

Next, on the Ga _0.90 In _0.10 As layer (603) which is the outermost surface of the laminated structure in the above case, n-type conduction having a mixed crystal ratio of 0.47 and a film thickness of about 400 nm is performed. Ga _0.47 In _0.53 As epitaxial layer (60
4) was provided by the atmospheric pressure MOCVD growth method described above. When the carrier concentration of this layer (604) was measured by the Hall effect method, it was 2.0 × 10 ¹⁶ cm ^-3 .

The wafer having such a structure was subjected to process processing such as mesa processing to obtain a Hall element by making full use of known photolithography method and etching method. After that, gold-germanium (A) containing about 13% by weight of germanium to form the input and output electrodes.
The u.Ge) alloy was vacuum-deposited, and then the above-mentioned wafer on which the electrode material was adhered was heat-treated at a temperature of 420 ° C. for a time of 3 minutes to form an ohmic electrode (605).

Next, the surface of the elementized wafer was coated with a SiO ₂ insulating film (606) by a usual plasma CVD method. The thickness of the SiO ₂ film (606) was about 300 nm. Next, in order to separate the electrode portion (605) and the Hall element individually, the SiO ₂ film (606) covering the portion corresponding to the dicing line (607) was removed with an inorganic acid. Further, in order to facilitate dicing, the back surface of the single crystal substrate (101) is etched with a hydrochloric acid aqueous solution, and a wafer formed with elements having an initial thickness of 350 μm is immersed in the same aqueous solution until the thickness becomes about 130 μm. I left it standing. After this back surface etching, dicing was performed along the dicing line (607) to form individual chips. The chip size was 350 μm × 350 μm, which is extremely common for Hall elements. Next, the chip was surrounded and surrounded by a general epoxy resin for surrounding. The maximum temperature required for the surrounding process is 190 ° C., and only in this embodiment, the surrounding temperature is not a unique temperature condition or process condition.

The Hall element produced as described above was subjected to electrical characteristic evaluation. Table 3 shows the evaluated items and characteristic values in comparison with the case of the present invention and the conventional example.
The above-mentioned laminated structure is not inserted in the conventional example, but GaInA manufactured by the same steps as above except the above
s Hall element. As shown in Table 3, between the new Hall element according to the present invention and the conventional Hall element, a significant difference was observed in the electron mobility at room temperature, and thus in the product sensitivity, demonstrating the superiority of the present invention. The present inventor diligently studied the cause of this difference, and from the result of analysis, it is shown that the magnitude of the fluctuation of the characteristic is the heat that the element is exposed to under a certain thermal environment as the Hall element becomes an element. It has been found that the degree of absorption of impact and thermal stress and the difference in ability largely depend on it, and in the case where the laminated structure according to the present invention is provided, the thermal stress is relaxed as compared with the structure found in the conventional example. It was interpreted that it was possible to suppress variations in device characteristics due to its excellent ability to operate.

[0041]

[Table 3]

[0042]

As described above, when GaInAs for heterojunction with InP is deposited, the mixed crystal ratio is specified to bring about the effect of remarkably improving the sensitivity of the Hall element, which is an extremely high-sensitivity hole which has never existed before. We can provide devices. In addition, according to the present invention, such high sensitivity can be realized, and thus the conventional lack of accuracy is said to be, for example, high-precision magnetic field measurement in a minute area, or precise rotation control of a rotating body. It will greatly contribute to the development of sensing technology in the industrial world by enabling

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a cross section of a heterojunction structure according to the present invention.

FIG. 2 is a diagram schematically showing a cross section of a conventional Hall element wafer.

FIG. 3 is a diagram schematically showing a cross section of a structure according to an example of the present invention.

FIG. 4 is a diagram schematically showing a cross section of a structure according to another embodiment of the present invention.

FIG. 5 is a schematic plan view of a Hall element according to another embodiment of the present invention.

6 is a schematic cross-sectional view of the structure of the Hall element of FIG.

[Explanation of symbols]

(101) ··· InP semi-insulating single crystal substrate (102) ··· InP epitaxial growth layer (103-1) ·· Ga _0.42 In _{0.58 with a} mixed crystal ratio of 0.42
As layer (103-2) ... Ga _0.47 In _{0.53 with} mixed crystal ratio 0.47
As layer (104) ··· Ohmic electrode (201) ··· Semi-insulating InP single crystal substrate (202) ··· InP epitaxial growth layer (203) ··· Ga _0.47 In _0.53 As layer (204) ) ··· Ohmic electrode (301) ··· Semi-insulating InP single crystal substrate (302) ··· InP epitaxial growth layer (303-1) · · Ga _0.42 In _{0.58 with a} mixed crystal ratio of 0.42
As layer (303-2) ... Ga _0.47 In _{0.53 with} mixed crystal ratio 0.47
As layer (303-3) ... Ga _0.46 In _{0.54 with a} mixed crystal ratio of 0.46
As layer (303-4) ... Ga _0.47 In _{0.53 with} mixed crystal ratio 0.47
As layer (304) ··· Au-Ge ohmic electrode (401) ··· InP semi-insulating single crystal substrate (402) ··· InP epitaxial growth layer (403-1) ··· Continuous mixed crystal ratio Changed GaI
nAs layer (403-2) ... Ga _0.47 In _{0.53 with a} mixed crystal ratio of 0.47
As layer (404) ··· Ohmic electrode (602) ··· Ga _0.04 In _{0.96 with a} mixed crystal ratio of 0.04
As layer (603) ... Ga _0.90 In _{0.10 with a} mixed crystal ratio of 0.90
As layer (604) ... Ga _0.47 In _{0.53 with a} mixed crystal ratio of 0.47
As layer (605) ... ohmic electrode (606) ... SiO ₂ insulating film (607) ... Dicing line layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryoichi Takeuchi 1505 Shimokagemori, Chichibu, Saitama Prefecture Showa Denko Co., Ltd. in Chichibu Factory (72) Inventor Masahiko Usuda 1505 Shimokagemori, Chichibu, Saitama Showa Denko Chichibu Factory (72) Inventor Keiichi Matsuzawa 1505 Shimokagemori, Chichibu City, Saitama Prefecture Showa Denko Chichibu Factory

Claims (3)

[Claims] 1. Indium phosphide and gallium indium arsenide (Ga _x I) on an indium phosphide (InP) substrate.
In a magnetoelectric conversion element having a heterojunction made of n _1-x As), the gallium arsenide / indium layer has a mixed crystal ratio x,
A magnetoelectric conversion element comprising a laminated structure of Ga _x In _1-x As and Gay _y In _1-y As different in y. 2. A mixed crystal ratio x with indium phosphide (InP).
There A magnetoelectric conversion element comprising comprises a heterojunction consisting of gallium arsenide, indium _{(Ga x In 1-x As} ) in the range of 0.57 or less 0.37 or more, Ga _x an In
_1-x As layer is composed of mixed crystal ratio x in each other having different multilayer laminate, and also in direct contact with the InP layer Ga _x an In
Magnetoelectric conversion element mixed crystal ratio of _1-x As layer is equal to or less than the mixed crystal ratio of other Ga _x In _1-x As layer constituting the Ga _x In _1-x As multilayer body. 3. A heterojunction made of indium phosphide (InP) and gallium indium arsenide (Ga _x In _1-x As) having a mixed crystal ratio x of 0.37 or more and 0.57 or less. In the magnetoelectric conversion element, the heterojunction is composed of a Ga _x In _1-x As layer and an InP layer in which the mixed crystal ratio x is continuously and gradually increased from the InP side. Conversion element.