JPH06237002A - Memory cell - Google Patents

Abstract

PURPOSE: To obtain a method for manufacturing EEPROM memory cells of dimensions of the order of submicrons. CONSTITUTION: A read only memory cell programmable and erasable electrically has a source junction excellent for providing a Fowler Nordheim tunneling enhanced at an erasing time. Cells are formed with an array on the surface of a semiconductor body 22, comprise sources and drains, and have channels under the floating gates 13 between the sources and the drains. Progressed sources 11 comprize diffusion regions 11B of inclined distribution formed by implanting arsenic As or antimony into the semiconductor body 22 from an inclined direction, and implanting phosphorus following that. The sources have heavily doped N<+> in the vicinities of the edges of laminated constructions of the floating gates 13/control gates 14, and have high field plate breakdown voltages.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to an electrically erasable and electrically programmable read only memory (EEPROM) having floating gate type memory cells. ) Is related to.

[0002]

EEPROMs of the type described herein utilize channel hot electron injection at the cell's drain-substrate junction for programming and Fowler-Nordheim at the source-substrate junction for erasing.
-Nordheim) tunneling is used to avoid excessive stress on the cell gate insulator. By separating the programming and erasing areas, each junction can be optimized independently.

Since channel hot electron injection is used on the drain side, the drain-substrate junction distribution should be steep for efficient programming.
Electrons are injected into the floating gate of the cell using the junction having this steep distribution. The floating gate turns the cell "off" or non-conducting when charged with electrons. For example, since the diffusion coefficient of arsenic is relatively smaller than that of phosphorus, a conventional steep junction is formed on the drain side by implanting arsenic.

A steeply distributed junction results in a relatively low junction breakdown voltage. In general, a low breakdown voltage is not a serious problem, since the programming voltage required on the drain side is lower than the steeply distributed low breakdown voltage. However, the low source side breakdown voltage is a serious limitation in erase. It is due to the nature of the Fowler-Nordheim tunneling mechanism. Erasing is accomplished by forcing electrons to move from the floating gate to the source via quantum mechanical tunneling. When the correct amount of electrons have moved, the floating gate is placed in an electrically neutral state, ie the cell is "on" or conducting.

The following conditions are required for effective erase to occur at the source-substrate junction: 1) There must be a high electric field across the gate insulator of the cell for electron tunneling to occur. I have to. 2) The source distribution must be graded for good junction breakdown voltage and to reduce leakage current during erase. 3) Adjacent to the floating gate end / control gate end, an appropriate N + region under the floating gate is depleted of surface charge and its N
It is necessary to avoid a voltage drop in the + region and to provide a maximum electric field across the gate insulator between the floating gate and the source region. 4) The N + region under this floating gate should have optimal implant dose and anneal drive for maximum electric field, but not excessive underlap.

The excess N + underlap strengthens the capacitive coupling between the source region and the floating gate, resulting in an effective reduction of the voltage drop between the floating gate and the source region, and thus of the electric field.

If the source-substrate junction breakdown voltage is lower than or about the same as the erase voltage, an undesired effect will occur. For example, "hot electrons" will be injected into the gate insulator of the cell. During junction breakdown, electron-hole pairs are generated in the depletion region of the junction, leading to large leakage currents. Some of these electron-hole pairs pass through the depletion region and are accelerated by the relatively high lateral electric field of the junction (which is responsible for the junction breakdown). These holes gain high energy (become "hot"). Some of these holes are swept into the gate insulator of the cell by the longitudinal electric field. Hot holes moving through the gate insulator are collected in the floating gate where they recombine with the electrons and neutralize the charge on the floating gate. Erase assisted by hot holes is undesirable. This is because some of the injected holes are trapped in the gate insulator, leading to deterioration in reliability. The deterioration includes consumption of the gate insulator (deterioration of device resistance), instability of the threshold voltage Vt, and current drive deterioration.

Further, a high threshold voltage Vt is required for each cell of the EEPROM having a one-transistor memory cell in the initial erased state (neutral floating gate state). This high initial threshold voltage Vt provides the cell with a sufficiently large margin from the overerased threshold voltage that the floating gate has a positive charge. Adjusting the cell threshold voltage to the required high value is commonly done by boron threshold adjustment implants.
The implantation of boron makes the source and drain junctions steeper, causing an undesired reduction in junction breakdown voltage. Therefore, the cell having the source-drain junction symmetrically formed of arsenic as described above is the most suitable for appropriately meeting the requirement of the high voltage necessary for electrically erasing the EEPROM. I can't say.

One conventional solution to the above problem is to introduce asymmetry in the source-drain junction by adding a phosphorus implant into the source. Because phosphorus has a large diffusion coefficient, it spreads out more than arsenic and underlaps under the cell floating gate, producing a more graded distribution of junctions with a higher breakdown voltage than a drain junction with arsenic alone. But this introduces problems.

One problem is that the introduction of phosphorus into the source junction creates a non-uniform surface boundary of the source junction under the floating gate. The concentration of arsenic is predominant in the portion of the source region just below the end of the floating gate. In the part of the source region that goes further below the floating gate, the phosphorus concentration is dominant. The respective surface concentrations of arsenic and phosphorus in these regions depend on the dose level of ion implantation and also on the time and temperature of the subsequent heat treatment step. Typically, the arsenic implant dose is about 5E15 (5 × 10 ¹⁵ ) ions / cm ² .
This dose, followed by the implant region anneal / drive at 900-1000 ° C., provides a stable junction to meet the memory cell transistor design requirements along with the surrounding transistors. The corresponding arsenic surface concentration is about 5E20 (5 × 10 ²⁰ ) atoms / cm ³ . The surface concentrations of arsenic and phosphorus are important because they affect band-to-band tunneling and cause the same problems introduced by hot-hole assisted erase.

Supplying a reverse bias to the N + junction (this
This is necessary for cell erase) is the silicon energy
Bend the gee-band above the equilibrium value in the depletion region.
It causes a cry. If the bend is silicon
If it is larger than the energy band gap, the triangle
A tunnel barrier is formed. Through this barrier, the electrons
Tunneling from the valence band of the source to the conduction band of the source
Done, leaving behind holes that are accelerated into the insulator
It will be. These holes are isolated from the breakdown that occurs during junction breakdown.
Caused by hot hole injection into the rim
It causes similar reliability issues. Between this band
Tunneling of at least the source junction under the floating gate
Also by guaranteeing a high surface concentration in the arsenic part
Can be reduced. This high surface concentration leaves the bonding area empty.
Prevent starvation. Traditional flash, typically
Thickness of 100 to 13 used for a dual-type EEPROM
About 5E19 for 0 angstrom cell insulator
(5 x 10¹⁹) Atom / cm ³Or higher surface concentration
Is required. As already mentioned, conventional high temperature and long
Arsenic implantation in a time annealing drive is
Make sure that the elementary parts do not contribute to tunneling between the bands.
Provides the concentration needed to prove.

When manufacturing integrated circuits of dimensions less than 1 micron, high temperatures and long thermal processes are undesirable because they adversely affect the operation of peripheral logic circuit transistors. For example, the phosphorus portion of the surface diffuses sufficiently far under the floating gate by a high temperature and long time thermal process, and has a bad influence such that a short channel effect appears in the device. The source junction also diffuses deep enough that there is a risk of punch-through from the source to the drain. The manufacturing process should be performed at low temperatures and short times to limit the spread of the arsenic / phosphorus combination N + region under the floating gate.

What is needed is a structure and method that overcomes the above problems.

[0014]

SUMMARY OF THE INVENTION In accordance with one embodiment of the present invention, an EEPROM memory cell that undergoes enhanced Fowler-Nordheim tunneling during erase is described. The source region includes a tilt angle diffusion region formed by implanting arsenic or antimony from the tilted direction. The tilt angle diffusion region is generally surrounded by a diffusion region formed by implanting phosphorus. The source-substrate junction near the edge of the tunneling window is formed by implanting arsenic or antimony. The source-substrate junction extends far below the gate by phosphorous implantation.

Implantation from a tilted direction causes arsenic or antimony ions (atoms) to enter laterally under the floating gate a much larger distance than the entry of ions by a standard vertical implant. (Ions become atoms when they reach the substrate.) The graded diffusion region formed by the implantation from the inclined direction provides an area of high surface concentration under the floating gate, which is enhanced by the Fowler enhanced as described above. -Necessary for Northeim tunneling and also for reducing band-to-band tunneling. The requirement for high junction breakdown voltage is met by a second (phosphorus) implant. During the subsequent thermal cycle, the implanted phosphorus diffused sufficiently,
It forms a graded source junction and thus increases the breakdown voltage of the junction.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a prior art example circuit for a memory cell array is shown as part of an integrated circuit of a memory chip for purposes of illustrating the application of the present invention.
Each cell has a source 11, a drain 12, a floating gate 13,
A floating gate transistor 10 having a control gate 14 is provided.

Each of the control gates 14 in one row of cells 10 is connected to a word line 15 and word line 15
Are connected to the word line decoder 16.
Each of the sources in one row of cells 10 is source line 1
It is connected to 7. Each of the drains 12 in one column of cells 10 is connected to a drain column line 18.
Each source line 17 is connected to a column decoder 19 by a column line 17a, and each drain column line 18 is connected to a column decoder 19.

In the write or program mode, the word line decoder 16 responds to the word line address signal on line 20r and the signal from the read / write / erase control circuit 21 (or microprocessor 21) to select the selected control. It serves to provide a preselected first programming voltage Vrw (about +12 volts) on a selected wordline 15 including gate conductor 14. The column decoder 19 also functions to provide a second program voltage Vpp (about +5 to +10 volts) on the selected drain column line 18, and thus on the drain 12 of the selected cell 10. The source line 17 is connected to the reference potential Vss. All the drain column lines 18 which are not selected have the reference potential Vs.
s is connected. These program voltages produce high current (drain 12 to source 11) states in the channel of the selected memory cell 10, resulting in channel hot electrons and avalanche breakdown electrons near the drain-channel junction, which Is implanted across the channel oxide into the floating gate 13 of the selected cell 10. The programming time is chosen long enough to program the floating gate 13 with a negative program charge of about -2 to -6 volts for the channel region. For a memory cell 10 made in accordance with the preferred embodiment of the present invention, the coupling coefficient between the control gate 14 / word line 15 and the floating gate 13 is about 0.5 to 0.6. Therefore,
Selected word line 1 including selected control gate 14
The program voltage Vrw of 5, for example, 12 volts is
A voltage of approximately +5 to +7 volts is provided on the selected floating gate 13. The floating gate 13 of the selected cell 10 is charged by channel hot electrons during programming, which electron then de-conducts the source-drain path under the floating gate 13 of the selected cell 10, the state of which is It is read as a "0" bit. The cells 10 that have not been selected have their source-drain paths under the floating gate 13 left conductive, and those cells 10 are read as "1" bits.

In the flash erase mode, the column decoder 1
9 functions to leave all drain column lines 18 floating. The word line decoder 16 functions to connect all the word lines 15 to the reference potential Vss. The column decoder 19 also functions to supply all source lines 17 with a high positive voltage Vee (about +10 to +15 volts). These erase voltages create a sufficient electric field intensity between the floating gate 13 and the source 11 across the tunnel area, and transfer a charge from the floating gate 13 to generate a Fowler-Nordheim tunnel current that erases the memory cell 10. Let Since the potential on word line 15 is 0 volts, cell 10 remains non-conductive during erase and thus no channel hot carriers are generated. The field plate breakdown voltage at the source 11 junction is made high enough to inhibit hot carrier injection. A high field plate breakdown voltage at the source 11 junction can be achieved by the present invention. It will be described later.

In the read mode, the word line decoder 16 responds to the word line address signal on the line 20r and the signal from the read / write / erase control circuit 21 to select a preselected positive line for the selected word line 15. Voltage Vcc (approx. +5 V) of the low voltage (ground potential or V
ss). The column decoder 19 functions to provide a preselected positive voltage Vsen (about +1.0 volt) to at least the selected drain column line 18 and a low voltage (0 volt) to the source line 17. The column decoder 19 also functions in response to the signal on the address line 20d to connect the selected drain column line 18 of the selected cell 10 to the data output terminal. Cell 1 connected to selected drain column line 18
The conductive or non-conductive state of 0 is transferred to the DATA OUT terminal. The read voltage provided to the memory array is sufficient to determine the channel impedance for the selected cell 10, but does not disturb the charge state of any floating gate 13 such as hot carrier injection or Fowler-Nordheim tunneling. Is not enough to cause.

For convenience, Table 1 shows a table of read, write, and erase voltages as follows:

[Table 1]

The high concentration N + surface area under the floating gate 13 is necessary to minimize hot carrier assisted erase. Arsenic implantation from a tilted direction is advantageous in several respects: 1) N + underlap with a tilted implantation reduces the time of high temperature processing compared to standard vertical implantation. Reducing the high temperature processing time reduces short channel effects in the cell 10 and peripheral logic circuit transistors. 2) The required N + surface region concentration on the order of 5E19 (5 × 10 ¹⁹ ) atoms / cm ³ or more can be achieved, so that no significant voltage drop occurs across source 11 during erase. This increases the electric field in the gate oxide 30 between the source 11 and the floating gate 13.
Thus, the Fowler-Nordheim tunneling assisted erasure is enhanced by the source 11 by arsenic implantation from the tilted direction.

The amount of diffusion of N + dopant under the gate depends on the implantation angle, the implantation dose, and the implantation energy. A simulated example of the effect of these process parameters on the N + junction distribution is shown in FIG.
And in FIGS. 6-9. 3 to 5 and 7 to 9
Show that proper selection of the graded arsenic implant dose, implant energy, and implant angle facilitates the N + region underlap compared to the prior art FIGS. 2 and 6 underlaps. In these figures, the distribution of implanted and diffused arsenic regions is 1E20 (1 × 10 ²⁰ ) per cubic centimeter and 1E19.
(1 × 10 ¹⁹ ), 1E18 (1 × 10 ¹⁸ ), 1E17
It is shown for each case of (1 × 10 ¹⁷ ) and 1E16 (1 × 10 ¹⁶ ) atoms.

The optimization of the junction breakdown voltage in the source 11 is done by implanting phosphorus, which can be from vertical or at a tilt angle. The results of the computer simulations using the phosphorus implantation from the vertical direction and the arsenic implantation from the vertical direction and the inclined direction are shown in FIGS. 2 to 5 and 6 to 9, respectively. These examples are 70k
Doping with arsenic at a dose of 5E15 ions / cm ² at an energy of eV and 4E14 ions / at 140 keV
cm ² phosphorus doping is shown. 2-5 and 6-
As shown in FIG. 9, the arsenic isoconcentration curve shows the region 11A.
, The isoconcentration curve of phosphorus shapes region 11B, and regions 11A and 11B form a sloping source-substrate junction with respect to sources 11A, 11B.

A prior art implant simulation using a prior art vertical arsenic implant 11A followed by a conventional vertical phosphorus implant 11B is shown in FIGS. 2 and 6, the ratio of the underlap distance of arsenic implantation to the depth distance is 1E.
0.4 for both low drive (ie 900 ° C. for 35 minutes) and medium drive (ie 1000 ° C. for 10 minutes) for a 20 atom / cm ³ arsenic concentration distribution.
It is the following. Similarly, the ratio of underlap distance to depth distance for an arsenic concentration distribution of 1E19 atoms / cm ³ is 0.
It is 6 or less.

In the simulation results of FIGS. 3-5 and 7-9, the ratio of the underlap distance of the arsenic implantation 11A to the depth distance is 1E20 atoms / cm ^{3 for} the concentration distribution.
Greater than 0.4 for both low and medium drives. These ratios are, for example, about 0.5-0.6 at a driving angle of 15 ° and about 0.8-at a driving angle of 60 °.
It is in the range of 1.0. Similarly, for the arsenic concentration distribution of 1E19 atoms / cm ³ , the ratio of the underlap distance to the depth distance is larger than 0.6 in both low drive and medium drive. Their ratio is, for example, 15 °
About the driving angle of about 0.65-0.75, 60 °
The driving angle is about 0.9-1.0.

For a method of making the device of FIGS. 3-5 and 7-9, FIGS. 10, 11A-11D,
Then, description will be made with reference to FIGS. 12A to 12G. The starting material is a slice of p-type silicon, the substrate 22 of which is only a small part. The slices are probably about 15 centimeters (6 inches) in diameter and the individual memory cells 10 are only a few microns wide and a few microns long.
Multiple process steps are typically performed to fabricate the transistors around the memory array, which are not described here. For example, an EEPROM memory device is a complementary field effect (CMOS) device that has N-wells and P-wells formed in a substrate 22 as part of a prior process for making peripheral transistors.

As shown in FIGS. 11A and 12A, a pad oxide layer 23 about 400 angstroms thick is grown or deposited on the surface of the substrate 22. This pad oxide layer protects the substrate 11 during the initial fabrication process and will be removed later. Next, low pressure CVD (low pressure chemica
A silicon nitride layer 24 is deposited over the pad oxide layer 23 using a vapor deposition method. This silicon nitride layer 24 is then patterned and plasma etched to expose areas where thick cell isolation field insulators 25 are to be formed.

About 7E12 ions / cm 2 to form the P + channel stop region 26 separating the memory cells.
A dose of ² boron implants is made. After removal of the photoresist layer, the thick field oxide forming thick field insulator 25 of the cell isolation, as shown in FIG. 11A, was exposed to steam at 1 atmosphere pressure at about 900 ° C. for about 6000 hours. Thermally grown to a thickness of -10000 Å with a local oxidation step. Alternatively, high pressure oxidation (HIPOX) can be used to shorten the oxidation time. As is well known, oxide grows underneath the edges of the silicon-nitride layer, forming "bird's beak" areas instead of sharp transitions.

11B-FIG. 11C and FIG. 12B-
Referring to FIG. 12C, the remaining portions of silicon nitride and pad oxide layers are removed. This process is performed on the silicon substrate 22 between the thick field insulators 25 for cell separation.
Expose. An implant is then performed to set the cell threshold voltage Vt. A high quality gate oxide 30 is then thermally grown after resist removal and after pre-gate cleaning. A process is performed to form floating gate conductor 13 by depositing a layer of first level polycrystalline silicon 28a over the surface of substrate 22. This first level polycrystalline silicon layer 28
a is deposited to a thickness of about 1500-3000 Angstroms. Layer 28a is N-type doped to make it conductive and de-glaze if necessary.
ze) will be done.

Next, a resist layer is formed on the substrate, followed by patterning, etching, resist removal, and cleaning of polycrystalline silicon. An intermediate level insulator layer 27, such as oxide / nitride / oxide (ONO), corresponding to an equivalent oxide (dielectric) thickness of 200-400 Angstroms, is formed on the first level polycrystalline silicon layer 28a. Formed by conventional methods. About 200
A second level polycrystalline silicon layer 28b, 0-4500 angstroms thick, is formed over the intermediate level insulator layer 27, which is N + doped and deglaze to render it conductive. Additionally and using well-known methods, the surface of the polycrystalline silicon is then covered 250.
A 0 Å thick layer of tungsten silicide (WSi 2) film 29 is deposited and then heat treated at 900 ° C. to 1000 ° C. in an annealing atmosphere for speed improvement.

Next, a stack etching process is performed as shown in FIGS. 11D and 12D to perform floating gate 13 and control gate 14 for each memory cell 10.
And are formed. Second level polycrystalline silicon layer 28
b, intermediate level insulator 27, and photoresist (not shown) is applied to define the stack structure of floating gate 13 and control gate 14 including first level polycrystalline silicon layer 28a. The control gate 14 is capacitively coupled to the corresponding lower floating gate 13 through a corresponding portion of the intermediate level insulator 27. The channel Ch formed by the laminated etching is shaped into a predetermined length, and the first and second laminated etching is performed.
The level polysilicon layer 28a, 28b is the source 11
It will be used later in the fabrication process as an implant mask to establish the length of the channel region between the drain and the drain 12.
In this way the channel junction can be tailored to optimize programming efficiency in the drain region 12 and to optimize erase efficiency in the source region 11.

Referring now to FIG. 12E, source region 1
The 1A distribution is formed by implanting arsenic from a tilted direction using a single photoresist processing step. Photoresist (not shown) is attached,
The source region is defined prior to implantation, thereby protecting the drain region 12 from implantation. Arsenic implantation has an energy of about 60 to 120 keV from a direction inclined by 15 to 75 degrees with respect to the vertical direction, about 1E1.
Performed at a dose of 5 to 5E15 ions / cm ² ,
N + source region 1 self-aligned below channel region
Form 1A. The tilt angle is an important process for N + underlap under the floating gate 13. Without the tilted implant 11A, a high temperature process is required to properly diffuse the N + dopant under the gate; however, the high temperature process is not compatible with the submicron MOS process.

Referring to FIG. 12F, the arsenic implant 11A from the tilted direction is followed by a lightly doped (N).
-) Phosphorus junction distribution implantation 11B is executed. This implantation is performed from a vertical or tilted direction with an energy in the range of about 80 to 170 keV and a dose of about 1E14 to 1E15 ions / cm ² . Subsequent to source implants 11A and 11B, resist removal, and proper cleaning, substrate 22 is exposed to an annealing atmosphere at 850.
To 1000 ° C. Additionally, before the N- (phosphorus) is implanted, the process is appropriately modified to N
Annealing of + arsenic implantation may be performed. Since phosphorus has a large diffusion coefficient, phosphorus diffuses more outward than arsenic, and thus this implant tunes the source-channel junction to a more graded junction distribution. The double implant causes the source region 11A to have an N + / N- distribution under the floating gate 13, which allows this junction to have a relatively higher breakdown voltage.

The drain 12 junction is formed after the formation of the source 11A, 11B junction. A photoresist layer is defined, exposing both the sources 11A, 11B and the drain 12 for implantation.

FIG. 12G shows a high dose, low energy standard arsenic source / drain implant after a shallow yet sharp drain 12 junction that facilitates hot carrier injection for efficient programming. , Show essential features of the completed memory cell 10. Arsenic implant (50-90 keV, about 1) used for both source 11A, 11B and drain 12 regions.
E15 to 5E15 ions / cm ² ) make the drain-channel junction have a steeper junction distribution.

In the above manufacturing process, antimony can be used instead of arsenic or in combination with arsenic.

After this step, the peripheral logic CMOS device is completed. To improve data retention, both sides and the top side of the stack have oxide layers 31 after this process.
Can also be grown or deposited. A borophosphosilicate glass (BPSG) layer (not shown) is then deposited over the slice surface. Following BPSG deposition, the substrate is again heated in an annealing atmosphere to 850-900 ° C. to densify the BPSG, recover the implant damage, and drive further junction distribution. A contact that is out of the array, along with a contact in the array
It is formed through the PSG layer. The contacts in the array are periodically formed in the y direction from the metal bit lines to the corresponding diffusion regions. Metal bit line is BPSG
It is formed on the layer, overcoming it and parallel to the diffusion region. This is done after the protective coating.

Depending on the design requirements of a particular device, different combinations of anneal temperature and anneal time for arsenic and phosphorus implants and / or different combinations of implant / anneal process sequences are used. For example, the anneal step described above could be replaced by a single high temperature step following BPSG deposition.

Although the present invention has been described in relation to particular embodiments, this description is not meant to be limiting. It will be apparent to those skilled in the art, after having read this specification, that various modifications to the embodiments cited herein, as well as alternative embodiments of the invention, are possible. As mentioned above, various combinations of arsenic, antimony, and phosphorus implanting and / or annealing steps can be used to optimize the source junction characteristics. Therefore, the claims of the present invention should be construed as including those modifications and embodiments as being within the scope of the present invention.

With respect to the above description, the following items will be further disclosed. (1) a floating gate, a control gate electrically insulated from the floating gate, a substrate having a surface, a channel region in the substrate below the floating gate and insulated from the floating gate, and in the substrate. A memory cell of a type having a source and a drain located at opposite ends of the channel region, the source having a concentration distribution of 1E20 atom / cm ³ of one of: arsenic or antimony. A diffusion region under the floating gate that is underlapped by a distance greater than 40 percent of the depth of the concentration distribution.

(2) The memory cell according to item 1,
A memory cell in which the source comprises phosphorus.

(3) The memory cell according to item 1,
A memory cell in which the channel region comprises boron.

(4) Floating gate, control gate electrically isolated from the floating gate, substrate having a surface, channel region in the substrate underneath the floating gate and insulated therefrom, and the substrate A source and a drain located at opposite ends of the channel region,
A memory cell of the type having: 1E20 atoms / cm ^{3 of} one of: Arsenic or Antimony.
A diffusion region with a sloped distribution having a concentration distribution of
A memory cell including a diffusion region under the floating gate, the diffusion region being underlapped by a distance greater than 50 percent of the depth of the concentration distribution.

(5) The memory cell according to item 4,
A memory cell in which the source comprises phosphorus.

(6) The memory cell according to item 4,
A memory cell in which the channel region comprises boron.

(7) Floating gate, control gate electrically insulated from the floating gate, substrate having a surface, channel region in the substrate below and insulated from the floating gate, and the substrate A source and a drain located at opposite ends of the channel region,
Wherein the source in the substrate is an inclined diffusion region having a concentration distribution of 1E20 atoms / cm ³ , and the depth of the diffusion region is below the floating gate. A diffusion region underlapped by a distance greater than half the length, the graded diffusion region including one of arsenic and antimony, the source including phosphorus, and the channel region. A memory cell containing boron.

(8) A method of manufacturing a non-volatile memory cell on the surface of a semiconductor substrate of the first conductivity type, wherein a first conductive thin wire having a gate insulator on the lower side is formed on the substrate. Forming, forming an intermediate level insulator layer on the substrate surface and the first conductive thin line, forming a second conductive layer on the intermediate level insulator layer, and forming a second conductive layer on the intermediate conductive layer.
A conductive layer, the intermediate level insulator layer, and the first
Defining a control gate / floating gate stack structure, the stack structure having edges that are essentially perpendicular to the surface. Selectively implanting at least one dopant of a shape to form a graded distribution diffusion region at the edge of the stack, the at least one dopant being relative to the edge of the stack. Forming at an angle.

(9) The method according to the eighth item, wherein the gradient distribution diffusion region extends into the substrate under the floating gate.

(10) The method according to item 8, wherein the gradient distribution diffusion region extends downward into the substrate by a first distance, and the gradient distribution diffusion region has 1E20 atoms /
The method wherein the concentration distribution in cm ³ extends laterally below the floating gate by a second distance, the second distance being at least 50 percent of the first distance.

(11) The method described in the eighth item, wherein the at least one dopant is arsenic.

(12) A method according to item 8, wherein the at least one dopant is antimony.

(13) The method according to the eighth item, wherein a phosphorus dopant is implanted into the substrate after the laminated structure is formed.

(14) The method according to item 8, wherein after the laminated structure is formed, a phosphorus dopant is implanted into the substrate at an angle with respect to the end of the laminated structure.

(15) The method described in the eighth item, wherein boron is implanted into the substrate prior to forming the first conductive layer.

(16) The method described in the eighth item, wherein the angle with respect to the edge of the laminated structure is in the range of 15 to 75 degrees.

(17) The electrically erasable and electrically programmable read-only memory cell 10 has a superior source junction 11 to provide enhanced Fowler-Nordheim tunneling during erase. The cell 10 is formed in an array on the surface of the semiconductor body 22, includes a source 11 and a drain 12, and has a channel below the floating gate 13 between the source 11 and the drain 12. The advanced source 11 includes a graded diffusion region 11B formed by implanting arsenic As or antimony from a tilted direction into the semiconductor body 22, followed by phosphorus. Source 11 is floating gate 1
3 / High concentration N + near the edge of the laminated structure of the control gate 14.
It has a region and a high field plate breakdown voltage.

Attention Copyright Texas Instruments Incorporated 1992. Portions of the document in this patent are subject to copyright protection. Texas Instruments, Inc. makes no sense for the patents issued or any copy of those documents in the patent files of the patents and trademark offices related to the issued patents. All other copyright rights are reserved.

[Brief description of drawings]

FIG. 1 is a partial block diagram of an electric circuit diagram of a conventional memory cell array.

FIG. 2 shows a prior art simulated doping profile and a standard phosphorus implant simulated doping profile after a low drive (eg, 900 ° C. for 35 minutes) temperature / time cycle for vertical arsenic implants. FIG. 11 is an enlarged cross-sectional view of a small portion of a memory cell taken along line AA ′ of FIG.

FIG. 3 is a view similar to FIG. 2 when arsenic is implanted at an angle inclined by 15 ° from the vertical.

FIG. 4 is a view similar to FIG. 2 in the case of implanting arsenic at an angle inclined by 30 ° from the vertical.

FIG. 5 is a view similar to FIG. 2 when arsenic is implanted at an angle of inclination of 60 ° from the vertical.

FIG. 6 shows a prior art simulated doping profile and a standard phosphorus implant doping profile after a medium drive (eg, 1000 ° C. for 10 minutes) temperature / time cycle for vertical arsenic implants. ,
FIG. 11 is an enlarged cross-sectional view of a small portion of the memory cell taken along the line AA ′ of FIG. 10.

FIG. 7 is a view similar to FIG. 6 when arsenic is implanted at an angle inclined by 15 ° from the vertical.

FIG. 8 is a view similar to FIG. 6 when arsenic is implanted at an angle inclined by 30 ° from the vertical.

FIG. 9 is a view similar to FIG. 6 when arsenic is implanted at an angle of inclination of 60 ° from the vertical.

FIG. 10 is an enlarged plan view of a small portion of the memory cell array.

FIG. 11: Line B of FIG. 10, showing various stages of manufacture
-B 'is an enlarged cross-sectional view of a small portion of the memory cell array taken along B'.

FIG. 12: Line A of FIG. 10 showing various stages of manufacture
-A 'is an enlarged cross-sectional view of a small portion of the memory cell array taken along A'.

[Explanation of symbols]

10 floating gate transistor 11 source 11A, 11B source region 12 drain 13 floating gate 14 control gate 15 word line 16 word line decoder 17 source line 17a column line 18 drain column line 19 column decoder 20r word line address signal line 20d address line 21 read / Program / erase control circuit (microprocessor) 22 Substrate 23 Pad oxide layer 24 Silicon nitride layer 25 Field insulator 26 Channel stop region 27 Intermediate level insulator layer 28a First level polycrystalline silicon layer 28b Second level polycrystalline Silicon layer 29 Tungsten silicide layer 30 Gate oxide 31 Oxide layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location G11C 16/04

Claims (2)

[Claims] 1. A floating gate, a control gate electrically insulated from the floating gate, a substrate having a surface, a channel region in the substrate below and insulated from the floating gate, and in the substrate. A memory cell of the type having a source and a drain located at opposite ends of the channel region, wherein the source has a concentration distribution of 1E20 atom / cm ³ of one of: arsenic or antimony. A diffusion region having a distributed distribution, the diffusion region being underlapped below the floating gate by a distance greater than 40 percent of the depth of the concentration distribution. 2. A method of making a non-volatile memory cell on the surface of a first conductivity type semiconductor substrate, the method comprising: forming on the substrate a first conductive wire with a gate insulator underneath. Forming an intermediate level insulator layer on the substrate surface and the first conductive thin wire; forming a second conductive layer on the intermediate level insulator layer; A layer, the intermediate level insulator layer, and the first conductive wire to etch the control gate /
Defining a stack of floating gates, wherein the stack has an edge that is essentially perpendicular to the surface; selectively implanting at least one dopant of a second conductivity type; Forming a diffusion region having a tilted distribution at the edge of the laminated structure, the at least one dopant being formed at an angle to the edge of the laminated structure. Including the method.