JPH06236836A - Circuit pattern - Google Patents

Abstract

(57) [Summary] [Object] To reliably form a pattern formed on a semiconductor substrate by exposure with a reduction projection exposure apparatus using modified illumination by obtaining a large DOF during exposure. [Structure] By extending a dummy pattern 24 to a pattern 17 required for a circuit, a large pitch dimension is eliminated and a uniform small pitch dimension is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern layout when forming a pattern on a semiconductor device.

[0002]

2. Description of the Related Art FIG. 6 is a conceptual view of a reduction projection exposure apparatus used when forming a pattern on a semiconductor device. In the figure, 1 is a light source, 2 is a fly-eye lens, 3 is an aperture setting position, 4 is a condenser lens, 5 is a reticle, 6 is a projection lens, 7 is a substrate to be processed, 8 is a photoresist on the substrate to be processed 7. It is a film, and the position of the photoresist film 8 is optically related to the aperture position 3 by a Fourier transform plane. FIG. 7 is a plan view showing the aperture under normal illumination. Reference numeral 9 is a light transmitting portion, and 10 is a shielding portion.
Exposure is performed by attaching this aperture to the aperture position 3 of the reduction projection exposure apparatus. FIG. 11 is a graph showing the DOF (depth of focus) of the reduction projection exposure apparatus, and 11 is the DOF when the aperture of normal illumination shown in FIG. 7 is used.
It is a curve. As shown in FIG. 11, when exposure is performed using normal illumination, the smaller pattern pitch dimension is DOF.
Also becomes smaller. Therefore, formation of a pattern having a fine pitch dimension is easily affected by a step on the semiconductor substrate because the DOF is small, and it is difficult to form a pattern having a large step.

For this reason, in recent years, an exposure method using modified illumination in a reduction projection exposure apparatus has been performed so as to cope with the formation of a fine pattern having a pitch dimension. The modified illumination will be described below. FIG. 8 is a plan view showing an aperture of the modified illumination in which the translucent portion is divided into four parts, and FIG. 9 is a plan view showing the aperture of the annular illumination of the modified illumination.
In the figure, 12 is a translucent part, and 13 is a shielding part. The modified illumination is constructed by attaching such an aperture to the aperture position 3 of the reduction projection exposure apparatus shown in FIG.
In addition, the light intensity distribution at the aperture position 3 is shown in FIG. 1 without using the apertures as shown in FIGS.
There is also a method of changing as shown in 0. In FIG. 10, 14
Is a portion where the light intensity is strong, and 15 is a portion where the light intensity is weak. In FIG. 11, which is a graph showing the DOF of the reduction projection exposure apparatus, 16 is the DOF curve when the aperture of the modified illumination shown in FIG. 8 is used. As shown in the figure,
The DOF curve 16 for modified illumination is D when the pitch dimension of the pattern is smaller than the DOF curve 11 for normal illumination.
When the OF becomes large and the pitch becomes large, the DO becomes large.
F becomes small. Further, the DOF curve shows the same tendency in modified illumination other than the case of using the aperture shown in FIG. As described above, in the modified illumination, a pattern having a small pitch dimension can be formed more reliably than in the normal illumination, which is effective in the recent trend toward miniaturization.

[0004]

By the way, in the conventional circuit pattern, there is a pattern in which a large pitch dimension and a small pitch dimension are mixed. 12 to 14 show examples of conventional circuit patterns on a semiconductor substrate, FIGS. 12, 13 and 14 (a) are plan views, and FIG. 14 (b) is FIG. 14 (a). FIG. In FIG. 12, 17 is a pattern on the semiconductor substrate,
Reference numeral 18 is an area in which the patterns 17 are arranged at a constant small pattern pitch, and 19 is an area in which a pattern pitch portion larger than the constant pattern pitch exists. These areas are exposed at the same time when the pattern is formed.
In the modified illumination, the DOF becomes small in a large pattern pitch portion, and it is difficult to form a pattern particularly on a substrate having a large step.

Further, in the example shown in FIG. 13, patterns are continuously arranged at a constant small pattern pitch, but 20 is an end pattern. Also in this case, in the modified illumination, the DOF in the end pattern 20 was considerably smaller than other continuous patterns, and it was difficult to form the pattern. Further, in the example shown in FIG. 14, 21 is a pattern arranged at a constant small pattern pitch, and 22 is a pattern 2.
The pattern 23 is thicker than the reference numeral 1, and 23 is a semiconductor substrate. Also in this case, in the modified illumination, the DOF in the thick pattern 22 and the pattern adjacent to it becomes small, and it is difficult to form the pattern as in the case shown in FIG.

As described above, in the conventional circuit pattern, when the pattern is formed by the reduction projection exposure apparatus using the modified illumination capable of exposing the pattern of the small pitch size, the pattern of the large pitch size is mixed. , DOF is insufficient, and accurate pattern formation cannot be performed. This tendency is particularly remarkable on a substrate having a large step.

The present invention has been made to solve the above problems, and when a semiconductor substrate is exposed by a projection exposure apparatus using modified illumination, a sufficient DOF can be obtained and pattern formation can be reliably performed. The purpose is to provide such a circuit pattern.

[0008]

[Means for Solving the Problems] Claim 1 according to the present invention
The circuit pattern described is a dummy pattern other than the pattern required for the circuit extended to the pattern required for the circuit,
Alternatively, by disposing them separately, the continuity of a certain pattern pitch is enhanced.

A circuit pattern according to a second aspect of the present invention is a linear pattern arranged at a predetermined interval,
By using a pattern of a connecting portion that partially connects these linear patterns as a substitute for a pattern thicker than the linear patterns of other portions, continuity of a certain pattern pitch is enhanced.

[0010]

In the circuit pattern of the present invention, the continuity of a fixed pattern pitch is enhanced by disposing a dummy pattern. Therefore, it is possible to eliminate a portion having a large pattern pitch in which a DOF in modified illumination is small in a portion required for a circuit, and a pattern required for a circuit can be exposed with a large DOF and can be reliably formed.

Further, since the pattern of the connecting portion is provided and the adjacent linear patterns are connected to substitute for the thick pattern, the thick pattern can be eliminated and the pattern can be surely formed with a large DOF pattern pitch.

[0012]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a plan view showing a circuit pattern according to a first embodiment of the present invention, which is an improvement of the circuit pattern of the conventional example shown in FIG. As shown in FIG. 1, by extending the dummy pattern 24 to the pattern 17 required for the circuit, the entire pattern is unified into a small pattern pitch. As a result, the DOF in the modified illumination becomes large over the entire pattern, and the pattern formation is ensured. Although some of the dummy patterns are left as the patterns of the semiconductor device in the end, some of the dummy patterns are not left like the mask pattern of ion implantation. In any case, the dummy pattern is
The formation is made so that the semiconductor device is not functionally adversely affected.

Example 2. 2 is a plan view showing a circuit pattern according to a second embodiment of the present invention, which is an improvement of the conventional example shown in FIG. 12 as in the first embodiment. Figure 2
Since the dummy pattern 25 is arranged separately from the pattern 17 required for the circuit as shown in FIG. 3 and the pattern pitch is unified, a large DOF can be obtained. Since the dummy pattern 25 is not necessary in the circuit but is additionally formed to unify the pattern pitch, it is desirable that the influence on the circuit is as small as possible. In this respect, this Embodiment 2
Then, the dummy pattern 25 is the pattern 17 necessary for the circuit.
Since they are electrically isolated from each other, the influence on the circuit is reduced accordingly.

Example 3. FIG. 3 is a plan view showing a circuit pattern according to a third embodiment of the present invention, which is an improvement of the conventional example shown in FIG. 12 as in the above embodiment. As shown in FIG. 3, a large dummy pattern 26 is provided separately from the pattern 17 necessary for the circuit. Dummy pattern 26
DOF becomes large at the end of the pattern 17 necessary for the circuit adjacent to the
Exposure at F becomes possible.

Example 4. FIG. 4 shows a circuit pattern according to a fourth embodiment of the present invention, which is an improvement of the conventional example shown in FIG. As shown in FIG. 4, next to the pattern 20 at the end of the continuous pattern having a constant small pattern pitch, linear dummy patterns 27 are continuously arranged at the same pattern pitch. As a result, the DOF in the end pattern 20 necessary for the circuit is restored, and the end pattern can be reliably formed.

Example 5. FIG. 5 shows a circuit pattern according to a fifth embodiment of the present invention, which is an improvement of the conventional example shown in FIG. FIG. 5A is a plan view showing a pattern 28 of connection parts provided on the same layer and adjacent patterns 29 are connected to each other.
Thus, the thick pattern 21 shown in FIG. 14 can be used as a substitute, and the DOF can be increased and the pattern pitch can be made smaller. Further, FIG. 5B is a cross-sectional view showing a pattern 30 of connection portions provided on different layers and adjacent patterns 29 are connected to each other.
0 can be substituted for the thick pattern 21 shown in FIG. 14, and the same effect can be obtained.

[0017]

As described above, according to the present invention, by providing the dummy pattern and the pattern of the connecting portion,
It is possible to make uniform a small pattern pitch, and a large DOF can be obtained at the time of exposure using modified illumination. Therefore, a certain level difference on the semiconductor substrate can be dealt with, and reliable pattern formation can be performed. Also, modified illumination that can expose patterns with small pitch dimensions can be effectively used.

[Brief description of drawings]

FIG. 1 is a plan view showing a circuit pattern according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a circuit pattern according to a second embodiment of the present invention.

FIG. 3 is a plan view showing a circuit pattern according to a third embodiment of the present invention.

FIG. 4 is a plan view showing a circuit pattern according to a fourth embodiment of the present invention.

5A and 5B are a plan view and a sectional view showing a circuit pattern according to a fifth embodiment of the present invention.

FIG. 6 is a conceptual diagram showing a configuration of a reduction projection exposure apparatus.

FIG. 7 is a plan view showing an aperture under normal illumination.

FIG. 8 is a plan view showing an example of an aperture in modified illumination.

FIG. 9 is a plan view showing an example of an aperture in modified illumination.

FIG. 10 is a diagram showing a light intensity distribution at an aperture position.

FIG. 11 is a diagram showing a DOF in a projection exposure apparatus.

FIG. 12 is a plan view showing a conventional circuit pattern.

FIG. 13 is a plan view showing a circuit pattern according to another conventional example.

FIG. 14 is a plan view showing a circuit pattern according to another conventional example.

[Explanation of symbols]

 17 Patterns Required on Circuit 24-27 Dummy Patterns 28, 30 Connection Part Patterns 29 Adjacent Linear Patterns

Claims (2)

[Claims] 1. In a circuit pattern formed on a semiconductor substrate by exposing the semiconductor substrate with a projection exposure apparatus using modified illumination, a dummy pattern other than a circuit required pattern is extended to a circuit required pattern. A circuit pattern characterized in that the continuity of a certain pattern pitch is enhanced by disposing them separately or separately. 2. In a circuit pattern formed on the semiconductor substrate by exposing the semiconductor substrate with a projection exposure apparatus using modified illumination, linear patterns arranged at predetermined intervals and these linear patterns are formed. A circuit pattern characterized in that the continuity of a certain pattern pitch is enhanced by substituting a thicker pattern than a linear pattern of other portions for the pattern of a partially connected connecting portion.