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JPH0622961Y2 - Ceramic material plate for chip type variable resistor - Google Patents

Ceramic material plate for chip type variable resistor

Info

Publication number
JPH0622961Y2
JPH0622961Y2 JP11262788U JP11262788U JPH0622961Y2 JP H0622961 Y2 JPH0622961 Y2 JP H0622961Y2 JP 11262788 U JP11262788 U JP 11262788U JP 11262788 U JP11262788 U JP 11262788U JP H0622961 Y2 JPH0622961 Y2 JP H0622961Y2
Authority
JP
Japan
Prior art keywords
ceramic material
material plate
chip
variable resistor
type variable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP11262788U
Other languages
Japanese (ja)
Other versions
JPH0233406U (en
Inventor
保 吉村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP11262788U priority Critical patent/JPH0622961Y2/en
Publication of JPH0233406U publication Critical patent/JPH0233406U/ja
Application granted granted Critical
Publication of JPH0622961Y2 publication Critical patent/JPH0622961Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は、チップ型の可変抵抗器において、そのセラミ
ック製チップ基板の製造に際して使用するセラミック素
材板に関するものである。
[Detailed Description of the Invention] [Industrial field of application] The present invention relates to a ceramic material plate used for manufacturing a ceramic chip substrate in a chip type variable resistor.

〔従来の技術〕[Conventional technology]

一般に、チップ型の可変抵抗器は、第4図及び第5図に
示すように、セラミック製のチップ基板1の上面に、当
該チップ基板1の略中心の部位に穿設した中心孔2と同
芯円状に抵抗膜3を形成し、該抵抗膜3に摺接する摺動
子4を、前記中心孔2に挿通した軸5にて回転自在に軸
支した構成にしている。なお、符号6,7は、前記抵抗
膜3の両端に対する端部電極端子、また、符号8は、前
記チップ基板1の裏面に形成の凹み部9内に設けられ、
且つ、前記軸5と電気的に導通するように構成した中心
電極端子である。
Generally, a chip-type variable resistor has the same structure as a central hole 2 formed in a substantially central portion of the chip substrate 1 on the upper surface of a ceramic chip substrate 1 as shown in FIGS. 4 and 5. The resistance film 3 is formed in the shape of a mandrel, and the slider 4 slidably contacting the resistance film 3 is rotatably supported by a shaft 5 inserted in the center hole 2. Reference numerals 6 and 7 are end electrode terminals for both ends of the resistance film 3, and reference numeral 8 is provided in a recess 9 formed on the back surface of the chip substrate 1,
Moreover, the center electrode terminal is configured to be electrically connected to the shaft 5.

そして、このチップ型の可変抵抗器において、中心孔2
と凹み部9とを備えたチップ基板1の製造に際して、従
来は、第6図に示すように、多数個のチップ基板1を複
数列に並べて一体化したセラミック素材板Aを、各チッ
プ基板1に中心孔2と凹み部9とを各々設けると共に、
各チップ基板1の間に長手方向に延びる縦筋目線A1及
びこれと直角の横筋目線A2を設けて製作し、このセラ
ミック素材板Aの上面における各チップ基板1の箇所に
抵抗膜3及び端部電極端子6,7等を塗着形成したの
ち、前記両筋目線A1,A2に沿って各チップ基板1ご
とにブレイクする順序で製造する方法を採用している。
In this chip type variable resistor, the central hole 2
In the manufacture of the chip substrate 1 having the concave portions 9 and the concave portions 9, conventionally, as shown in FIG. 6, a ceramic material plate A in which a large number of chip substrates 1 are arranged in a plurality of rows and integrated into one chip substrate 1 is used. The central hole 2 and the recessed portion 9 are respectively provided in the
A vertical streak line A1 extending in the longitudinal direction and a horizontal streak line A2 perpendicular to the longitudinal streak line A1 are provided between the respective chip substrates 1, and the resistance film 3 and the end portions are formed on the upper surface of the ceramic material plate A at the respective chip substrates 1. After the electrode terminals 6, 7 and the like are formed by coating, a manufacturing method is adopted in which the chip substrates 1 are broken in the order along the lines A1 and A2.

この場合、前記セラミック素材板Aの左右両端縁には、
撮み用の耳片A3,A4を一体的に造形すると共に、こ
の両耳片A3,A4にV型の位置決め用ノッチA5,A
6を設けて、このノッチA5,A6によって、前記抵抗
膜3の塗着形成等に際しての位置決めを行うようにして
いる。
In this case, the left and right edges of the ceramic material plate A are
The ear ears A3 and A4 for photographing are integrally formed, and the notches A5 and A of V-shaped positioning are formed on the ear ears A3 and A4.
6 is provided, and the notches A5 and A6 are used to perform positioning when forming the resistive film 3 by coating.

〔考案が解決しようとする課題〕[Problems to be solved by the device]

前記セラミック素材板Aにおける各チップ基体1には、
中心孔2と凹み部9とを各々を備えていることから、こ
のセラミック素材板Aの製造に際しては、セラミックの
原料粉末aを、第8図に示すように、上下一対の成形型
B,Cにて押圧して固めることにより型成形したのち、
これを高温で焼成することが行なわれる。
Each chip base 1 on the ceramic material plate A is
Since each of the central hole 2 and the recessed portion 9 is provided, when the ceramic material plate A is manufactured, the ceramic raw material powder a is mixed with a pair of upper and lower molding dies B and C as shown in FIG. After molding by pressing with to solidify,
This is fired at a high temperature.

しかし、このように、一対の成形型B,Cで型成形した
のち焼成して製造されるセラミック素材板Aの左右両端
縁に、その製造に際して前記のような位置決め用ノッチ
A5,A6付き耳片A3,A4を一体的に造形するよう
にした場合には、その焼成に際して、以下に述べるよう
に、セラミック素材板Aの幅寸法Sに不揃いが発生する
点に問題がある。
However, in this way, the ear pieces with the positioning notches A5 and A6 as described above are manufactured on the left and right edges of the ceramic material plate A manufactured by molding with the pair of molding dies B and C and then firing. When A3 and A4 are integrally formed, there is a problem in that the width dimension S of the ceramic material plate A is not uniform during firing, as described below.

すなわち、両耳片A3,A4を備えたセラミック素材板
Aを、一対の成形型B,Cによって型成形する場合にお
いて、当該セラミック素材板Aのうち各チップ基板1の
部分は、一対の成形型B,Cに設けた凹み部9の成形用
突起C1及び中心孔2の成形用突起B1の存在により強
く圧縮されることにより、当該部分における組織の密度
が、セラミック素材板Aのうち両耳片A3,A4の部分
よりも密になり、換言すると、セラミック素材板Aのう
ち両耳片A3,A4の部分における組織の密度が、セラ
ミック素材板Aのうち各チップ基板1の部分よりも粗に
なることにより、高温での焼成に際して、当該両耳片A
3,A4の部分が、第6図に二点鎖線Dで示すように、
他の部分よりも大きく収縮することになるから、セラミ
ック素材板Aにおける幅寸法Sが、両耳片A3,A4の
部分と、他の部分とで不揃いになる。
That is, in the case where the ceramic material plate A having the two ear pieces A3 and A4 is molded by the pair of molding dies B and C, the portion of each chip substrate 1 of the ceramic material plate A is a pair of molding dies. By being strongly compressed due to the presence of the molding projection C1 of the recessed portion 9 provided in B and C and the molding projection B1 of the central hole 2, the density of the tissue in the corresponding portion is reduced by the two ear pieces of the ceramic material plate A. It becomes denser than the portions A3 and A4, in other words, the density of the tissue in the portions of the ear plates A3 and A4 of the ceramic material plate A becomes rougher than that of the chip substrate 1 of the ceramic material plate A. As a result, when firing at high temperature, the two ear pieces A
As shown by the chain double-dashed line D in FIG.
Since it shrinks more than other portions, the width dimension S of the ceramic material plate A becomes uneven between the portions of the two ear pieces A3 and A4 and the other portions.

その結果、各チップ基板1と、位置決め用のノッチA
5,A6との位置関係がずれて、セラミック素材板Aに
おける各チップ基板1に対して抵抗膜3を塗着する場合
に、抵抗膜3がチップ基板1の中心からずれたり、或い
は、両耳片A3,A4に隣接する各チップ基板1の寸法
にバラ付きが発生したりするのであった。
As a result, each chip substrate 1 and the positioning notch A
When the resistive film 3 is applied to each chip substrate 1 on the ceramic material plate A due to the positional relationship with the A5 and A6 being displaced, the resistive film 3 is displaced from the center of the chip substrate 1 or both ears The size of each chip substrate 1 adjacent to the pieces A3 and A4 may vary.

本考案は、この問題、つまり、型成形した耳片付きセラ
ミック素材板を高温で焼成するに際して、当該セラミッ
ク素材板の幅寸法に不揃いが発生することを防止できる
ようにしたセラミック素材板を提供するものである。
The present invention provides a ceramic material plate capable of preventing this problem, that is, the width dimension of the ceramic material plate with unevenness when the molded ceramic material plate with ear pieces is fired at a high temperature. Is.

〔課題を解決するための手段〕 この目的を達成するために本考案は、中心孔及び凹み部
を備えた多数個のチップ基板を複数列に並べ、且つ、そ
の端縁に位置決め用ノッチ付き耳片を連接して一体的に
型成形して成るチップ型可変抵抗器用セラミック素材板
において、前記両耳片の部分に、凹所を凹み形成する構
成にした。
[Means for Solving the Problem] In order to achieve this object, the present invention provides a plurality of chip substrates having a central hole and a recessed portion arranged in a plurality of rows, and an edge with positioning notches for positioning. In a ceramic material plate for a chip type variable resistor, which is formed by connecting pieces integrally with each other and molding them integrally, a recess is formed in the portion of the both ear pieces.

〔考案の作用・効果〕[Function and effect of device]

このように、耳片付きセラミック素材板の型成形に際し
て、前記耳片の部分に凹所を凹み形成するようにする
と、当該耳片の部分は強く圧縮され、その部分における
組織は、各チップ基板の部分における組織と同様に密に
なるから、高温での焼成に際して、前記耳片の部分が、
他の部分、つまり、各チップ基板の部分よりも大きく収
縮することを防止できるのである。
In this manner, when the ceramic material plate with ear pieces is formed by molding, a recess is formed in the ear piece portion, the ear piece portion is strongly compressed, and the tissue in that portion is formed by each chip substrate. Since it becomes dense like the tissue in the part, when firing at high temperature, the part of the ear piece,
It is possible to prevent the parts from shrinking more than other parts, that is, the parts of the respective chip substrates.

すなわち、本考案によると、型成形した耳片付きセラミ
ック素材板を高温で焼成するに際して、当該セラミック
素材板の幅寸法に不揃いが発生することを防止できるか
ら、このセラミック素材板における各チップ基板に対し
て抵抗膜を塗着する場合に、抵抗膜が各チップ基板の中
心からずれたりすること、及び前記耳片に隣接する各チ
ップ基板に寸法のバラ付きが発生することを確実に回避
できる効果を有する。
That is, according to the present invention, it is possible to prevent unevenness in the width dimension of the ceramic material plate when firing the molded ceramic material plate with ear pieces at a high temperature. When the resistance film is applied by applying the resistance film, it is possible to surely prevent the resistance film from being displaced from the center of each chip substrate and the occurrence of dimensional variation in each chip substrate adjacent to the ear piece. Have.

〔実施例〕〔Example〕

以下、本考案の実施例を図面(第1図〜第3図)につい
て説明すると、図において符号Aは、多数個のチップ基
板1を複数列に並べ、且つ、その両端縁にV型の位置決
め用ノッチA5,A6を有する耳片A3,A4を備えた
セラミック素材板を示し、該セラミック素材板Aは、第
3図に示すように、セラミックの原料粉末aを上下一対
の成形型B,Cに押圧して固めることにより、各チップ
基板1の相互間及び各チップ基板1と両耳片A3,A4
との間に、各々縦筋目線A1と横筋目線A2とを設けて
一体的に型成形される。
Hereinafter, an embodiment of the present invention will be described with reference to the drawings (FIGS. 1 to 3). In the drawings, reference numeral A indicates a large number of chip substrates 1 arranged in a plurality of rows, and V-shaped positioning on both edges thereof. 3 shows a ceramic material plate provided with ears A3, A4 having notches A5, A6 for use in the ceramic material plate A. As shown in FIG. By pressing and hardening to each other, between each chip substrate 1 and each chip substrate 1 and both ear pieces A3, A4.
And a vertical streak line A1 and a horizontal streak line A2 are respectively provided between and, and they are integrally molded.

この型成形に際して、各チップ基板1の裏面には、一方
の成形型Bに設けた突起B1により凹み部9を各々形成
すると共に、各チップ基板1の中心には、他方の成形型
Cに設けた突起C1により中心孔2を各々形成する。
At the time of this die molding, the recessed portion 9 is formed on the back surface of each chip substrate 1 by the projection B1 provided on one die B, and at the center of each chip substrate 1 is provided on the other die C. The central holes 2 are formed by the protrusions C1.

そして、前記両成形型B,Cのうち上方の位置する他方
の成形型Cには、前記両耳片A3,A4に対する部分に
突起C2を設けることにより、前記セラミック素材板A
の一体的な型成形に際して同時に、両耳片A3,A4の
部分に凹所A7,A8を凹み形成するようにする。
Then, the other molding die C located above the molding dies B and C is provided with a projection C2 at a portion corresponding to the two ear pieces A3 and A4, so that the ceramic material plate A
Simultaneously with the integral molding of, the recesses A7 and A8 are formed in the portions of the two ear pieces A3 and A4.

このように、両耳片A3,A4付きセラミック素材板A
の型成形に際して、前記両耳片A3,A4の部分に凹所
A7,A8を凹み形成すると、当該両耳片A3,A4の
部分は、当該両耳片A3,A4に凹所A7,A8を形成
するための突起C2によって、強く圧縮され、当該両耳
片A3,A4の部分における組織が、凹み部9の形成用
突起B1と中心孔2の形成用突起C1とによって強く圧
縮される各チップ基板1の部分における組織と同様に密
になるのである。
In this way, the ceramic material plate A with both ears A3 and A4
When the recesses A7 and A8 are formed in the portions of the both ear pieces A3 and A4 in the molding of (3), the portions of the both ear pieces A3 and A4 form the recesses A7 and A8 in the both ear pieces A3 and A4. Each chip that is strongly compressed by the projection C2 for forming, and the tissue in the portion of the binaural pieces A3, A4 is strongly compressed by the projection B1 for forming the recess 9 and the projection C1 for forming the central hole 2. It becomes dense like the texture of the substrate 1.

従って、型成形後のセラミック素材板Aを高温で焼成す
るに際して、前記両耳片A3,A4の部分が、第6図に
二点鎖線Dで示すように、他の部分、つまり、各チップ
基板1の部分よりも大きく収縮することを確実に防止で
きるのである。
Therefore, when the ceramic material plate A after molding is fired at a high temperature, the portions of the two ear pieces A3, A4 are different from each other, that is, each chip substrate, as shown by the chain double-dashed line D in FIG. It is possible to reliably prevent the contraction larger than that of the first part.

なお、両耳片A3,A4に対する凹所A7,A8は、セ
ラミック素材板Aの裏面又は表裏両面に対して設けるよ
うにしても良いことは云うまでもない。
It goes without saying that the recesses A7 and A8 for the two ear pieces A3 and A4 may be provided on the back surface or both front and back surfaces of the ceramic material plate A.

【図面の簡単な説明】[Brief description of drawings]

第1図〜第3図は本考案の実施例を示し、第1図はセラ
ミック素材板の平面図、第2図は第1図のII−II視拡大
断面図、第3図は型成形の状態を示す縦断正面図、第4
図はチップ型可変抵抗器の平面図、第5図は第4図のV
−V視断面図、第6図は従来のセラミック素材板の平面
図、第7図は第6図のVII−VII視断面図、第8図は従来
のセラミック素材板の型成形の状態を示す図である。 1……チップ基板、2……中心孔、3……抵抗膜、4…
…摺動子、5……軸、6,7……端部電極端子、8……
中心電極端子、9……凹み部、A……セラミック素材
板、A1……縦筋目線、A2……横筋目線、A3,A4
……耳片、A5,A6……位置決め用ノッチ、A7,A
8……凹所、B,C……成形型、B1,C1,C2……
突起。
1 to 3 show an embodiment of the present invention. FIG. 1 is a plan view of a ceramic material plate, FIG. 2 is an enlarged sectional view taken along line II-II of FIG. 1, and FIG. Fourth vertical front view showing the state
The figure is a plan view of the chip-type variable resistor, and FIG. 5 is the V of FIG.
-V sectional view, FIG. 6 is a plan view of a conventional ceramic material plate, FIG. 7 is a sectional view taken along line VII-VII of FIG. 6, and FIG. 8 is a state of molding of a conventional ceramic material plate. It is a figure. 1 ... Chip substrate, 2 ... Center hole, 3 ... Resistive film, 4 ...
… Slider, 5 …… Axis, 6,7 …… End electrode terminal, 8 ……
Center electrode terminal, 9 ... Recessed portion, A ... Ceramic material plate, A1 ... Longitudinal line, A2 ... Horizontal line, A3, A4
...... Ear pieces, A5, A6 …… Positioning notches, A7, A
8 ... Recess, B, C ... Mold, B1, C1, C2 ...
Protrusion.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】中心孔及び凹み部を備えた多数個のチップ
基板を複数列に並べ、且つ、その端縁に位置決め用ノッ
チ付き耳片を連接して一体的に型成形して成るチップ型
可変抵抗器用セラミック素材板において、前記両耳片の
部分に、凹所を凹み形成したことを特徴とするチップ型
可変抵抗器用セラミック素材板。
1. A chip mold formed by arranging a large number of chip substrates each having a central hole and a recessed portion in a plurality of rows, and connecting an end piece with a notch for positioning to an edge thereof to integrally mold the chip pieces. A ceramic material plate for a chip type variable resistor, characterized in that recesses are formed in the two ear pieces in the ceramic material plate for a variable resistor.
JP11262788U 1988-08-26 1988-08-26 Ceramic material plate for chip type variable resistor Expired - Lifetime JPH0622961Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11262788U JPH0622961Y2 (en) 1988-08-26 1988-08-26 Ceramic material plate for chip type variable resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11262788U JPH0622961Y2 (en) 1988-08-26 1988-08-26 Ceramic material plate for chip type variable resistor

Publications (2)

Publication Number Publication Date
JPH0233406U JPH0233406U (en) 1990-03-02
JPH0622961Y2 true JPH0622961Y2 (en) 1994-06-15

Family

ID=31351736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11262788U Expired - Lifetime JPH0622961Y2 (en) 1988-08-26 1988-08-26 Ceramic material plate for chip type variable resistor

Country Status (1)

Country Link
JP (1) JPH0622961Y2 (en)

Also Published As

Publication number Publication date
JPH0233406U (en) 1990-03-02

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