JPH06213967A - Ic tester - Google Patents

Abstract

PURPOSE:To test the plural kinds of ICs and the ICs having bidirectional pins continuously without changing the test pins and to test the state accurately even if the pin of the IC to be inspected becomes the high impedance state. CONSTITUTION:For every test pin 17, which is connected to a pin 31 of an IC 30 to be inspected, pattern data and attribute data are sent out from a personal computer 20 through an interface circuit 11, a pattern data memory part 13 and an attirbute-data memory part 14. The data from the output pin of the IC are stored in an output data memory part 15. The data stored in the memory part 15 are judged with the personal computer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is connected between a simple personal computer (hereinafter referred to as a personal computer) and an integrated circuit (hereinafter referred to as an IC) to be tested, and the logic circuit of the IC to be tested is connected. Regarding the IC tester to test.
More specifically, a personal computer is used for the gate array and PLD.
Digital IC such as (Programable Logic Device),
The present invention relates to an IC tester for easily testing a logic circuit made by combining them.

[0002]

2. Description of the Related Art A plurality of pins drawn out of a digital IC are an input pin, an output pin, a bidirectional pin, a power supply pin, and a G pin.
It has pin attributes such as ND pin. Conventionally, in this type of tester, a dedicated test pin is connected to each of a plurality of pins of an IC to be tested according to a pin attribute to perform a test.

[0003]

Therefore, according to the above-mentioned conventional method, when testing different types of ICs continuously, or when testing a bidirectional pin in which an input state or an output state occurs in one pin, , Each time, it was necessary to change to a dedicated test pin. Further, when testing one IC, it is necessary to replace it with an appropriate test pin even when the attribute of the pin of the connected IC does not match the attribute set by the test pin. Due to this replacement, the test must be interrupted, and if it is erroneously connected, it may be a cause of electrically damaging the IC to be tested. Further, according to the conventional method, when the pin of the IC is an output pin, it is impossible to test the high impedance state.

An object of the present invention is to provide an IC tester capable of continuously testing a plurality of types of ICs or ICs having bidirectional pins without changing the test pins in correspondence with the pin attributes of the IC under test. To provide. Another object of the present invention is to provide an IC tester that can accurately test the pin of a test IC even if the pin is in a high impedance state.

[0005]

The structure of the present invention for achieving the above object will be described with reference to FIG. The present invention is
An IC tester 10 which is connected between the personal computer 20 and the IC 30 to be tested and tests the logic circuit of the IC 30 to be tested.
Is. The IC tester 10 includes an interface circuit 11 that receives data and control signals from the personal computer 20 and transfers data to the personal computer 20, and a plurality of test pins 17 connected to a plurality of pins 31 of the IC 30 to be tested.
And a pattern data storage unit 13 that stores pattern data to be output from the test pin 17 to the IC 30 to be tested for each test pin based on the data from the interface circuit 11, and a test pin based on the data from the interface circuit 11. An attribute data storage unit 14 that stores attribute data of the test pin 17 for each test pin, and an IC to be tested for each test pin
The output data storage unit 15 stores data from a plurality of pins 31 of 30. Furthermore, this IC tester 10
Pattern data is written to or read from the pattern data storage unit 13, attribute data is written to or read from the attribute data storage unit 14, or data from a plurality of pins 31 of the IC 30 to be tested is stored as output data according to a control signal from the interface circuit 11. The data from the first control unit 12 that controls to write to the unit 15 or to read to the interface circuit 11 and the data from the pattern data storage unit 13 or the attribute data storage unit 14 is output to the test pin 17 or the IC 3 to be tested.
The second control unit 16 outputs data from the plurality of 0 pins 31 to the output data storage unit 15 via the test pin 17.

[0006]

After the predetermined number of test pins 17 are connected to the pins 31 of the IC 30 to be tested, the first control section 12 stores the pattern data and the test pin attribute data in the respective storage sections 13, based on the data from the personal computer 20. Transfer to 14.
The second control unit 16 transmits data to the test IC 30 via the test pin 17 according to the attribute of the pin, and transmits the result to the output data storage unit 15. The data stored in the storage unit 15 is sent to the personal computer 20, and the test result is judged.

[0007]

An embodiment of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the IC tester 10 is connected between a personal computer 20 and an IC 30 to be tested, and has an interface circuit 11, a first control unit 12, a pattern data storage unit 13, an attribute data storage unit 14, and output data. Storage unit 1
5, the second control unit 16, and a plurality of test pins 17. The interface circuit 11 is a parallel interface circuit, which is connected to the interface circuit 20a of the personal computer 20 via the data bus line 11a and the control signal line 11b, and is connected to the pattern data storage unit 13 and the test pin via the data bus line 11c. It is connected to the attribute data storage unit 14.

Here, the pattern data means a digital signal of "1" or "0" for outputting from the test pin 17 to the IC 30 to be tested for each test pin when each test pin 17 transmits a signal to the IC 30 to be tested. And the expected value data from the test IC that will be input to the test pin 17 when the test IC 30 is in the output state. Only the test data is stored in the pattern data storage unit 13. What is the test pin attribute data?
This is data for checking whether the pin of the IC to be tested to which the test pin is connected has an attribute of an input pin, an output pin, or a bidirectional pin. The pattern data and the attribute data are created in time series for each test pin using dedicated software in the personal computer 20.

The interface circuit 11 is connected to the first control unit 12 via the control signal line 11d, and the first control unit 12 controls the control signal lines 12a, 12b, 12c and 1.
The pattern data storage unit 13, the attribute data storage unit 14, the output data storage unit 15, and the second control unit 16 are respectively connected via 2d. Further, the pattern data storage unit 13 and the attribute data storage unit 14 are respectively connected to the data bus line 13
It is connected to the second controller 16 via a and 14a. Second
The control unit 16 has a plurality of test pins 17, and is connected to the output data storage unit 15 via the data bus line 16a.

As shown in FIG. 2, the second controller 16 includes a pattern data latch circuit 161, an attribute data latch circuit 1
62, semiconductor switch controller 163, buffer 1
64, a manual switch 165, a jumper switch 166, and a semiconductor switch 167. Although the buffer 164, the manual switch 165, the jumper switch 166, and the semiconductor switch 167 are respectively provided in a plurality of numbers corresponding to the number of test pins, only one is shown in each of FIGS. The data bus line 13a from the pattern data storage unit 13 is connected to the latch circuit 161, and the data bus line 14a from the attribute data storage unit 14 is connected to the latch circuit 162. Further, the latch circuits 161 and 1
62 is a latch signal line 12 from the first control unit 12
e, the latch enable signal line 12f and the OUT signal line 12g are connected to each other.

The latch circuit 16 is connected to the input of the buffer 164.
The data line 161a from the latch circuit 162 is connected to the control line of the data line 161a.
Are connected, and the output of the buffer 164 is connected to the test pin 17 via the switch 165. The control signal line 12d from the first controller 12 is connected to the control input of the controller 163. The controller 163 is the switch 16
7 has a switch 163a for determining the initial state. The control signal line 163b from the controller 163 is connected to the control input of the switch 167.
The switching signal line 167 a of No. 7 is connected to the connection point A between the switch 165 and the test pin 17. The data line 16a from the connection point A to the switch 166 and the output data storage unit 15 is connected. The attribute data latch circuit 162 and the semiconductor switch controller 163 have an I (not shown).
The reset signal lines 162b and 163c from the reset switch of the C tester 10 are connected to each other. IC
A double-pole double-throw switch 10c is provided between the power supply 10a and GND 10b of the tester 10 and the respective Vcc terminals and GND terminals of the switches 166 and 167. A predetermined voltage is applied to the terminals.

A method of using the IC tester 10 having such a configuration will be described. First, a reset signal is sent to the reset signal lines 162b and 163c to initialize the IC tester 10. As a result, all the latches of the attribute data latch circuit 162 are initialized to the low level, and the buffer 164 enters the high impedance state. Next, the double-pole double-throw switch 10c is opened, and the respective Vcc terminals and GND terminals of the switches 166 and 167 are connected to the power source 10 of the IC tester 10.
Separated from a and GND10b, separate system. As a result, all the test pins 17 are in a high impedance state.

In this state, as many test pins as the number of the pins 31 of the IC 30 to be tested are selected from the plurality of test pins 17, and these are arbitrarily connected to the pins 31 via the line 18 without paying attention to the order. . If the test pin 17 connected here corresponds to the power supply pin or the GND pin of the IC 30 under test, the manual switch 16 of the corresponding test pin 17 is used.
Open 5 and use the jumper switch 166 to connect V to the power pin.
Connect the cc power supply and the GND terminal to the GND pin. In addition, the test pin 17 is a power supply pin of the IC 30 to be tested or G
If it does not correspond to the ND pin, the manual switches 165 of all the corresponding test pins 17 are closed, and the jumper switch 166 is set to nothing.

Further, in order to stabilize the test pin 17 when the IC tester 10 is in the initial state, the switch 163a is turned on / off for each test pin to determine the initial state of the semiconductor switch 167. Then, again reset signal line 162
After sending the reset signals to b and 163c, the double pole double throw switch 10c is closed and a voltage is applied to the IC 30 to be tested. This completes the test preparation work for the IC 30 to be tested.

To test the IC 30 to be tested, first, the personal computer 2
From 0 to the pattern data storage unit 1 via the first control unit 12.
3 and the personal computer 2 in the test pin attribute data storage unit 14
Transfer the data created with 0. After the transfer of all the data is completed, the first control unit 12 generates a latch signal and a latch enable signal, and the pattern data latch circuit 161 and the attribute data latch circuit 162 respectively latch the test signals for one pattern. Next, when the OUT signal is sent from the control unit 12, one pattern of data is sent to all the test pins 17 via the buffer 164. In this state, the data transmitted from the test pin 17 connected to the output pin of the IC 30 to be tested is written in one of the two output data storage units 15. Then, a control signal is sent from the first controller 12 to the semiconductor switch controller 163, and the semiconductor switch 167 is switched to the switch 163a.
Irrespective of the state, the data transmitted from the test pin 17 is written in the other output data storage unit 15.
This is repeated for a predetermined test pattern, and the test ends.

If any error occurs in this process, the first controller 12 immediately generates a reset signal,
The IC tester 10 is initialized so that the test IC 30 is not adversely affected. The result of the test can be visually confirmed by a display (not shown) connected to the personal computer 20 by loading the data of the two output data storage units 15 into the personal computer 20, respectively. When the two data sent from the output data storage unit 15 are different from each other, the data sent from the IC 30 to be tested can have a high impedance.

When one IC has been tested and another IC is to be tested, the IC tester 10 is initialized as described above, the two-pole double-throw switch 10c is opened, and the test preparation work is performed. Test as well. As a result, the test pins can be replaced without electrically damaging the IC 30 to be tested.

FIG. 3 is an operation time chart when the test pin 17 is connected to the bidirectional pin of the IC 30 to be tested.
The symbols of the signal waveforms in FIG. 3 correspond to the symbols shown by the crosses in FIG. In FIG. 3, time t _{0 to} t ₁ , time t _{1 to} t ₂ ,
.., time t _{13 to} t ₁₄ respectively represent one pattern transmission time of data. As is clear from the signal waveform indicated by reference numeral (b), T ₁ (t _{0 to} t ₆ ) is the time when the test pin operates as an input pin, and T ₂ (t _{6 to} t ₁₄ ) is the test pin. It is the time to operate as an output pin. At time T ₁ , the signal waveform of the pattern data indicated by the code (a) is the code (d).
It becomes the same as the signal waveform shown by.

Further, in the time period from t _{6 to} t ₉ of the time T ₂ , the signal waveform of the code (d) is switched between the low level and the high level within one pattern, and the output pin is in the open state, that is, the high impedance state. It is shown that there is. t _{9 to} t
_At the time of ₁₄ , since the signal waveform of the code (d) is constant without changing the level within one pattern, it is shown that some data is transmitted to the test pin connected to the output pin. Specifically, the signal waveforms indicated by these symbols (d) are written in the output data storage unit 15 and then
It is transferred to the personal computer 20, where it is compared with the expected value data and judged.

[0020]

As described above, according to the present invention, the pattern data and the test pin attribute data are transferred to the respective storage units based on the data from the personal computer, and the test pin is determined according to the pin attribute. After the data is transmitted to the IC to be tested via the output data and the result is transmitted to the output data storage unit, the data stored in this storage unit is judged by the personal computer. Multiple types of IC without changing test pins according to attributes
ICs with or bidirectional pins can be tested continuously. Even if the pins of the IC to be tested are in a high impedance state, there is an excellent effect that the state can be accurately tested.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram including an IC tester according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing in detail a main part thereof.

FIG. 3 is an operation time chart thereof.

[Explanation of symbols]

 10 IC Tester 11 Interface Circuit 12 First Control Section 13 Pattern Data Storage Section 14 Attribute Data Storage Section 15 Output Data Storage Section 16 Second Control Section 17 Test Pin 20 Personal Computer 30 Test IC 31 IC Pin

Claims (2)

[Claims] 1. A test circuit I, which is connected between a personal computer (20) and an IC (30) to be tested, for testing a logic circuit of the IC (30) to be tested.
C tester (10), an interface circuit for receiving data or control signals from the personal computer (20) and transferring data to the personal computer (20)
(11), a plurality of test pins (17) for connecting to each of a plurality of pins (31) of the IC to be tested (30), and the test pins based on data from the interface circuit (11). From the test pin (17) to the IC to be tested
A pattern data storage unit (13) that stores pattern data to be output to (30), and stores attribute data of the test pin (17) for each test pin based on the data from the interface circuit (11). Attribute data storage unit (14), and a plurality of pins (31) of the IC to be tested (30) for each test pin
Output data storage unit (15) for storing data from the, and write or read the pattern data in the pattern data storage unit (13) by a control signal from the interface circuit (11), the attribute data to the attribute data Memory
Writing to or reading from (14) or data from a plurality of pins (31) of the IC to be tested (30) is output data storage section (15).
Data from the pattern data storage unit (13) or the attribute data storage unit (14) and a first control unit (12) for controlling writing to or reading from the interface circuit (11). 17) or outputs data from a plurality of pins (31) of the IC (30) to be tested via the test pin (17) to the output data storage section (15)
An IC tester, comprising: a second control unit (16) for controlling the output of the IC tester. 2. A semiconductor switch (16)
7) and a semiconductor switch controller for switching the semiconductor switch (167) according to a control signal from the first controller (12)
(163), the output data storage section (15) has two storage areas, and the IC to be tested (3) according to the switching of the semiconductor switch (167).
The IC tester according to claim 1, wherein the data from the test pin (17) connected to the output pin (0) is separately stored in the two storage areas.