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JPH06216167A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JPH06216167A
JPH06216167A JP5007326A JP732693A JPH06216167A JP H06216167 A JPH06216167 A JP H06216167A JP 5007326 A JP5007326 A JP 5007326A JP 732693 A JP732693 A JP 732693A JP H06216167 A JPH06216167 A JP H06216167A
Authority
JP
Japan
Prior art keywords
fine particles
semiconductor device
filler
solder
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5007326A
Other languages
Japanese (ja)
Other versions
JP2810285B2 (en
Inventor
Toshiki Yagihara
俊樹 八木原
Masami Fujii
正己 藤井
Toshiki Kurosu
俊樹 黒須
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Minebea Power Semiconductor Device Inc
Original Assignee
Hitachi Ltd
Hitachi Haramachi Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Haramachi Electronics Ltd filed Critical Hitachi Ltd
Priority to JP5007326A priority Critical patent/JP2810285B2/en
Publication of JPH06216167A publication Critical patent/JPH06216167A/en
Application granted granted Critical
Publication of JP2810285B2 publication Critical patent/JP2810285B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H10W72/30

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】 (修正有) 【目的】臘材厚さを均一にすることにより、他の性能を
犠牲にすること無く信頼性のバラツキを低減でき、且つ
信頼性の高い半導体装置を提供すること。 【構成】金属ベース2の上に、電極処理を施した絶縁基
板4bを配置し、その上に半導体素子1が積層配置さ
れ、各々を臘材5にて接着した半導体装置において、臘
材中に臘材厚より小さい粒径の微細粒子8を30%以下
で含有している臘材である半導体装置。
(57) [Summary] (Modified) [Purpose] Providing a highly reliable semiconductor device that can reduce variations in reliability without sacrificing other performance by making the thickness of the members uniform. To do. [Structure] In a semiconductor device in which an electrode-treated insulating substrate 4b is arranged on a metal base 2, semiconductor elements 1 are laminated thereon, and each is adhered by a member 5, in a member. A semiconductor device which is a filler containing 30% or less of fine particles 8 having a particle size smaller than the filler thickness.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高信頼性を有する半導体
装置及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly reliable semiconductor device and a method of manufacturing the same.

【0002】[0002]

【従来の技術】パワーモジュールを例に採ると、従来絶
縁板にはAl23,BeO等が、また最近ではAlN等
が採用され、ニッケルメッキを施したベースに半田にて
接続されている。しかし、モジュールが大容量の方向に
拡大しており、このため絶縁基板及び金属ベースも大形
化し、臘材による均一な接続が臘材のかたよりや気泡等
が生じることにより難しくなってきている。
2. Description of the Related Art Taking a power module as an example, a conventional insulating plate made of Al 2 O 3 , BeO or the like, or recently made of AlN or the like is connected to a nickel-plated base by soldering. . However, the module is expanding in the direction of a large capacity, and therefore the insulating substrate and the metal base are also becoming large in size, and it is becoming difficult to uniformly connect the members by the members of the members, the air bubbles and the like.

【0003】また、より信頼性を要求される用途に採用
されつつあり、均一な臘材による接続技術が重要であ
る。
Further, it is being adopted for applications requiring higher reliability, and a connection technique using a uniform bar is important.

【0004】これに対し、図2に示すような所定臘付け
部の周囲に樹脂等による臘材の流れ止め6を設け、接続
部の臘材料を確保する構造、及び図3に示すような絶縁
板4と金属ベース2の間に、凹凸を設けた薄い中間金属
板7を挿入し、臘材5a,5b厚さの均一性を図った構
造が採用されている。
On the other hand, as shown in FIG. 2, a structure for securing the flow material 6 of the connecting portion is provided by providing a flow stopper 6 for the flow material around the predetermined attaching portion, and insulation as shown in FIG. A thin intermediate metal plate 7 having irregularities is inserted between the plate 4 and the metal base 2 so that the thickness of the bar members 5a and 5b is uniform.

【0005】しかし、図2のような構造では、臘材面内
での傾きについてはコントロールできず、たとえば半導
体装置の動作,休止に伴う温度変化により熱膨張率の異
なる絶縁板4と金属ベース2の間の臘材5は疲労を受
け、臘材の薄い部分から亀裂を生じ極端な場合、剥離に
至る。臘材の厚さと亀裂発生までの温度変化のサイクル
数には、図4のような関係があり、臘材の均一性は信頼
性のバラツキを少なくする上で重要である。
However, in the structure shown in FIG. 2, the inclination in the plane of the bar cannot be controlled, and for example, the insulating plate 4 and the metal base 2 having different thermal expansion coefficients due to the temperature change caused by the operation and rest of the semiconductor device. The bar 5 between them undergoes fatigue, causing cracking from the thin part of the bar and in extreme cases leading to peeling. There is a relationship as shown in FIG. 4 between the thickness of the filler and the number of cycles of temperature change until crack initiation, and the uniformity of the filler is important for reducing variations in reliability.

【0006】また、図3のような構造では、半導体素子
が動作した時に発生する熱は、絶縁板4を通り金属ベー
ス2から放熱するが、その熱抵抗は部材が一層追加とな
ることにより増加し、素子に対する冷却性能が低下す
る。
Further, in the structure as shown in FIG. 3, heat generated when the semiconductor element operates is radiated from the metal base 2 through the insulating plate 4, but its thermal resistance increases due to the additional member. However, the cooling performance for the element deteriorates.

【0007】素子の動作時の発熱密度は、素子の性能改
善と共に増加する傾向にあり、冷却性能の低下は、素子
の性能を引出す上で弊害となる。
The heat generation density during the operation of the element tends to increase with the improvement of the element performance, and the deterioration of the cooling performance is a detriment to the performance of the element.

【0008】[0008]

【発明が解決しようとする課題】上記のように、装置の
大形化に対した信頼性を確保する構造、他の性能の一部
を犠牲にして達成されている。
As described above, this is achieved by sacrificing a part of the structure and the structure for ensuring the reliability against the size increase of the device.

【0009】本発明では、他の性能を犠牲にすること無
く、装置の大形化に対応した信頼性を確保する構造の提
供である。
The present invention is to provide a structure for ensuring reliability corresponding to an increase in the size of a device without sacrificing other performances.

【0010】[0010]

【課題を解決するための手段】図4の関係に着目し、臘
材厚さを均一にする構造の提案である。
[Means for Solving the Problems] This is a proposal of a structure in which the thickness of the bar members is made uniform by paying attention to the relationship of FIG.

【0011】[0011]

【作用】臘材厚さを均一にすることにより、他の性能を
犠牲にすること無く信頼性のバラツキを低減でき、且つ
信頼性の高い半導体装置を提供できる。
By making the thickness of the filler uniform, it is possible to reduce the variation in reliability without sacrificing other performances and to provide a highly reliable semiconductor device.

【0012】[0012]

【実施例】図1に、本発明の一実施例を示す。FIG. 1 shows an embodiment of the present invention.

【0013】絶縁基板4bは、熱伝導性の良好なAlN
を使用し、電極処理4a,4cはCuの薄板を臘付けに
より接続した構造を有し、半導体素子は融点が300℃
程度のPb−Sn系半田を用いてAlNのCu電極4a
上に半田付けされる。半導体素子1の基体であるSiお
よびAlN4bの熱膨張率は、それぞれ3×10-6
℃,4×10-6/℃と非常に近いため臘材の疲労は起き
にくい。
The insulating substrate 4b is made of AlN having good thermal conductivity.
And the electrode treatments 4a and 4c have a structure in which thin Cu plates are connected by bonding, and the semiconductor element has a melting point of 300 ° C.
Cu electrode 4a of AlN using about Pb-Sn solder
Soldered on. The thermal expansion coefficients of Si and AlN4b, which are the bases of the semiconductor element 1, are 3 × 10 −6 /
Since it is very close to ℃ and 4 × 10 -6 ℃, fatigue of the bark is unlikely to occur.

【0014】そのごAlワイヤ3により配線を施し、C
uベース2の融点が180℃程度の半田5で接着する。
Cuベースの熱膨張率は約17×10-6/℃とSi及び
AlNに対して大きくこの部分の熱疲労耐量が半導体装
置の信頼性確保の上で重要である。
Wiring is performed by the Al wire 3, and C
The u base 2 is bonded with the solder 5 having a melting point of about 180 ° C.
The thermal expansion coefficient of the Cu base is about 17 × 10 −6 / ° C., which is large relative to Si and AlN, and the thermal fatigue resistance of this portion is important for ensuring the reliability of the semiconductor device.

【0015】ここでは、目的とする熱疲労寿命を確保す
るため、臘付け後半田厚みは均一に100μm以上を満
足する必要が有る。
Here, in order to secure the desired thermal fatigue life, it is necessary to uniformly satisfy the solder thickness after gluing to 100 μm or more.

【0016】よって、Cuベース2とAlN基板4間の
臘付け用半田としては、高温でも粒径を維持できるNi
微細粒子8の70〜100μmを5%含有したPbSn
共晶半田で、厚み300μm、寸法は接着面積の1/3
の半田シートを配置しておき、臘付け時にはAlN基板
又はCuベース側より十分な荷重を与え製造する。
Therefore, as the solder for bonding between the Cu base 2 and the AlN substrate 4, Ni that can maintain the grain size even at high temperature is used.
PbSn containing 5% of 70 to 100 μm of fine particles 8
Eutectic solder, thickness 300μm, size is 1/3 of the bonded area
The solder sheet is placed, and a sufficient load is applied from the side of the AlN substrate or the Cu base when the soldering is performed.

【0017】製造上の問題としては、Ni微細粒子が1
00μm以上となる場合、Ni微細粒子の含有量が30
%以上となる場合、臘付け時荷重を与えない場合に粒子
が重なり合うことが発生しCuベースとAlN基板間の
隙間が広くなり半田量が不足し半田ボイドの発生原因と
なる。
As a manufacturing problem, Ni fine particles are
When it is more than 00 μm, the content of Ni fine particles is 30
If it is more than 100%, particles may overlap each other when a load is not applied at the time of squeezing, the gap between the Cu base and the AlN substrate becomes wide, and the amount of solder becomes insufficient, which causes a solder void.

【0018】図1でのNi微細粒子8は、半田シート中
に全面均一にNi微細粒子を圧延にて埋め込んだもので
ある。
The Ni fine particles 8 shown in FIG. 1 are obtained by uniformly filling the solder sheet with Ni fine particles by rolling.

【0019】図5には他の実施例を示す、本図はCuベ
ース2とAlN基板4間の半田5の厚みを均一にするた
めに必要最小限のNi微細粒子埋め込み量にて製造する
方法として、Cuベース2にPbSn共晶クリーム半田
9を印刷し、その上の両端部へNi微細粒子8を散布す
ることにより、局部的なスペーサ効果にて半田厚みを確
保できる構造となっている。この場合、臘付け中に半田
が溶融し半田が流れ出した時、共にNi微細粒子がCu
ベースとAlN基板間から流れだす恐れが有るため、半
田流れ防止,半田サイズ縮小化,Ni微細粒子散布面積
拡大等の対応が必要である。
FIG. 5 shows another embodiment. This figure shows a method of manufacturing with a minimum amount of Ni fine particles embedded to make the thickness of the solder 5 between the Cu base 2 and the AlN substrate 4 uniform. As a result, the PbSn eutectic cream solder 9 is printed on the Cu base 2 and the Ni fine particles 8 are sprinkled on both end portions on the PbSn eutectic cream solder 9, so that the solder thickness can be secured by a local spacer effect. In this case, when the solder melts during soldering and the solder flows out, Ni fine particles are
Since there is a risk of flow out from between the base and the AlN substrate, it is necessary to take measures such as preventing solder flow, reducing solder size, and expanding Ni fine particle dispersion area.

【0020】図6には、他の実施例としてCuベース2
とAlN基板4間の半田5にガラス繊維を埋め込んだ場
合を示す。半田5は、ガラス繊維10を最少2本圧延し
て埋め込むことにより半田厚みの均一な確保が出来る。
FIG. 6 shows a Cu base 2 as another embodiment.
A case where glass fiber is embedded in the solder 5 between the AlN substrate 4 and the AlN substrate 4 is shown. As for the solder 5, a uniform thickness of the solder can be secured by rolling and embedding at least two glass fibers 10.

【0021】[0021]

【発明の効果】大形の、絶縁板を有する半導体装置の温
度変化に伴う熱疲労信頼性の向上を図った製造方法が提
供できる。
As described above, it is possible to provide a manufacturing method in which the reliability of thermal fatigue of a large-sized semiconductor device having an insulating plate due to temperature change is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例(樹脂層及び配線,端子は省
略)の平面図及び断面図である。
FIG. 1 is a plan view and a sectional view of an embodiment of the present invention (a resin layer, wiring, and terminals are omitted).

【図2】従来構造(絶縁板の電極処理,半導体素子,樹
脂層及び配線,端子は省略)の平面図および断面図であ
る。
2A and 2B are a plan view and a cross-sectional view of a conventional structure (electrode treatment of an insulating plate, a semiconductor element, a resin layer and wiring, and terminals are omitted).

【図3】他の従来例(絶縁板の電極処理,半導体素子,
樹脂層及び配線,端子は省略)の側面図である。
FIG. 3 is another conventional example (electrode treatment of insulating plate, semiconductor element,
It is a side view of a resin layer, wiring, and a terminal).

【図4】半田亀裂長さと温度変化サイクル数(対数表
示)の関係図である。
FIG. 4 is a relationship diagram of a solder crack length and a temperature change cycle number (logarithmic display).

【図5】本発明の他の実施例(絶縁板の電極処理,半導
体素子,樹脂層及び配線,端子は省略)の平面図及び断
面図である。
5A and 5B are a plan view and a sectional view of another embodiment of the present invention (electrode treatment of an insulating plate, semiconductor elements, resin layers and wirings, and terminals are omitted).

【図6】本発明の他の実施例(絶縁板の電極処理,半導
体素子,樹脂層及び配線,端子は省略)の平面図及び断
面図である。
6A and 6B are a plan view and a cross-sectional view of another embodiment of the present invention (electrode treatment of insulating plate, semiconductor element, resin layer and wiring, terminals are omitted).

【符号の説明】[Explanation of symbols]

1…半導体素子、2…金属ベース、3…アルミワイヤ、
4a…上側電極、4b…絶縁基板、4c…下側電極、5
…臘材(半田)、6…流れ止め樹脂、7…中間金属板、
8…Ni微細粒子、9…クリーム半田、10…ガラス繊
維。
1 ... Semiconductor element, 2 ... Metal base, 3 ... Aluminum wire,
4a ... upper electrode, 4b ... insulating substrate, 4c ... lower electrode, 5
... solder (soldering), 6 ... flow-stopping resin, 7 ... intermediate metal plate,
8 ... Ni fine particles, 9 ... Cream solder, 10 ... Glass fiber.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 黒須 俊樹 茨城県日立市幸町三丁目1番1号 株式会 社日立製作所日立工場内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Toshiki Kurosu 3-1-1, Saiwaicho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi factory

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】金属ベースの上に、電極処理を施した絶縁
基板を配置し、その上に半導体素子が積層配置され、各
々が臘材にて接着した半導体装置において、臘材中に臘
材厚より小さい粒径の微細粒子を30%以下で含有して
いる臘材である事を特徴とする半導体装置。
1. A semiconductor device in which an electrode-treated insulating substrate is disposed on a metal base, semiconductor elements are stacked on the insulating substrate, and each is adhered by a rod, and the rod is placed in the rod. A semiconductor device, which is a filler containing 30% or less of fine particles having a particle diameter smaller than the thickness.
【請求項2】請求項1において、臘材中の微細粒子が局
部的に集中して存在する事を特徴とする半導体装置。
2. A semiconductor device according to claim 1, wherein fine particles in the filler are locally concentrated.
【請求項3】請求項1において、積層された臘材が臘付
け前は臘付け後より厚みを厚くしておく事を特徴とする
臘材。
3. The member according to claim 1, wherein the laminated members are made thicker before being attached than after being attached.
【請求項4】請求項1において、部材へクリーム状の臘
材を印刷しておきその後に微細粒子を臘材上へ挿入し各
々の部材を積層状に積み重ねて臘付けする事を特徴とす
る半導体装置の製造方法。
4. The method according to claim 1, wherein the members are printed with a cream-like filler, and then fine particles are inserted onto the filler and each member is stacked in a laminated form and attached. Manufacturing method of semiconductor device.
【請求項5】請求項1において、微細粒子の材質が臘材
の溶融点以上で粒径を実質的に維持できる金属・ガラス
・カーボン・有機質材である事を特徴とした臘材。
5. The rod material according to claim 1, wherein the material of the fine particles is a metal / glass / carbon / organic material capable of substantially maintaining the particle diameter above the melting point of the filler.
【請求項6】請求項1において、臘材の成分が鉛(P
b)系半田の場合は鉛が95%以下・鈴(Sn)系半田
の場合は鈴が95%以下である事を特徴とする臘材。
6. The composition according to claim 1, wherein the component of the timber is lead (P
b) Lead material is 95% or less in the case of solder based on solder, and bell is 95% or less in the case of solder based on Sn (Sn) solder.
【請求項7】請求項1において、微細粒子形状が繊維状
である事を特徴とする微細粒子。
7. The fine particles according to claim 1, wherein the shape of the fine particles is fibrous.
【請求項8】請求項1において、臘材状態が固形又はク
リーム状である事を特徴とする臘材。
8. The bark of claim 1, wherein the bark is in a solid or creamy state.
【請求項9】請求項1において、絶縁基板と金属ベース
間及び絶縁基板と半導体素子間に接着用臘材を積層状に
配置した上に荷重を与え臘付けを行う事により、微細粒
子の粒径とほぼ等しい臘材厚みを確保できることを特徴
とする半導体装置の製造方法。
9. The fine particles according to claim 1, wherein adhesive tabs are laminated between the insulating substrate and the metal base, and between the insulating substrate and the semiconductor element, and a load is applied to the adhesive tabs so that fine particles are formed. A method for manufacturing a semiconductor device, which is capable of ensuring a thickness of a filler substantially equal to a diameter.
JP5007326A 1993-01-20 1993-01-20 Semiconductor device and manufacturing method thereof Expired - Lifetime JP2810285B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5007326A JP2810285B2 (en) 1993-01-20 1993-01-20 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5007326A JP2810285B2 (en) 1993-01-20 1993-01-20 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH06216167A true JPH06216167A (en) 1994-08-05
JP2810285B2 JP2810285B2 (en) 1998-10-15

Family

ID=11662846

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2810285B2 (en)

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US7722962B2 (en) 2000-12-21 2010-05-25 Renesas Technology Corp. Solder foil, semiconductor device and electronic device
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JP2014133256A (en) * 2013-01-11 2014-07-24 Toyota Central R&D Labs Inc Brazing structure
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