JPH06202867A - Parallel computer - Google Patents

Abstract

(57) [Summary] [Purpose] To obtain a parallel computer with efficient data processing and improved processing capability. The execution stage 6'compares the memory address with the address SMA of the memory data storage unit 9 and the operation result MA which is the read address calculated by the operation executor 13 when the instruction code OP instructs reading. Bowl 1
Compare by 0. And the memory / address comparator 1
When the match signal GET whose comparison result is 0 is the H level and it is determined that both MA and SMA match, the same data as the read data from the data memory 3 by the memory access stage 7 which is the next stage, It can be obtained by reading the data DATA based on the data MD in the memory data storage unit 9. [Effect] The pipeline processing can be performed more efficiently, and the processing capacity can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer for executing instructions in a pipeline system, and more particularly to a reduced instruction set computer RISC adopting a pipeline system.

[0002]

2. Description of the Related Art In RISC, memory access is
It employs a load / store architecture that is limited to load (read) and store instructions. All arithmetic instructions are performed using the data stored in the internal registers. RISC generally has the following features.

(1) The instruction is executed in one machine cycle.

(2) Fixed-length instructions (3) Only load / store instructions access the memory,
Later instructions are performed on registers.

(4) By pipeline processing, several instructions are simultaneously processed in parallel.

(5) Processing for improving performance is performed by hardware, and complicated processing is performed by software.

FIG. 9 shows an example of a general functional configuration of RISC. In FIG. 9, the RISC is composed of an instruction memory 1 for storing instructions, a register file 2 including a plurality of registers for temporarily storing data, a data memory 3 for storing data, and a pipeline of 5 stages. It consists of stages 4-8.

The instruction fetch stage (IF) 4 is provided with a program counter (not shown), and the address signal generated from the program counter is used for the instruction memory 1
Give to. The instruction designated by the applied address signal is fetched and sent to the instruction decoding stage 5.

The instruction decode stage (ID) 5 receives an instruction from the instruction memory 1 via the instruction fetch stage 4 and decodes the instruction. Then, the instruction decoding stage 5 executes the next execution stage 6 without waiting for the given instruction based on the instruction decoding result.
In the case of an instruction that can be executed by, the execution stage 6 registers the data used to execute the given instruction.
The data is read from the filter 2 and the read data is given to the execution stage 6.

The execution stage (EXC) 6 executes a given instruction when the decoded instruction is an arithmetic instruction. When the decoded instruction is a memory access instruction (load instruction, store instruction), the execution address of the data memory 3 is calculated and the memory access stage (ME
M) give to 7.

The memory access stage 7 accesses the data memory 3 according to the execution address obtained from the execution stage 6 and executes writing and reading of data.

The write back stage (WB) writes the calculation result and the read data from the data memory 3 into the register file 2.

The RISC also operates in response to an externally applied two-phase non-overlap clock signal. An example of the two-phase non-overlap clock signals φ1 and φ2 is shown in FIG. RISC is pipelined and fetches a new instruction every clock cycle. Figure 9
In the RISC shown in (5), 5 cycles are required to complete the execution of one instruction. However, because the parallel computer RISC is pipelined so that it can start a new instruction every clock cycle, the start of a new instruction can be done before the completion of the current instruction.

FIG. 11A shows the pipeline operation of RISC. Instructions 1 to 3 are fetched in the instruction fetch stage 4, and then pass through the instruction decode stage 5, the execution stage 6, the memory access stage 7 and the write back stage 8.

As shown in FIG. 11A, the cycle T2
In, the instruction decoding of the instruction 1 and the fetching of the instruction 2 are simultaneously performed. In cycle T3, instruction 1 is executed, instruction 2 is decoded, and instruction 3 is fetched at the same time. In this way, since the instructions are executed in parallel in a pipeline manner, it is possible to execute one instruction in one machine cycle as a whole.

Memory access instructions in RISC include instructions that handle data in word units, as well as instructions that handle bytes or half words. Generally, reading from the memory is performed in units of one word (a plurality of bytes), and if the instruction is in units of bytes or half words, unnecessary data is discarded.

[0017]

DISCLOSURE OF THE INVENTION The conventional RI having the above structure
As shown in FIG. 11 (b), the instruction 3 (load (read) instruction in byte unit), the instruction 2 (load (read) instruction in byte unit), and the instruction 3 (operation instruction) are sequentially performed in 3 order as shown in FIG. One instruction is sequentially given and processed, and in addition, the instruction 2 reads a part of the data read from the data memory 3 by the instruction 1, and the data read by the execution of the instruction 2 is the instruction 3 Suppose it is used in the processing of.

In such a case, as shown in FIG. 11B, the instruction 1 is first executed and then terminated. That is,
The instruction 1 is processed in the instruction fetch stage 4 during the period T1, and the instruction 1 is processed in the instruction decode stage 5 during the period T2. The processing of the instruction 1 in the execution stage 6, the memory access stage 7, and the write back stage 8 is performed in the periods T3 and T.
4 and T5, respectively.

On the other hand, for the instruction 2, the instruction fetch stage 4 is executed in the period T2, and the instruction 2 in the instruction decode stage 5 is processed in the period T3. In the periods T4, T5, T6, the execution stage 6, the memory,
The processing of the instruction 2 in the access stage 7 and the write back stage 8 is performed.

The instruction 3 is processed in the instruction fetch stage 4 in the period T3, and is processed in the instruction decode stage 5 in the period T4. However, the execution of the processing of the instruction 3 in the execution stage 6, the memory access stage 7, and the write back stage 8 from the period 5 is stopped. This is because, as described above, the instruction 3 uses the data read from the data memory 3 in the instruction 2, and thus the execution of the instruction 2 ends (the data is stored in the register file 2 by the write-back stage 8). This is because the instruction 3 cannot be executed without waiting for.

That is, the instruction 3 has a period T5 and a period T.
Waiting state in 6 (pipeline interlock)
Then, the execution is restarted in the period T7 next to the period T6 in which the instruction 2 is completed. As for the restarted instruction 3, the processing of the instruction 3 in the instruction / decode stage 5 is performed in the period T7. Then, the processing of the instruction 3 in the execution stage 6, the memory access stage 7, and the writeback stage 8 is executed in the periods T8, T9, and T10, respectively.

As described above, although the same data is continuously read by the instruction 1 and the instruction 2, and the data to be read by the instruction 2 is already read from the data memory 3 by the execution of the instruction 1. , The instruction 2 again performs the same read operation as the instruction 1, which is a wasteful operation. .

When the instruction 3 uses the read data of the instruction 3, the data read by the instruction 2 can be executed in the execution stage 6 after being written in the register file 2 once. Access register file 2 at. Therefore, it is necessary to wait in the periods T5 and T6 during the execution of the read process of the instruction 2.

However, as shown in FIG. 11B, the data read by the execution of the instruction 2 has a period T.
It has already been read from the data memory 3 at the time point 4. Nevertheless, since the instruction 3 is discarded during the processing of the instruction 2, the instruction 3 referring to the data must wait until the execution of the instruction 2 ends.

As a result, since an extra waiting time is provided, it takes a long time to complete the execution of the instruction.
It has reduced the processing capacity of parallel computers such as ISC.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a parallel computer which performs efficient data processing and improves the processing capacity.

[0027]

A parallel computer according to a first aspect of the present invention receives a register, data storage means for storing data necessary for executing an instruction, an instruction code, and decodes the instruction code. And a command determined based on the result of decoding by the command decoding unit are executed using the data stored in the register as necessary, and the command instructs reading from the data storage unit. An instruction execution unit that calculates and outputs a read address of the data storage unit; and an external data read unit that reads the stored data of the read address from the data storage unit when the instruction instructs the read. Register writing means for writing the read data to the register when the instruction instructs the read, Serial instruction decode unit, said instruction execution means, the external data reading means and the register write means can each parallel execution in a pipelined manner,
When the reading from the data storage means is executed, the read address is used as a temporary storage address, and the read data is further stored as temporary storage data. When the temporary storage addresses match, the temporary storage data in the temporary storage means can be read and the instruction can be executed.

Preferably, as in the parallel computer according to a second aspect, the instruction executing means changes the read instruction of the instruction to read the external data when the read address matches the temporary storage address. The reading processing by the means for the data storage means is invalidated.

[0029]

According to the first aspect of the present invention, the temporary storage storage means of the parallel computer according to claim 1 stores the read data as the temporary storage data and the temporary storage data when the reading from the data storage means is executed. Therefore, when the read address coincides with the temporary storage address, the instruction execution means can read the temporarily stored data in the temporary storage means and execute the instruction.

Therefore, when the first instruction to be executed first instructs the reading from the data storage means and the second instruction to be executed later instructs the processing using the read data of the first instruction, The second instruction does not wait for the read data of the first instruction to be stored in the register,
The instruction can be executed by reading the stored data stored in the temporary storage means.

[0031]

【Example】

<First Embodiment> FIG. 1 is a block diagram showing in detail the internal structure of a RISC according to the first embodiment of the present invention.
The RISC shown in FIG. 1 is an instruction memory 1 for storing instructions.
A register file 2 composed of a plurality of registers for temporarily storing data, a data memory 3 for storing data, and an instruction fetch stage 4, which is a pipeline stage of 5 stages, It is composed of an instruction decode stage 5, an execution stage 6 ', a memory access stage 7 and a write back stage 8. In addition, the memory data storage unit 9 is configured to be accessible to the execution stage 6 '.

The RISC read process is performed in units of one word (4 bytes) from the data memory 3. Also,
The RISC operates in response to externally applied two-phase non-overlap clock signals φ1 and φ2. Since the basic operation is the same as that of the conventional signals φ1 and φ2 shown in FIG. 10, description thereof will be omitted.

The instruction fetch stage 4 has a program counter 40, and supplies the address signal generated from the program counter to the instruction memory 1. The instruction designated by the applied address signal is fetched by the instruction fetch stage 4 and sent to the instruction decode stage 5.

The instruction decode stage 5 receives the instruction 50 from the instruction memory 1 via the instruction fetch stage 4 and decodes the instruction. And instruction decoding
Based on the decoding result of the instruction, the stage 5 is an instruction to which the execution stage 6 is given if necessary, when the given instruction can be executed in the next execution stage 6'without waiting. The data used to execute the above is read from the register filter 2, and the read data is given to the execution stage 6.

The execution stage 6'comprises a memory / address comparator 10 for comparing the operation result MA output from the operation executor 13 with the address SMA held in the memory data storage unit 9, and the instruction code of the preceding instruction. According to OP, the storage address D of the preceding instruction and the source address S3
1 and S32 respectively, and a register file address comparator 11 for outputting selection signals S1 and S2 which are comparison results, and selection signals S1 and S2, a coincidence signal G
Register file that selects data in response to ET
A data selector 12, an operation executor 13 that executes an operation based on the selected data, and registers 16 and 19
And 21. The instruction 50 given from the decode stage 5 includes an instruction code OP, two source addresses S31 and S32, and a storage address D.

Register file / address comparator 11
Is the storage address D of the preceding instruction via the register 19,
The source addresses S31 and S32 of the current instruction are received, the source addresses S31 and S32 are respectively compared with the storage address D2, a match / mismatch is detected, and the selection signals S1 and S2 are sent to the register file data selector 12. Output to. The details will be described later.

The storage register 16 holds the instruction code OP given from the decode stage 5. The held instruction code OP is given to the register 17 and the memory address comparator 10 in the memory access stage 7.

The storage register 19 holds the storage address D given from the decoding stage 5. The held storage address D is given to the register file address comparator 11 and the register 20 in the memory access stage 7.

Register file data selector 1
2 receives the two data R1 and R2 given from the register file 2 and the memory data DATA obtained from the memory address comparator 10.
And register file data selector 12
Operates in response to the selection signals S1 and S2 and the coincidence signal GET provided from the register / address comparator 11. Details will be described later.

The operation executor 13 uses the register file data selector 1 via the data buses 23 and 24.
2 is connected to perform operation based on the operation code OP using the given data. The execution result MA of the operation is calculated by the register 21, the memory / address comparator 10 and the data.
It is given to the memory 3. Details will be described later.

The memory / address comparator 10 receives the instruction code OP, the memory address SMA and the memory data MD stored in the memory data storage unit 9, and the operation result MA calculated by the operation executor 13. Receive. This calculation result MA becomes a read address at the time of reading. Then, the memory / address comparator 10 compares the address SMA with the operation result MA and detects a match / mismatch. Details will be described later.

Memory access stage 7 includes a register 17 for holding an instruction code, a register 20 for holding a storage address, and a data register 22 for holding operation result data. In the write-back stage 8, the data of the register 22 holding the execution result data is written in the register file 2 according to the address of the given storage address 20.

FIG. 2 shows an example of the configuration of the register file / address comparator 11 shown in FIG. The register file / address comparator 11 includes a match detector 111 and a match detector 112.

The coincidence detector 111 selects the H / L selection signal S based on the coincidence / non-coincidence between the storage address D of the preceding instruction obtained from the register 19 and the source address S31.
1 is output to the register file data selector 12. The coincidence detector 112 determines the storage address D of the preceding instruction.
Based on the match / mismatch with the source address S32, the H / L selection signal S2 is output to the register file data selector 12.

Register file data selector 1
An example of the configuration of No. 2 is shown in FIG. The register file data selector 12 includes tri-state buffers 121 and 122 each having an output connected to the data bus 23,
Each output is composed of tri-state buffers 123 and 124 connected to the data bus 24, and AND gates 125 and 126.

The AND gate 125 determines whether or not the desired data is obtained from the memory / address comparator 10 at H / H level.
The match signal GET indicated by L and the selection signal S1 from the register file / address comparator 11 are input and the output thereof is used as the control signal GS1.
Output to 1 and 123. The AND gate 126 inputs the coincidence signal GET and the selection signal S2, and outputs the output as the control signal GS2 to the tri-state buffers 122 and 124.

The tri-state buffer 121 is controlled to be active / inactive based on H / L of the inverted signal of the control signal GS1, and the data R supplied from the register file 2 is controlled.
Receive 1 in the input section. Tri-state buffer 123
Is activated based on H / L of the inverted signal of the control signal GS2.
The deactivation is controlled, and the data R2 given from the register file 2 is received at the input section.

Further, the tri-state buffer 122 is
Activation / deactivation is controlled based on H / L of the control signal GS1, and the input unit receives the data MD obtained from the memory data storage unit 9. Tri-state buffer 124 is controlled by control signal GS2 memory address activation / deactivation, and receives data MD obtained from memory data storage 9 at its input.

In the register file data selector 12 having such a configuration, when the selection signal S1 is provided at H level and the coincidence signal GET is provided at H level, the control signal GS1 becomes H level. The tri-state buffer 122 becomes active and the data MD
Is output to the data bus 23. At this time, since the tri-state buffer 121 is inactive, the output is in the high impedance state. Then, the selection signal S2 is H
When the control signal GS2 goes high when the match signal GET is given at level H and the coincidence signal GET is given at level H, the tri-state buffer 124 is activated.
D is output to the data bus 24. At this time, the tri-state buffer 123 is in the inactive state, so that the output is in the high impedance state.

On the other hand, when one of the selection signal S1 and the coincidence signal GET is given at the L level, the control signal GS1 goes to the L level, so that the tri-state buffer 121 is activated and the data R1 is transferred. Data bus 2
Output to 3. At this time, the tri-state buffer 12
Since 2 is inactive, the output is in a high impedance state. Then, the selection signal S2 and the coincidence signal GET
When one of these signals is applied at the L level, the control signal GS1 goes to the L level, so that the tri-state buffer 123 is activated and the data R2 is output to the data bus 24. At this time, tri-state buffer 1
Since 24 is inactive, the output is in a high impedance state.

FIG. 4 shows an example of the configuration of the arithmetic execution unit 13.
The operation executor 13 has registers 131 and 132 for holding the data obtained via the data buses 23 and 24, respectively.
And an arithmetic unit 133 that executes an operation based on the instruction code OP using the data held by the registers 131 and 132. Therefore, when the instruction code OP instructs the read operation, the operation result MA of the operator 133 becomes the read address.

FIG. 6 shows an example of the structure of the memory / address comparator 10. The memory / address comparator 10 includes a coincidence detector 101 and a data creation unit 102.

The coincidence detector 101 receives the memory address MA stored in the memory data storage unit 9, the operation result MA calculated by the operation executor 13, and the instruction code OP, respectively. Then, the coincidence detector 101
When the instruction code OP is a memory read instruction,
A match / mismatch between the held memory address SMA and the operation result MA that is a read address is detected, and H / L is set based on the match / mismatch, and a match signal GET indicating that data has been obtained is generated. Further, the coincidence detector 101 is a byte indicating H / L indicating which byte in the data MD of 1 word (4 bytes) is the coincident portion based on the read content of the instruction code OP. The selection signals B1 to B4 are output to the data creation unit 102.

The data generator 102 uses the byte selection signal B
1 to B4 and the data MD stored in the memory data storage unit 9 are received. Then, for example, when the selection signal B1 is H
At the level, when the selection signals B2 to B4 are at the L level,
The data bus signal DATA is generated by shifting the upper 1 byte of the data MD to the lower byte. The match signal GET and the data signal DATA are supplied to the register file data selector 12.

An example of the configuration of the memory data storage unit 9 is shown in FIG.
Shown in. The memory data storage unit 9 includes a data memory 91, which is a primary memory that temporarily holds an address of a load (read) instruction, and a data memory 92, which is a primary memory that temporarily holds memory data. . Address memory 92 receives instruction code OP and memory address MA. When the instruction code OP is a load (read) instruction, the address memory 91 holds an address whose bits are masked under the memory address MA. If it is a store instruction, it is reset.

The data memory 91 is connected to the memory bus and holds the data LD output from the data memory 3 as the data MD. The held data MD is given to the memory / address comparator 10.

The operation of the first embodiment will be described below with reference to FIG. In the following description, FIG.
It is assumed that the RISC shown in FIG. 11 executes the instruction 1 and the instructions 2 and 3 described with reference to FIG.

That is, three instructions are sequentially given and processed in the order of instruction 1 (byte unit load (read) instruction), instruction 2 (byte unit load (read) instruction), and instruction 3 (arithmetic instruction). In addition to this, a part of the data read from the data memory 3 in the instruction 1 is used in the instruction 2
Is read, and the data read by executing the instruction 2 is used in the processing of the instruction 3.

The instruction 1 is processed in the instruction fetch stage 4 in the period T1 and processed in the instruction decode stage 5 in the period T2. The processing of the instruction 1 in the execution stage 6 ', the memory access stage 7 and the write back stage 8 is executed in the periods T3, T4 and T5, respectively.

On the other hand, for the instruction 2, the instruction fetch stage 4 is executed in the period T2, and the instruction 2 is processed in the instruction decode stage 5 in the period T3.

In the period T4, the calculation result MA, which is a memory address, is calculated by the calculation executor 13, and the memory address SMA of the memory data storage unit 9 is compared by the memory address comparator 10.

As a result, since the memory address MA read in the instruction 1 and the address SMA stored in the memory data storage unit 9 match, the H-level match signal GET indicates the memory address comparator 10 as the match signal GET. Generated by.

In the instruction 3, the instruction fetch stage 4 is executed in the period T3, and in the period T4, the processing of the instruction 2 in the instruction decode stage 5 is performed. In the period T5, the data of the instruction 2 has already been obtained in the memory data storage unit 9. Therefore,
In the period T5, as the execution stage 6'of the instruction 3, the operation executor 13 can perform the operation processing by using the data DATA output from the memory / address comparator 10. Hereinafter, this point will be described in detail.

In the execution stage 6'of the instruction 2, the memory address comparator 10 determines the memory address SMA of the data read by the instruction 1 stored in the memory data storage unit 9 and the memory address of the instruction 2 Is compared with the calculation result MA. At this time, the instruction code OP of the instruction 2 is referred to, the instruction code OP is a load (read) instruction, and the address match is detected.
A level coincidence signal GET is generated. In addition, memory
The address comparator 10 extracts a necessary portion from the data stored in the memory data storage unit 9 and outputs the data DAT.
Output as A. Therefore, the required data is the data DA
Register file data selector 1 as TA
2 is transferred.

In the execution stage 6'of the instruction 3, the register file address comparator 11 determines the storage address D of the instruction 2 and the source address S included in its own instruction 3.
31 and S32 are compared and selection signals S1 and S2 are output. At this time, since the instruction 3 is an instruction for performing arithmetic processing using the data read by the instruction 2, the selection signal S1,
At least one of S2 becomes H level.

Further, the register file data selector 12 sends the data DATA to the data bus 23 in response to the selection signals S1 and S2 and the H level coincidence signal GET indicating that the memory data has been obtained. give. That is, since data selection signal S1 or S2 is applied at H level and coincidence signal GET is applied at H level, data DATA is applied to data bus 23 or 24 in accordance with the signal line.

Therefore, the data read by the command 2 can be immediately used by the command 3, and the command 3 can be used as shown in FIG.
There is no need to provide a standby state as in the conventional example shown in. That is, referring to FIG. 11C, at the end of the period T4, the read data of the instruction 2 can be obtained, and the obtained data is given to the instruction 3 as the data DATA. The instruction 6 can be processed by the stage 6 '.

As a result, the processing of the instruction 3 can be efficiently performed, so that the processing capability of the RISC can be improved.

<Second Embodiment> FIG. 7 is a block diagram showing in detail the internal structure of a RISC according to a second embodiment of the present invention. As shown in the figure, in addition to the first embodiment, the execution stage 6 '' of the second embodiment changes the instruction in response to the coincidence signal GET indicating that data has been obtained. It further has a container 25. FIG. 8 shows an example of the configuration of the instruction changer 25. The instruction changer 25 includes a register 251 that holds a register file write instruction and a selection circuit 252. The selection circuit 252 receives the coincidence signal GET given from the memory / address comparator 10 and the instruction code OP given from the register 16. The selection circuit 252 is controlled by the coincidence signal GET. For example, when the match signal GET is at the H level, the selection circuit selects the instruction code instructing the read instruction invalidity (change instruction) held in the register 251, and writes it in the register 17 of the memory access stage 7. On the other hand, when the coincidence signal GET is at L level, the instruction code OP is written in the register 17 as it is.

Other configurations and basic operations are the same as those in the first embodiment, and will not be repeated. Only the operation different from that of the first embodiment will be described below.

In response to the coincidence signal GET, the instruction changer 25 selects either the instruction code OP obtained from the register 16 or the change instruction stored in the register 251 and indicating the invalidation of the read instruction. That is, when the match signal GET is at the H level, the selection circuit 252 selects the change instruction held in the register 251,
It is written in the register 17.

As a result, already in the execution stage 6 '',
When a read instruction such as the instruction 2 read from the memory data storage unit 9 is executed, the instruction is made so that the read processing from the data memory 3 is not performed again in the next memory access stage 7. Since it can be changed, useless execution of memory access processing can be prevented.

[0073]

According to the first aspect of the present invention, the temporary storage storage means of the parallel computer according to claim 1 uses the read address as the temporary storage address and the read data as the temporary storage data when reading from the data storage means. When the read address matches the temporary storage address, the instruction executing means can read the temporarily stored data in the temporary storage storage means and execute the instruction.

Therefore, when the first instruction to be executed first instructs the reading from the data storage means and the second instruction to be executed later instructs the processing using the read data of the first instruction, The second instruction does not wait for the read data of the first instruction to be stored in the register,
The instruction can be executed by reading the stored data stored in the temporary storage means.

As a result, the time required to process the second instruction is shortened as compared with the conventional technique, and efficient data processing can be performed to improve the processing capability.

Further, the first instruction executed first instructs reading from the first address of the data storage means, and the second instruction executed later also reads from the first address of the data storage means. When instructing the reading, the second instruction can read the stored data stored in the temporary storage storage unit without accessing the data storage unit. Therefore, when the read address coincides with the temporary storage address (successful reading from the temporary storage storage means), the instruction execution means of the parallel computer according to claim 2 changes and reads the instruction given to the external data reading means. By invalidating the instruction, it is possible to eliminate the waste of the reading process from the data storage unit by the external data reading unit.

As described above, when the first instruction and the second instruction read the same address, the read instruction accesses the same address like RISC, and is a byte unit or half-byte unit. Even in the case of an instruction to read data with, it is relatively likely to occur in a parallel computer of the type that always reads data in units of multiple bytes and extracts the necessary part, so it is very effective in improving processing efficiency. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal configuration of a RISC that is a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a register file address comparator shown in FIG.

3 is a circuit diagram showing a configuration example of a register file data selector shown in FIG.

FIG. 4 is an explanatory diagram showing a configuration example of the arithmetic execution unit shown in FIG.

5 is an explanatory diagram showing an internal configuration example of a memory data storage section shown in FIG. 1. FIG.

6 is a block diagram showing a configuration example of a memory / address comparator shown in FIG. 1. FIG.

FIG. 7 is a block diagram showing an internal configuration of a RISC that is a second embodiment of the present invention.

8 is an explanatory diagram showing a configuration example of the instruction changer shown in FIG.

FIG. 9 is a block diagram showing a configuration of a conventional RISC.

FIG. 10 is a timing diagram showing a two-phase clock controlling a RISC.

FIG. 11 is an explanatory diagram showing the progress of pipeline processing by RISC according to the related art and the embodiment.

[Explanation of symbols]

 2 register file 3 data memory 6 ′ execution stage 6 ″ execution stage 9 memory data storage unit 10 memory address comparator 11 register file address comparator 12 register file data selector 13 operation executor 25 instructions Changer

Claims (2)

[Claims] 1. A register, a data storage means for storing data necessary for executing an instruction, an instruction decoding means for receiving an instruction code and decoding the instruction code, and a determination result based on a decoding result of the instruction decoding means. An instruction executing means for executing a read instruction from the data storage means, and executing and outputting the read address of the data storage means when the instruction stores the data stored in the register. And external data read means for reading the stored data of the read address from the data storage means when the instruction directs the reading, and writing the read data to the register when the instruction directs the reading. Register writing means, the instruction decoding means, the instruction executing means, the external data reading The read means and the register write means can be respectively executed in parallel in a pipeline manner, and when the read from the data storage means is executed, the read address is used as a temporary storage address and the read data is stored as a temporary storage data. The instruction execution means may read the temporary storage data of the temporary storage means and execute the instruction when the read address matches the temporary storage address. calculator. 2. The instruction executing means, when the read address matches the temporary storage address, changes the read instruction of the instruction to invalidate the read processing for the data storage means by the external data read means. The parallel computer according to claim 1.