JPH06208137A - Manufacture of thin film transistor matrix - Google Patents
Manufacture of thin film transistor matrixInfo
- Publication number
- JPH06208137A JPH06208137A JP364093A JP364093A JPH06208137A JP H06208137 A JPH06208137 A JP H06208137A JP 364093 A JP364093 A JP 364093A JP 364093 A JP364093 A JP 364093A JP H06208137 A JPH06208137 A JP H06208137A
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- Japan
- Prior art keywords
- film
- electrode
- substrate
- transparent
- storage capacitor
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- Thin Film Transistor (AREA)
Abstract
(57)【要約】
【目的】 薄膜トランジスタ(TFT) マトリクスの製法に
関し,2層目絶縁膜に開けるコンタクト孔を順テーパ形
状にし且つ基板表面の導通化を防止し,素子の信頼性と
製造歩留の向上を目的とする。
【構成】 透明絶縁性の基板 1上にゲート電極 2と蓄積
容量下部電極 3を形成し,その上に第1層目絶縁膜 4,
動作半導体層 5, チャネル保護膜 6を順次成膜し,ゲー
ト電極直上のチャネル保護膜を残し,基板上にコンタク
ト層 7と金属膜 8を順に成膜し,パターニングして, ド
レイン電極8Dと, ソース電極8Sと, 蓄積容量上部電極8C
を形成し,基板上に透明樹脂からなる第2層目絶縁膜 9
を被着し,第2層目絶縁膜にコンタクト孔を形成し,基
板上に透明電極膜を成膜して, 蓄積容量上部電極とソー
ス電極とにコンタクトをとり, パターニングして画素電
極11を形成するように構成する。
(57) [Abstract] [Purpose] Regarding the manufacturing method of a thin film transistor (TFT) matrix, the contact hole formed in the second insulating film is made into a forward tapered shape and the conduction on the substrate surface is prevented, and the reliability and the manufacturing yield of the device are improved. For the purpose of improving. [Structure] A gate electrode 2 and a storage capacitor lower electrode 3 are formed on a transparent insulating substrate 1, and a first insulating film 4,
The operating semiconductor layer 5 and the channel protection film 6 are sequentially formed, leaving the channel protection film directly above the gate electrode, and the contact layer 7 and the metal film 8 are sequentially formed on the substrate and patterned to form the drain electrode 8D and Source electrode 8S and storage capacitor upper electrode 8C
And the second insulating film made of transparent resin on the substrate.
Then, a contact hole is formed in the second insulating film, a transparent electrode film is formed on the substrate, the upper electrode of the storage capacitor and the source electrode are contacted, and the pixel electrode 11 is patterned. Configured to form.
Description
【0001】[0001]
【産業上の利用分野】本発明はアクティブマトリクス駆
動方式による液晶パネル等に構成される薄膜トランジス
タ(TFT) マトリクスの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (TFT) matrix formed in a liquid crystal panel or the like by an active matrix driving method.
【0002】近年,ラップトップパーソナルコンピュー
タや壁掛けテレビに使用するTFT マトリクス型液晶パネ
ルの開発が進められている。TFT マトリクス型液晶パネ
ルは表示品質がCRT と同等であることが認められつつあ
るが, 価格, 信頼性, 製造歩留の点で改善の余地が残さ
れている。In recent years, a TFT matrix type liquid crystal panel used for a laptop personal computer and a wall-mounted television has been under development. Although it is recognized that the TFT matrix liquid crystal panel has a display quality equivalent to that of a CRT, there is room for improvement in terms of price, reliability, and manufacturing yield.
【0003】[0003]
【従来の技術】アクティブマトリクス駆動方式による液
晶パネルはドット表示を行う個々の画素に対応してマト
リクス状にTFT を配置し,各画素にメモリ機能を持たせ
コントラスト良く多ラインの表示を可能としている。2. Description of the Related Art A liquid crystal panel based on an active matrix driving system has TFTs arranged in a matrix corresponding to individual pixels for dot display, and each pixel has a memory function to enable multi-line display with good contrast. .
【0004】図4はTFT マトリクスの平面図である。TF
T マトリクス型液晶パネルは, X,Y方向に交差してマ
トリクス状に配置された多数のゲートバスライン41とド
レインバスライン42に駆動電圧を印加して,両バスライ
ン交差部に接続されたTFT 43を選択駆動することによ
り, 対応する所望の画素をドット表示するように構成さ
れている。このようなTFT マトリクスの構造は, 例え
ば, 透明絶縁性のガラス基板上にチタン(Ti)−アルミニ
ウム(Al)からなる多数のゲートバスラインとドレインバ
スラインとが窒化シリコン(SiN) 等からなる層間絶縁膜
を介してX,Y方向に交差した形に配置され, 両バスラ
インの交差部にTFT が接続されている。また,TFT の動
作半導体層にアモルファスシリコン(a-Si)層を用いる場
合には,ゲート絶縁膜にプラズマ気相成長(P-CVD) 法に
よる窒化シリコン膜(SiN) あるいは窒化シリコンオキシ
ナイトライド(SiNO)膜が用いられていた。FIG. 4 is a plan view of the TFT matrix. TF
The T-matrix liquid crystal panel applies a driving voltage to a large number of gate bus lines 41 and drain bus lines 42 arranged in a matrix so as to intersect in the X and Y directions, and is connected to the intersections of both bus lines. By selectively driving 43, the corresponding desired pixel is displayed in dots. Such a TFT matrix structure is constructed, for example, on a transparent insulating glass substrate with a number of gate bus lines made of titanium (Ti) -aluminum (Al) and drain bus lines made of silicon nitride (SiN) or the like. The TFTs are connected to the intersections of both bus lines by arranging them so as to intersect in the X and Y directions via an insulating film. Moreover, when an amorphous silicon (a-Si) layer is used as the operating semiconductor layer of the TFT, a silicon nitride film (SiN) or a silicon nitride oxynitride (P-CVD) film is used as the gate insulating film. A SiNO) film was used.
【0005】なお,図中, 8DはTFT のドレイン電極, 8S
はTFT のソース電極, 8Cは蓄積容量上部電極(補助容量
バスライン)を示す。図5(A) 〜(F) は従来のTFT 素子
の製造工程を説明する断面図である。In the figure, 8D is the drain electrode of the TFT and 8S
Is the source electrode of the TFT, and 8C is the upper electrode of the storage capacitor (auxiliary capacitor bus line). 5 (A) to 5 (F) are cross-sectional views illustrating a conventional process for manufacturing a TFT element.
【0006】図5(A) において,透明絶縁性基板として
ガラス基板 1上にスパッタリングによりAl膜とCr膜を連
続して成膜し,フォトリソグラフィによりレジスト膜を
パターニングした後, レジスト膜をマスクにしてエッチ
ングしてゲート電極 2と蓄積容量下部電極 3を形成す
る。In FIG. 5 (A), an Al film and a Cr film are successively formed on a glass substrate 1 as a transparent insulating substrate by sputtering, the resist film is patterned by photolithography, and then the resist film is used as a mask. Then, the gate electrode 2 and the storage capacitor lower electrode 3 are formed by etching.
【0007】次いで, レジスト膜を剥離し,P-CVD 法に
より, 第1層目絶縁膜であるゲート絶縁膜および蓄積容
量誘電体膜としてSiN 膜 4, 動作半導体層としてa-Si膜
5,チャネル保護膜としてSiN 膜 6を連続成長する。こ
こで, 第1層目絶縁膜は,CVD SiN 膜 4の代わりに原子
層エピタキシ(ALD) 法によるアルミナ膜を用いてもよ
い。Then, the resist film is peeled off, and a P-CVD method is used to form a gate insulating film as the first insulating film and a SiN film as a storage capacitor dielectric film 4, and an a-Si film as an operating semiconductor layer.
5. SiN film 6 is continuously grown as a channel protective film. Here, as the first insulating film, an alumina film formed by an atomic layer epitaxy (ALD) method may be used instead of the CVD SiN film 4.
【0008】図5(B) において,ゲート電極 2の直上の
チャネル保護膜 6を残すようにパターニングする。図5
(C) において,基板上にコンタクト層として n+ 型a-Si
層 7とソースドレイン電極用金属膜 8を連続成膜する。In FIG. 5B, patterning is performed so that the channel protection film 6 immediately above the gate electrode 2 remains. Figure 5
In (C), n + type a-Si is used as a contact layer on the substrate.
The layer 7 and the source / drain electrode metal film 8 are continuously formed.
【0009】図5(D) において,コンタクト層 7とソー
スドレイン電極用金属膜 8をパターニングして, ドレイ
ン電極8Dと, ソース電極8Sと, 蓄積容量上部電極8Cを形
成する。In FIG. 5D, the contact layer 7 and the source / drain electrode metal film 8 are patterned to form a drain electrode 8D, a source electrode 8S, and a storage capacitor upper electrode 8C.
【0010】図5(E) において,第2層目絶縁膜14とし
て,P-CVD 法によりSiN 膜を成膜し,ソース電極8Sと蓄
積容量上部電極8C上にコンタクト孔を形成する。図5
(F) において,基板上に透明電極膜としてITO 膜を成膜
して, 蓄積容量上部電極8Cとソース電極8Sとにコンタク
トをとり, パターニングして画素電極11とし,TFT マト
リクスを形成する。In FIG. 5 (E), a SiN film is formed as the second layer insulating film 14 by the P-CVD method, and contact holes are formed on the source electrode 8S and the storage capacitor upper electrode 8C. Figure 5
In (F), an ITO film is formed as a transparent electrode film on the substrate, the storage capacitor upper electrode 8C and the source electrode 8S are contacted, and patterned to form the pixel electrode 11 and the TFT matrix.
【0011】[0011]
【発明が解決しようとする課題】第2層目絶縁膜 9は厚
さ3000〜4000Åに成膜するが,成膜条件により膜質は大
きく変わる。この膜質の変化により,この膜に, ドライ
またはウエットエッチングによりコンタクト孔を形成し
た際に, 図6のようにコンタクト孔の断面形状が順テー
パ,垂直,逆テーパの形が得られる。順テーパの場合は
特に問題はなく,ITO 膜11を成膜した際にコンタクト孔
を通して蓄積容量上部電極とソース電極とにコンタクト
をとることができるが,逆テーパの場合はコンタクトを
とることができず表示欠陥となる。The second insulating film 9 is formed to a thickness of 3000 to 4000 Å, but the film quality varies greatly depending on the film forming conditions. Due to this change in film quality, when a contact hole is formed in this film by dry or wet etching, the cross-sectional shape of the contact hole can be a forward taper, a vertical taper or a reverse taper, as shown in FIG. In the case of the forward taper, there is no particular problem, and when the ITO film 11 is formed, it is possible to make contact with the storage capacitor upper electrode and the source electrode through the contact hole, but in the case of the reverse taper, it is possible to make contact. Instead, it becomes a display defect.
【0012】また, 第2層目絶縁膜 9はモノシラン(SiH
4)とアンモニア(NH3) を主原料とする強い還元雰囲気中
で成膜されるため,下地に金属の化合物汚染が微量に残
留していても, これを還元して導通性異物を発生させ
る。そのため,基板表面が導通することがあった。The second insulating film 9 is monosilane (SiH
4 ) and ammonia (NH 3 ) are used as the main raw materials to form a film in a strong reducing atmosphere, so even if a small amount of metal compound contamination remains on the substrate, it will be reduced and conductive foreign matter will be generated. . As a result, the surface of the substrate sometimes became conductive.
【0013】本発明はTFT 素子の製造において,2層目
絶縁膜に開けるコンタクト孔を順テーパ形状にし且つ基
板表面の導通化を防止し,素子の信頼性と製造歩留の向
上を目的とする。It is an object of the present invention to improve the reliability of the device and the manufacturing yield by making the contact hole formed in the second insulating film into a forward tapered shape and preventing conduction on the substrate surface in the manufacture of the TFT device. .
【0014】[0014]
【課題を解決するための手段】上記課題の解決は, 1)透明絶縁性の基板 1上にゲート電極 2と蓄積容量下
部電極 3を形成し,その上に第1層目絶縁膜 4, 動作半
導体層 5, チャネル保護膜 6を順次成膜する工程と,次
いで, 該ゲート電極直上の該チャネル保護膜を残すよう
に, 該チャネル保護膜をパターニングする工程と, 次い
で,該基板上に高濃度半導体からなるコンタクト層 7と
ソースドレイン電極用金属膜 8を順に成膜する工程と,
次いで, 該コンタクト層と該ソースドレイン電極用金属
膜 8をパターニングして, ドレイン電極8Dと, ソース電
極8Sと, 蓄積容量上部電極8Cを形成する工程と, 次い
で, 該基板上に透明樹脂からなる第2層目絶縁膜 9を被
着する工程と, 次いで,該ソース電極上および該蓄積容
量上部電極上において,第2層目絶縁膜にコンタクト孔
を形成する工程と, 次いで,該基板上に透明電極膜を成
膜して, 該蓄積容量上部電極と該ソース電極とを該透明
電極膜にコンタクトをとり, 該透明電極膜をパターニン
グして画素電極11を形成する工程とを有する薄膜トラン
ジスタマトリクスの製造方法,あるいは 2)前記第2層目絶縁膜 9が, 熱硬化性樹脂または光硬
化性樹脂または感光性樹脂である前記1)記載の薄膜ト
ランジスタマトリクスの製造方法,あるいは 3)透明絶縁性の基板 1上に形成された画素電極11を覆
って透明絶縁膜を成膜する薄膜トランジスタマトリクス
の製造方法により達成される。[Means for Solving the Problems] 1) A gate electrode 2 and a storage capacitor lower electrode 3 are formed on a transparent insulating substrate 1, and a first insulating film 4, 4 The step of sequentially forming the semiconductor layer 5 and the channel protective film 6, and then the step of patterning the channel protective film so as to leave the channel protective film directly above the gate electrode, and then the high concentration on the substrate. A step of sequentially forming a contact layer 7 made of a semiconductor and a metal film 8 for source / drain electrodes,
Next, the contact layer and the source / drain electrode metal film 8 are patterned to form a drain electrode 8D, a source electrode 8S, and a storage capacitor upper electrode 8C, and then a transparent resin is formed on the substrate. A step of depositing a second-layer insulating film 9, then a step of forming a contact hole in the second-layer insulating film on the source electrode and the storage capacitor upper electrode, and then on the substrate. Forming a transparent electrode film, contacting the storage capacitor upper electrode and the source electrode with the transparent electrode film, and patterning the transparent electrode film to form a pixel electrode 11. Manufacturing method, or 2) The method for manufacturing a thin film transistor matrix according to 1), wherein the second insulating film 9 is a thermosetting resin, a photocurable resin, or a photosensitive resin. It is achieved by the method of manufacturing the thin film transistor matrix to form a transparent insulating transparent insulating film covering the pixel electrode 11 formed on the substrate 1.
【0015】[0015]
【作用】本発明では, 第2層目絶縁膜としてCVD SiN の
代わりに透明樹脂膜を用いる。これは本発明者が, 樹脂
膜はP-CVD 法に見られた成膜条件に依るコンタクト孔の
断面形状のばらつきがなく,逆テーパが形成されること
なく安定に塗布形成できることを確かめた結果を利用し
たものである。In the present invention, a transparent resin film is used instead of CVD SiN as the second insulating film. This is the result of the present inventor confirming that the resin film can be stably applied and formed without the reverse taper being formed without variation in the cross-sectional shape of the contact hole depending on the film forming conditions found in the P-CVD method. Is used.
【0016】また,樹脂であるため,金属化合物の残渣
の還元はなく, さらに回転塗布によるため樹脂表面が平
坦化される。Further, since it is a resin, the residue of the metal compound is not reduced, and the resin surface is flattened due to the spin coating.
【0017】[0017]
【実施例】 実施例(1) :図1(A) 〜(F) は本発明の実施例(1) の断
面図である。EXAMPLE Example (1): FIGS. 1 (A) to 1 (F) are sectional views of Example (1) of the present invention.
【0018】図1(A) において,透明絶縁性基板として
ガラス基板 1上にスパッタリングにより厚さ1000ÅのAl
膜と厚さ1000ÅのCr膜を連続して成膜し,フォトリソグ
ラフィによりレジスト膜をパターニングした後, レジス
ト膜をマスクにしてエッチングしてゲート電極 2と蓄積
容量下部電極 3を形成する。In FIG. 1 (A), a glass substrate 1 as a transparent insulating substrate is sputtered with a thickness of 1000 Å of Al.
The film and a Cr film with a thickness of 1000 Å are continuously formed, and after patterning the resist film by photolithography, the resist film is used as a mask for etching to form the gate electrode 2 and the storage capacitor lower electrode 3.
【0019】次いで, レジスト膜を剥離し,P-CVD 法に
より, 第1層目絶縁膜であるゲート絶縁膜および蓄積容
量誘電体膜として厚さ4000Åの窒化シリコン(SiN) 膜
4, 動作半導体層として厚さ 150Åのa-Si膜 5, チャネ
ル保護膜として厚さ1200ÅのSiN 膜 6を連続成長する。
ここで, 第1層目絶縁膜は, SiN 膜 4の代わりにALD法
によるアルミナ膜を用いてもよい。Next, the resist film is peeled off, and a P-CVD method is used to form a gate insulating film as the first insulating film and a silicon nitride (SiN) film having a thickness of 4000 Å as a storage capacitor dielectric film.
4. A 150-Å-thick a-Si film 5 as an operating semiconductor layer 5 and a 1200-Å-thick SiN film 6 as a channel protective film are continuously grown.
Here, as the first insulating film, an alumina film formed by the ALD method may be used instead of the SiN film 4.
【0020】図1(B) において,ゲート電極 2直上のチ
ャネル保護膜 6を残すようにパターニングする。図1
(C) において,基板上にコンタクト層として厚さ 600Å
の n+ 型a-Si層 7と厚さ1500Åのクロム(Cr)膜からなる
ソースドレイン電極用金属膜 8を連続成膜する。In FIG. 1B, patterning is performed so as to leave the channel protective film 6 directly above the gate electrode 2. Figure 1
In (C), the thickness of the contact layer on the substrate is 600Å
The n + type a-Si layer 7 and the metal film 8 for source / drain electrodes, which is made of a chromium (Cr) film having a thickness of 1500 Å, are continuously formed.
【0021】図1(D) において,コンタクト層 7とソー
スドレイン電極用金属膜 8をパターニングして, ドレイ
ン電極8Dと, ソース電極8Sと, 蓄積容量上部電極8Cを形
成する。In FIG. 1D, the contact layer 7 and the source / drain electrode metal film 8 are patterned to form a drain electrode 8D, a source electrode 8S, and a storage capacitor upper electrode 8C.
【0022】図1(E) において,第2層目絶縁膜 9とし
て,透明の熱硬化性樹脂膜を塗布し,キュア(熱処理)
を行う。熱硬化性樹脂は,例えばシリコン系またはエポ
キシ系熱硬化性樹脂を用い,回転塗布または印刷法によ
り塗布し,キュア後所定の厚さを 0.4μmにする。印刷
法の場合は基板上の接続端子に樹脂を付着しないように
してもよい。In FIG. 1 (E), a transparent thermosetting resin film is applied as the second insulating film 9 and cured (heat treatment).
I do. As the thermosetting resin, for example, a silicon-based or epoxy-based thermosetting resin is used, which is applied by spin coating or printing, and after curing, has a predetermined thickness of 0.4 μm. In the case of the printing method, the resin may not be attached to the connection terminals on the substrate.
【0023】次いで,フォトリソグラフィにより,ソー
ス電極と蓄積容量上に開口部を持つレジスト膜10を基板
上に形成する。図1(F) において,レジスト膜10をマス
クにして, 熱硬化性樹脂膜をエッチングしてコンタクト
孔を形成し,レジスト膜10を除去する。この際同時に接
続端子上の樹脂もエッチング除去する。Next, a resist film 10 having openings on the source electrode and the storage capacitor is formed on the substrate by photolithography. In FIG. 1F, the thermosetting resin film is etched using the resist film 10 as a mask to form contact holes, and the resist film 10 is removed. At the same time, the resin on the connection terminals is also removed by etching.
【0024】次に, 樹脂上に画素電極膜として厚さ 700
ÅのITO 膜を成膜して, 蓄積容量上部電極8Cとソース電
極8Sとにコンタクトをとり, パターニングして画素電極
11とし,TFT マトリクスを形成する。Next, a pixel electrode film having a thickness of 700 is formed on the resin.
Å ITO film is formed, contact is made to the storage capacitor upper electrode 8C and source electrode 8S, and patterning is performed.
11 to form a TFT matrix.
【0025】実施例(2) :実施例(1) では, 第2層目絶
縁膜 9として透明の熱硬化性樹脂膜を用いたが,これの
代わりに光硬化性樹脂, 例えば, UV樹脂を用い, 実施例
(1) と同様に成膜してもよい。Example (2): In Example (1), a transparent thermosetting resin film was used as the second insulating film 9, but instead of this, a photo-setting resin, for example, a UV resin was used. Use, Example
The film may be formed in the same manner as (1).
【0026】実施例(3):図2は本発明の実施例(3)の
断面図である。2層目絶縁膜 9として感光性樹脂,例え
ば感光性ポリイミド樹脂を用い, フォトマスク12を用い
て, 感光性ポリイミド樹脂をパターニングしてソース電
極8Sと蓄積容量上部電極8C上にコンタクト孔を形成す
る。Embodiment (3): FIG. 2 is a sectional view of an embodiment (3) of the present invention. A photosensitive resin, such as a photosensitive polyimide resin, is used as the second layer insulating film 9, and the photosensitive polyimide resin is patterned using a photomask 12 to form contact holes on the source electrode 8S and the storage capacitor upper electrode 8C. .
【0027】実施例(4):図3は本発明の実施例(4)の
断面図である。この例は,第2層目絶縁膜として本発明
の透明樹脂膜 9あるいは従来例のSiN膜14を用いてTFT
を形成した後, 基板表面に保護膜13として透明絶縁膜を
成膜するようにしている。この際, 接続端子上は保護膜
を成膜しないようにする。または成膜してもその後エッ
チング除去してもよい。保護膜13により基板表面は平坦
化され, 次工程が精度よく行える。Embodiment (4): FIG. 3 is a sectional view of an embodiment (4) of the present invention. In this example, the transparent resin film 9 of the present invention or the SiN film 14 of the conventional example is used as the second insulating film for the TFT.
After forming, the transparent insulating film is formed as the protective film 13 on the surface of the substrate. At this time, do not form a protective film on the connection terminals. Alternatively, the film may be formed or may be removed by etching after that. The surface of the substrate is flattened by the protective film 13, and the next step can be performed accurately.
【0028】次に実施例の効果を要約する。 (1) 2層目絶縁膜に樹脂膜を用いるため,成膜が容易
で, 成膜装置も簡単で小型化できる。また, 感光性樹脂
を用いた場合はレジストの塗布工程が省略できる。 (2) 樹脂は成膜条件が安定しているため,コンタクト孔
を形成する際に, 従来みられた逆テーパ形状をなくすこ
とができる。従って, コンタクト孔の形状が安定化する
ため,画素電極膜のITO 膜を成膜した際に断線を防止で
きる。 (3)樹脂であるため,金属酸化物の残渣の還元はなくな
り, 基板表面の導通を防止できる。 (4)樹脂膜は回転塗布に依るため基板表面を平坦化でき
る。 (5) 信頼性, 製造歩留が向上し,低価格化が実現でき
る。Next, the effects of the embodiment will be summarized. (1) Since a resin film is used for the second insulating film, film formation is easy, and the film formation device is simple and compact. Further, when a photosensitive resin is used, the resist coating step can be omitted. (2) Since the resin film formation conditions are stable, it is possible to eliminate the conventional inverse taper shape when forming contact holes. Therefore, since the shape of the contact hole is stabilized, disconnection can be prevented when the ITO film of the pixel electrode film is formed. (3) Since it is a resin, the reduction of the metal oxide residue is eliminated and conduction on the substrate surface can be prevented. (4) Since the resin film is applied by spin coating, the substrate surface can be flattened. (5) Reliability and manufacturing yield are improved, and cost reduction can be realized.
【0029】[0029]
【発明の効果】本発明によれば,TFT 素子の製造におい
て,第2層目絶縁膜に開けるコンタクト孔を順テーパ形
状に形成でき且つ基板表面の導通化を防止することがで
きた。この結果,本発明は素子の信頼性と製造歩留の向
上に寄与することができた。According to the present invention, in the manufacture of the TFT element, the contact hole formed in the second-layer insulating film can be formed in a forward tapered shape and the conduction on the substrate surface can be prevented. As a result, the present invention was able to contribute to the improvement of device reliability and manufacturing yield.
【図1】 本発明の実施例(1) の断面図FIG. 1 is a sectional view of an embodiment (1) of the present invention.
【図2】 本発明の実施例(3)の断面図FIG. 2 is a sectional view of an embodiment (3) of the present invention.
【図3】 本発明の実施例(4)の断面図FIG. 3 is a sectional view of an embodiment (4) of the present invention.
【図4】 TFT マトリクスの平面図[Figure 4] Plan view of the TFT matrix
【図5】 従来のTFT 素子の製造工程を説明する断面図FIG. 5 is a cross-sectional view illustrating a manufacturing process of a conventional TFT device.
【図6】 コンタクト孔の断面図FIG. 6 is a sectional view of a contact hole.
1 透明絶縁性基板でガラス基板 2 ゲート電極 3 蓄積容量下部電極 4 第1層目絶縁膜(ゲート絶縁膜および蓄積容量誘電
体膜)でSiN 膜 5 動作半導体層でa-Si膜 6 チャネル保護膜でSiN 膜 7 コンタクト層で n+ 型a-Si層 8 ソースドレイン電極用金属膜 8D ドレイン電極 8S ソース電極 8C 蓄積容量上部電極 9 第2層目絶縁膜で透明樹脂膜 10 レジスト膜 11 画素電極でITO 膜1 Transparent insulating substrate, glass substrate 2 Gate electrode 3 Storage capacitor lower electrode 4 First layer insulating film (gate insulating film and storage capacitor dielectric film) SiN film 5 Operating semiconductor layer a-Si film 6 Channel protective film With SiN film 7 n + type a-Si layer with contact layer 8 metal film for source / drain electrode 8D drain electrode 8S source electrode 8C storage capacitor upper electrode 9 second layer insulation film transparent resin film 10 resist film 11 pixel electrode ITO film
Claims (3)
(2) と蓄積容量下部電極(3)を形成し,その上に第1層
目絶縁膜(4), 動作半導体層(5) , チャネル保護膜(6)
を順次成膜する工程と,次いで, 該ゲート電極直上の該
チャネル保護膜を残すように, 該チャネル保護膜をパタ
ーニングする工程と,次いで,該基板上に高濃度半導体
からなるコンタクト層(7) とソースドレイン電極用金属
膜(8) を順に成膜する工程と,次いで, 該コンタクト層
と該ソースドレイン電極用金属膜をパターニングして,
ドレイン電極(8D)と, ソース電極(8S)と, 蓄積容量上部
電極(8C)を形成する工程と,次いで, 該基板上に透明樹
脂からなる第2層目絶縁膜(9) を被着する工程と,次い
で,該ソース電極上および該蓄積容量上部電極上におい
て,第2層目絶縁膜にコンタクト孔を形成する工程と,
次いで,該基板上に透明電極膜を成膜して, 該蓄積容量
上部電極と該ソース電極とを該透明電極膜にコンタクト
をとり, 該透明電極膜をパターニングして画素電極(11)
を形成する工程とを有することを特徴とする薄膜トラン
ジスタマトリクスの製造方法。1. A gate electrode on a transparent insulating substrate (1)
(2) and storage capacitor lower electrode (3) are formed, on which the first insulating film (4), operating semiconductor layer (5), channel protective film (6)
And a step of patterning the channel protective film so as to leave the channel protective film directly above the gate electrode, and then a contact layer (7) made of a high-concentration semiconductor on the substrate. And a source / drain electrode metal film (8) in that order, and then patterning the contact layer and the source / drain electrode metal film,
Step of forming drain electrode (8D), source electrode (8S) and storage capacitor upper electrode (8C), and then depositing a second layer insulating film (9) made of transparent resin on the substrate And a step of forming a contact hole in the second-layer insulating film on the source electrode and the storage capacitor upper electrode,
Then, a transparent electrode film is formed on the substrate, the storage capacitor upper electrode and the source electrode are contacted with the transparent electrode film, and the transparent electrode film is patterned to form a pixel electrode (11).
And a step of forming a thin film transistor matrix.
脂または光硬化性樹脂または感光性樹脂であることを特
徴とする請求項1記載の薄膜トランジスタマトリクスの
製造方法。2. The method of manufacturing a thin film transistor matrix according to claim 1, wherein the second insulating film (9) is a thermosetting resin, a photocurable resin or a photosensitive resin.
素電極(11)を覆って透明絶縁膜を成膜する工程を有する
ことを特徴とする薄膜トランジスタマトリクスの製造方
法。3. A method of manufacturing a thin film transistor matrix, comprising a step of forming a transparent insulating film so as to cover a pixel electrode (11) formed on a transparent insulating substrate (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP364093A JP3239504B2 (en) | 1993-01-13 | 1993-01-13 | Method of manufacturing thin film transistor matrix |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP364093A JP3239504B2 (en) | 1993-01-13 | 1993-01-13 | Method of manufacturing thin film transistor matrix |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06208137A true JPH06208137A (en) | 1994-07-26 |
| JP3239504B2 JP3239504B2 (en) | 2001-12-17 |
Family
ID=11563087
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP364093A Expired - Fee Related JP3239504B2 (en) | 1993-01-13 | 1993-01-13 | Method of manufacturing thin film transistor matrix |
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| Country | Link |
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| JP (1) | JP3239504B2 (en) |
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