JPH06197111A - Internetwork equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an internetwork device capable of high-speed relay. [Composition] In an internetwork device which connects a plurality of networks to each other and relays information from one network to another network, the internetwork device is provided corresponding to each network, and the information from the network is based on a destination. A relay processing unit 3 for relaying is provided, and the relay processing unit analyzes the destination of the information from the network by referring to the storage unit 342 that stores the relay route information corresponding to the destination and the storage unit 342. And an analysis processing unit 343 for outputting the analysis result, and a transfer processing unit 31 for transferring the information from the network to another corresponding relay processing unit based on the analysis result of the analysis processing unit 343.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internetwork system relay process for interconnecting a plurality of networks and an internetwork system.

[0002]

2. Description of the Related Art Conventionally, an internetwork device such as a router or a gateway has a communication port for connecting to a network and a processor for performing a routing process according to a protocol of each network. Take the configuration that you have. The routing process is performed as follows.

A packet received from a communication port connected to one network is stored in a buffer, a processor analyzes the destination address of the packet, and detects a destination device or an internetwork device in the direction in which the destination device is connected. , Routing processing is performed by selecting a communication port for transmitting the packet. Further, the packet is relayed by sending the packet from the corresponding port.

Further, since the internetwork device needs to support various networks, for example, from about 10 Mbps such as IEEE802.3 to about 100 Mbps such as FDDI (Fiber Distributed Data Interfase), and further ATM. (Asynchr
onous Transfer Mode) to 155 Mbps to 2.
Various communication ports will be prepared up to 4 Gbps.

There are several types of techniques for routing between networks, such as the IP protocol (Intern
et Protocol) is well known. In this IP protocol, an IP address is used as a logical address for internetworking. And the destination IP address,
The physical (MAC: Media Access Control) of the destination device or the internetwork device in the direction in which the destination device is connected.
l) Has a route information table that describes addresses,
Routing can be performed by referring to this.

As a technique for performing high-speed routing,
For example, as described in Japanese Patent Application Laid-Open No. 3-132131, efficient routing is performed by reading the header part and determining the destination before accepting a packet.

Further, as a technique for recognizing a received frame at high speed, for example, as described in Japanese Patent Laid-Open No. 2-238544, the next time based on the type of the frame already received or the frame transmitted by the own station, The frame receiving process is speeded up by predicting the type of the received frame and preparing the header part process of the received frame. Furthermore, as a technique for transferring the received packet data from the receiving side routing processor to the transmitting side routing processor, for example, Japanese Patent Laid-Open No. 62-82747 is used.
There is a technique described in Japanese Patent Publication No. 4-48302. In the prior art, there is provided a distributed packet switching system including a plurality of line control devices, wherein a logical channel number of each packet received from an incoming line and a line number and a logical channel number of an outgoing line from which the packet is sent out. Is stored in the packet switching control table, the header information is updated on the side of the line control device that has received the incoming line to the line number and logical channel number of the outgoing line of the transfer destination, and this is sent to the network. In other words, the line controller on the receiving side updates the packet header, adds a transfer header containing the logical identification number of the port on the transmitting side, and then adds it to the data path for data transfer between the line controllers. Transfer data is placed.

[0008]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
There are problems with the following points.

The method described in Japanese Patent Application Laid-Open No. 3-132131, which directly sends a packet to a destination node without accumulating the packet, is effective in a specialized simple routing control method, but has a large capacity. It is impossible to perform complicated routing such as searching the information table to determine the route and processing the packet such as changing the destination MAC address.

Further, in the prior art, since the routing processing for low speed communication and the routing processing for high speed communication are not standardized, the routing processing is performed according to each speed. For this reason, when trying to improve the performance of the system from low-speed communication to high-speed communication, much consideration has not been given to the fact that routing processing for high-speed communication must be newly added.

Furthermore, the conventional technique disclosed in Japanese Patent Laid-Open No. 3-132131 is effective in speeding up the routing of individual packets.
The conventional technique disclosed in Japanese Patent No. 238544 is effective for speeding up packet processing by predicting the header of the packet to be received next from the nature of the communication protocol. However, even when it becomes necessary to route a packet having the same destination as a packet that has been routed in the past, the route information must be searched again by the same procedure as in the past, which is a waste of processing.

Further, in the prior art disclosed in the above-mentioned Japanese Patent Laid-Open No. 62-82747, the logical line identification number (line number) of the transmitting side line control device is performed after all the routing processing is performed in the receiving side line control device. : Corresponds to RN.)
Is added to the packet, and the packet is sent to the transmission side line control device. In the packet switching system of the prior art, since only one line is connected to one line control device, the line number of the outgoing line can represent the line control device on the transmitting side. When an outgoing line (network interface port) is provided, the outgoing line controller of the sending side cannot recognize which outgoing line of the line controller the packet should be sent to. The method of specifying the outgoing line is not described in the related art.

An object of the present invention is to provide an internetwork device which enables high-speed routing processing in order to solve the above-mentioned problems of the prior art.

[0014]

SUMMARY OF THE INVENTION The present invention is an internetwork device for connecting a plurality of networks to each other and relaying information from one network to another network, the internetwork device being provided for each network. A relay processing unit that relays information from the network based on a destination of the information, and the relay processing unit refers to a storage unit that stores relay route information corresponding to the destination and the storage unit. Then, an analysis processing unit that analyzes the destination of the information from the network and outputs the analysis result, and a transfer that transfers the information from the network to another corresponding relay processing unit based on the output of the analysis processing unit. Processing means. The analysis processing means and the transfer processing means perform parallel processing. The analysis processing means outputs relay path information as an analysis result, and the transfer processing means adds the relay path information of the analysis processing means to the information from the network and transfers the information. The storage means further stores, as the relay route information, identification information regarding the output destination network of the relay processing section, and the transfer processing section receives the transferred information from another relay processing section and performs the analysis. The processing means analyzes the output destination based on the relay route information added to the transferred information and the identification information on the output destination of the storage means, and the transfer processing means transfers the output from another relay processing section. The obtained information is output to the output destination network analyzed by the analysis processing means.

The analysis processing means, when analyzing the output destination,
It is determined whether or not the destination stored in the storage means and the destination of the information from the network match. If they match, the analysis result is output, and the transfer processing means
Even when the output of the analysis processing means does not match the destination during the transfer processing, the information from the network can be transferred to another relay processing unit.

The relay processing section further has a shared storage means that can be read and written by the analysis processing means and the transfer processing means, and the shared storage means has relay route information corresponding to the destination analyzed by the analysis processing means. Can be memorized.

The relay processing section further has a judging means for judging whether or not the destination stored in the shared storage means and the destination of the information newly received from the network are coincident with each other. The processing means performs the analysis processing when the determination means determines that they do not match, and when the determination means determines that they match, the relay route information stored in the shared storage means is processed. Process to rewrite only the relay route information that cannot be reused.

The transfer processing means may further have a function of analyzing the destination of information from the network and outputting the analysis result.

The relay processing section further has a storage means for storing information from the network and a holding means for holding the destination of the information from the network, and the analysis processing means has the destination stored in the holding means. And the transfer processing means transfers the information accumulated in the accumulating means.

The storage means uses a value based on a predetermined hashing function as an address based on the numerical value indicating the destination, and the analysis processing means uses the numerical value indicating the destination when referring to the storage means. , The hashing value can be obtained and referred to.

Further, the relay processing section includes a plurality of ports connected to the network, and the storage means stores the logical identification number of the relay processing section corresponding to the destination and the logical identification information of the port of the relay processing section. Stored as relay route information,
The analysis processing unit outputs the relay route information as the analysis result, and the transfer processing unit outputs the information transferred from another relay processing unit to the relay route information output by the analysis processing unit. It can be added and output to the output destination network.

A relay processing circuit that is mounted on an internetwork device that connects a plurality of networks to each other and relays information from one network to another network, is provided corresponding to each network. The relay processing circuit refers to the storage unit that stores the relay route corresponding to the destination, and analyzes the destination of the information from the network by referring to the storage unit, and outputs the analysis result.
And a second processor that transfers information from the network to another corresponding relay processing unit based on the analysis result of the first processor.

A relay processing circuit which is mounted on an internetwork device which connects a plurality of networks to each other and relays information from one network to another network, the relay processing circuit being provided corresponding to each network. The processing circuit includes a storage unit that stores the relay route corresponding to the destination, a first processor that refers to the storage unit, analyzes the destination of the information from the network, and outputs the analysis result, and the first processor. A second processor that transfers information from the network to another corresponding relay processing unit based on the analysis result of the one processor may be provided.

In a network system having a plurality of networks and an internetwork device that connects the networks to each other and relays information from one network to another network, the internetwork device is the information from the network. Has a relay processing unit for relaying based on a destination corresponding to each network, and the relay processing unit is connected by a bus,
The relay processing unit analyzes the destination of the information from the network and outputs the analysis result, and the information from the network to other corresponding relay processing units based on the analysis result of the analysis processing unit. It is possible to perform distributed processing of transfer processing for transferring

In an internetwork device that connects a plurality of networks to each other and relays information from one network to another network, the internetwork device is provided corresponding to each network, and the information from the network is based on a destination. A relay processing unit for relaying, each of the relay processing units being connected to a common bus, for dividing information from a network connected to the own relay processing unit into blocks of fixed length; Adding means for adding the identification information of the corresponding relay processing unit based on the destination to each of the blocks divided by; sending means for sending the block to which the identification information is added by the adding means to the bus; The receiving unit that receives the block to which the identification information of the own relay processing unit is added from the bus and the block that is received by the receiving unit are separated. If the information that is, may have a unified means for integrating the blocks that are the divided. In this case, the capacity of the information is added to the information in advance, and the integrating means performs integration of the divided blocks based on the capacity added to the information in advance. Good.

Further, the first relay processing unit excludes the reception of information from the relay processing units other than the first and second relay processing units when receiving the information from the second relay processing unit. The second relay processing unit is provided with an exclusive control unit for performing exclusive control, and when the information is transmitted to the first relay processing unit,
The first relay processing unit is provided with a transfer control unit for confirming whether or not the information is received, and notifying that the information is to be transmitted if the information is not received, When notified by the transfer control unit of the second relay processing unit, the exclusive control unit receives only the information from the relay processing unit.

[0027]

The relay processing unit of the internetwork device receives the information from the network connected to each of them. In the relay processing unit, the received information is stored in the storage unit (packet buffer memory), and the information about the destination is stored in the storage unit (header memory). The analysis processing unit refers to the storage unit (route information table) that stores the relay route information corresponding to the destination, analyzes the destination held in the holding unit, outputs the analysis result, and outputs the analysis result. Store in the shared storage means.

The transfer processing means reads the shared storage means and transfers the information stored in the storage means to another corresponding relay processing section based on the analysis result of the analysis processing means. The transfer processing means adds relay route information to the information from the network as an analysis result of the analysis processing means and transfers the information.

In the other relay processing unit, the transfer processing unit receives the transferred information from the relay processing unit, and the analysis processing unit refers to the storage unit and adds the transferred information to the transferred information. The output destination is analyzed from the existing relay route information, and the transfer processing means outputs the information transferred from another relay processing section to the output destination network analyzed by the analysis processing means.

Further, when the relay processing section further has a judging means for judging whether or not the destination stored in the shared storage means and the destination of the information newly received from the network coincide with each other, the analysis is performed. The processing means performs the analysis processing when the determination means does not match, and when the determination means matches, rewrites only the route information that cannot be reused in the shared storage means. As a result, the routing process can be speeded up.

The relay processing units are respectively connected by a bus and divide the information from the network into fixed-length blocks, and correspond to each block divided by the dividing unit based on the destination. Adding means for adding identification information of the relay processing section, sending means for sending the block to which the identification information is added by the adding means to the bus, and receiving the block to which the identification information of the own device is added from the bus In the case where the receiving means and the integrating means for integrating the divided blocks when the block received by the receiving means is the divided information, there are the following effects.

The second dividing unit of the relay processing unit divides the information from the network into fixed-length blocks. The adding unit adds the identification information of the corresponding relay processing unit to each block divided by the dividing unit based on the destination. The sending means sends the block to which the identification information is added by the adding means to the bus.

In the first relay processing section on the receiving side, the receiving means receives the block to which the identification information of the own device is added from the bus. The integrating means integrates the divided blocks when the information received by the receiving means is the divided information. The integrated information is sent to the network connected to the first relay processing unit.

Further, in order to exclude the reception of other information at the time of transferring the block, an exclusive control means and a transfer control section can be provided. In this case, the transfer control unit of the second relay processing unit determines whether or not the exclusive control unit of the first relay processing unit on the receiving side receives the information at the time of sending to the first relay processing unit. If the information is not received, it is notified that the information will be sent. Upon receipt of the notification from the transfer control unit of the second relay processing unit on the transmission side, the exclusive control unit receives only the information from the second relay processing unit, and When the information is received, exclusive control is performed to exclude the reception of information from the relay processing units other than the first and second relay processing units. As a result, the blocks transmitted from the plurality of relay processing units are not mixed and the processing can be simplified.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

First, the overall architecture of the internetwork device will be described.

The internetwork apparatus according to the present embodiment is characterized in that it has a plurality of routing modules (relay processing units) provided corresponding to the network, and adopts an architecture in which the performance can be easily improved by adding modules. That is. Each of the plurality of modules has a routing processor that analyzes an address and performs a routing process. Further, the routing processor is configured to have one or a plurality of communication ports, respectively.

The block diagram shown in FIG. 2 is an overall block diagram of the router. In FIG. 2, reference numeral 1 is a router bus, which has a throughput of, for example, 200 MBytes / sec. The router bus 1 is connected to a management unit 2 having a management function for the entire apparatus and a function for collecting and distributing routing information. Also, on the router bus 1,
Modules can be connected from 1 to 8 modules. Each module has a routing processor 3 having a function of performing high-speed routing. The management unit 2 sets the routing information in the routing processor 3, and each routing processor 3 realizes a router by performing the routing operation based on the routing information. Furthermore, under each routing processor 3,
Communication control units 51 to 53 having communication ports for connecting to a network are connected. The communication control unit can be connected to each type of network. Where for example
High-speed communication port of 100 Mbps class like FDDI
Basically, only one port can be connected per routing processor. Similarly, in the case of high-speed communication such as a 155 Mbps leased line or 155 Mbps ATM, only one port is connected to the routing processor 3. In addition, for example, IEEE802.3 (CSMA / C
D), IEEE802.5 (token ring LAN), N-ISDN, or the like, in the case of medium to low speed communication, one routing processor is connected to a plurality of (1 to 4 ports) medium to low speed ports. That is, in the case of medium and low speed communication, one routing processor can connect a plurality of networks.

The configuration of the routing processor 3 will be outlined with reference to FIG. In FIG. 2, the routing processor 3 controls a μP (microprocessor) 31 that performs routing processing, a memory 33 that includes a packet buffer that stores packets and a routing table that stores route information, and controls the memory 33 and the μP 31. It has a control circuit 32 that interfaces with the communication control unit. The memory 33 is a storage unit that stores the received packets and a storage unit that holds the header portion indicating the destination information. Here, the routing table is described as being stored in the memory 33.
It is also possible to prepare a local memory directly connected to P31 and store the routing table in the memory. The data structure of the routing table is shown in FIG.
The packet transfer format for transfer is shown in FIG. Details will be described later.

Next, the flow of routing processing in the routing processor 3 will be described. In addition,
As a pre-process of the routing process, the management unit 2 distributes the routing information to all the routing processors 3 to each routing table, and each routing processor 3 has the routing information in the area of the routing table in the memory 33. It is in the state of being. For example, the collection of the routing information of the management unit 2 is performed by exchanging it with another internetwork device by a routing protocol such as RIP or OSPF, or by statically setting in advance by the user. . The communication control unit 51 transfers the packet received from the LAN 71 to the memory 33, and the packet buffer of the memory 33 stores the received packet. The μP 31 detects the header portion of the stored packet and refers to the routing table to perform the routing process. For example, when the destination is the line 72, this packet is transferred from the routing processor 3 (a) to the routing processor 3 (b). In addition, for example, if the destination is the own device, it is transferred to the management unit 2. For example, the destination is LA
For N71, that is, its own routing processor 3
If it is under (a), discard it.

Next, a method of dealing with the case where the performance of the above internetwork apparatus is improved will be described.

High performance is required in the following cases.

(1) When the routing capacity is insufficient because the routing processor has a plurality of medium / low speed communication control units.

(2) When the high-speed communication control unit is connected to the routing processor, the high-speed routing must be performed.

FIG. 1 shows a configuration for improving performance. In FIG. 1, a routing assist unit 34 is added to the routing processor 3. The routing assist unit 34 is an analysis processing unit that analyzes the destination of information from the network and outputs an analysis result, performs processing related to routing, and shares the processing with the μP 31.
In this case, the μP 31 has at least the function of a transfer processing unit that transfers information from the network to another corresponding relay processing unit based on the analysis result of the routing assist unit 34. The flow of routing in such a configuration will be described by taking IP routing as an example.

In FIG. 1, the routing processor basic unit (the part of the routing processor 3 other than the routing assist unit 34 is hereinafter referred to as the routing processor basic unit) mainly performs the process related to packet transfer. The processing contents of the routing processor basic unit include packet transfer control between the communication control unit 61 and the memory 33, packet buffer control in the memory 33, packet processing, packet transfer control between the routing processor and other routing processors, routers. Information exchange with the management unit 2, drive of the communication control unit 61, trace / statistics, etc. are performed.

As the process sharing of the routing assist unit 34, the process related to the routing including the search of the routing table is performed. The contents of the processing include the processing of extracting the header portion from the received packet, the processing of determining the communication protocol from the extracted header portion, and if the determined communication protocol is TCP / IP, the routing table is searched and the next hop (next This is a process of obtaining an IP address of an internetwork device of the local network) and notifying it to the μP 31 of the routing processor basic unit. Here, if the communication protocol is not TCP / IP, the routing process is not performed. TCP /
It is also possible to realize a multi-protocol router by causing the routing assist unit 34 to perform a plurality of protocol processes such as OSI other than IP. In the above description, if the communication protocol is other than TCP / IP, the routing process is not performed. However, by providing the routing assist unit 34 with the bridge assist function, when the protocol of the received packet is not supported. Can also be operated as a bridge. FIG. 4 shows a processing share and a processing flow of the routing processor basic unit and the routing assist unit 34 when the routing assist unit 34 is added. When the routing assist unit 34 is added, if the routing table is stored in the memory 342 of the storage unit, the routing process can be performed at higher speed.

Next, the routing process in such a basic configuration will be described.

The communication control unit 61 transfers the packet received from the high speed LAN 74 to the memory 33 and stores it. on the other hand,
During this transfer, the routing assist circuit 343 extracts the packet header useful in the routing processing and the reception status added by the communication control unit 61, and the memory 3
42, the memory 342 stores the extracted packet header and reception status. During this transfer, the routing assist circuit 343 analyzes the packet header in parallel. Details of the header analysis items will be described later. The routing table is stored in the memory 34 in advance.
It shall be constructed and defined in 2. Also, μP
The memory 342 also shares the instruction and work area for 341. Since the memory 342 has a smaller capacity than the packet buffer memory 33, a high-speed memory can be used and the processing performance can be improved. μP341
Performs routing processing from the information in the header stored in the memory 342, and passes the result to the μP 31. The procedure for passing is, for example, to the routing assist circuit 343,
A dual port memory that can be accessed from both μP341 and μP31 is provided, and after μP341 writes the result data to the area of this dual port memory, μP31
Is interrupted, and the μP 31 reads this written data. Further, by configuring the routing table cache by using this area as a structure like a cache memory, it is possible to significantly reduce the processing such as the routing table search at the time of hit, so that the processing speed can be increased. Details will be described later. It should be noted that, as the content of the result, the sequence of the received packet (the number for associating the packet body stored in the memory 33 with the header stored in the memory 342) information and the packet are valid / invalid. There is information about that. Further, as an example of the IP routing as the content of the result, it is composed of attributes such as frame type, destination IP address, subnet mask, next router IP address, destination interface number (ID of routing processor and communication control unit), and the like. . This will be described later. The μP 31 takes over this result and performs processing such as replacing the packet header on the packet previously stored in the memory 33. Then, it is transferred to the routing processor corresponding to the destination port.

Next, details of the routing assist unit 34 will be described with reference to FIGS. 1 and 3. FIG. 3 shows a configuration diagram of the routing assist unit 34.

In FIG. 3, the assist circuit 343 receives the latch timing control signal (a) and the packet header and reception status data (b) from the control circuit 32, and is connected to the μP31 via the μP31RP interface and bus. ing. The assist circuit 343 analyzes a header of each packet and outputs the result, a memory 342 of a storage unit that stores the packet header and the analysis result, and a μP 341 that performs a routing process.
Processing unit. Further, the assist circuit 343 is
FIFO 34 as a holding means for temporarily holding the packet header
312, and dual port memory 34316 of shared storage means for storing when transferred to the μP 31. The header analysis unit includes a MAC header check circuit, an LLC header check circuit, a SNAP header check circuit, an IP header check circuit, and a reception status check circuit.

In FIG. 3, the packet transferred from the communication control unit 61 to the memory 33 receives the information of the packet head position and the latch timing (a) from the control circuit 32, and the packet header and the reception status (b) are FIF
It is stored in the memory 342 under the control of the DMA control circuit 34313 via O34312. IP over FD
The packet structure in the case of DI is shown in FIG. In FIG. 5, data as a packet header to be transferred / stored is a MAC (Media Access Control) header, an LLC (Link Layer Control) header, a SNAP header, an IP header and status information. The start position of the packet is taught from the control circuit 32 by the signal (a). On the other hand, the transferred data is stored in the judgment register 343150 and sequentially checks the following items.

The following is, for example, when routing is performed using an IP address (hereinafter referred to as IP routing)
The processing of the header analysis unit in FIG.

(1) MAC header check The MAC header is added by each router and DA (Dest
ination Address) and SA (Source address)
Indicates the physical address of the communication port of the router. The FC field of the MAC header is added with frame identification information indicating a plurality of frame types. Examples of frame types include LLC frame, MAC frame, SM
There are T frames and the like. MAC header check circuit 34
3151 sees the FC field, LLC frame, M
Identify AC frames, SMT frames, etc. I
The frame to be P-routed is an LLC frame.

Also, the MAC header check circuit 3431
51 checks the DA field to see if the DA is its own address. The frame to be IP-routed is for itself. If the DA is its own address, the result is output so that it is routed. If it is not the own address, DA
Is a multicast or not. If the DA indicates multicast, it is determined whether or not it matches the multicast address of its own device. It has multiple multicast addresses and uses it for associative memory CAM
It is stored in advance in 344. DA and CAM received
It can be determined by comparing with the contents of 44. If the DA is not a multicast, or if it does not match the multicast address of its own device, the result that routing is not performed is output.

(2) LLC Header Check The LLC header check circuit 343152 determines that the DSAP,
Looking at the SSAP and CTL fields, IP
Make sure you are pointing to the protocol. When the LLC header part has a specific bit pattern, it can indicate that the protocol is an IP protocol. Therefore, it is checked whether the LLC header part matches the specific bit pattern and the result is output.

(3) SNAP Header Check The SNAP header check circuit 343153 checks the PID field to confirm that it is instructing the IP protocol. Also, looking at the TYPE field, the protocol of the data following the SNAP header identifies either IP / ARP / other, and outputs the result.

(4) IP Header Check The IP header check circuit 343154 has the V area (versio
n of IP) to see if it is a supported IP version. Also, HL (IP headerlength)
Check that the IP header length is appropriate. Also, the destination IP address (DA), which is a logical address, is extracted. If it is not the IP version or if it is not an appropriate IP header length, that is output, and if it is the IP version and an appropriate IP header length, the destination IP address (DA) is output.

(5) Reception status check The reception status check circuit 343155 confirms the normality of the received frame by looking at the status. If it is a normal IP header, the TO required for the routing table search
Information such as S (Type of Service) and DA (destination IP address) is extracted.

The results of the above (1) to (5) are stored in the register 3
It stores in 43156. The result is concatenated with the tail of the data to be stored in the previous head position, and
The information necessary for the subsequent routing and the result of the header analysis will be stored inside.

As described above, since the routing assist circuit 343 completes the pre-routing steps such as frame identification and correct / wrong determination, the processing load of the μP 341 can be reduced and the routing processing can be speeded up. μP341
Looks at the header analysis result stored in the memory 342,
If the frame should be IP routed, μP34
1 performs an IP routing process.

FIG. 13 shows another configuration example of the header analysis section. With reference to FIG. 13, another configuration example of the block that analyzes the header of the frame sent from the communication control unit at the time of reception will be described.

In FIG. 13, the received frame data is simultaneously input to the comparator and the switch, for example, in units of 32 bits according to the width of the data bus. In the comparator, since successive comparison is performed every time data is input (for example, in this example, comparison is performed every 32 bits), the counter at the comparison position is counted by the control signal input at the same time as the data. The comparison position counter is
Information on what bit of data is input from the start position of the header is held. The data selector switches based on the information, and the MAC header, LLC header, SNAP header,
The specific data to be compared among the specific bit patterns such as the IP header is sent to the comparator. For example, in the first comparison, FC header of the MAC header shown in FIG. 5 and the top 3 bytes of DA are compared with a total of 4 bytes (32 bits), and in the second comparison, the remaining 3 bytes of DA and the beginning of SA are compared. The position of 1 byte is compared, the position of the next 4 bytes of SA is compared in the third comparison, and the position of the remaining 1 byte of SA and the DSAP 1 byte of the LLC header are compared with the received data in the fourth comparison. Each is compared with a specific bit pattern. Instead of accumulating the input data and comparing the MAC header to the IP header at once, the comparison is performed little by little from the beginning position as described above. The comparator compares the input received data with the data to be compared, and outputs a match / mismatch as a comparison result to the switch, the result register and the sequencer. As a result, the switch is controlled to be turned on when it is necessary to continue inputting data, and is turned off when it is not necessary to input more data. If you still need to enter data, for example,
If the data input so far is the MAC header and LLC header, and the SNAP header and IP header are the next and the comparison data match, the input frame may be an IP frame for which routing processing should be performed. Therefore, it is necessary to continue the header analysis. Further, when it is not necessary to input more data, for example, when the received frame is an invalid frame and it is meaningless to continue the header analysis, or when it is a valid frame, the routing process is performed during the analysis. If it is determined that the frame is not necessary, or if the received frame is an IP frame and the entire header portion has been input, it is determined that there is no need to input at the mismatching stage. By the operation of this switch, only a necessary portion of the entire frame can be captured and an unnecessary portion can be ignored. If there is a delay between the comparison of data with the comparator and the control of the switch,
In FIG. 13, it is advisable to insert a delay circuit having a delay time commensurate with the delay in front of the switch to adjust the timing. Once the data passed through the switch is stored in the FIFO, the sequencer circuit activates the DMA controller 34313 to transfer the data stored in the FIFO to the memory 34.
DMA transfer to 2. At this time, the result register 34315
The result of the header analysis stored in 6 is also transferred to the memory 342. The timing of writing to the memory 342 is instructed by the sequencer circuit. After that, the processor performs necessary processing such as routing processing by looking at the analysis result and the header stored in the memory 342.

As described above, by configuring the header analysis unit of the routing assist circuit 343 with hardware, it is possible to analyze the frame at a higher speed.
In addition, the routing assist circuit 343 performs one of the previous routing processes such as frame identification and correct / wrong judgment.
Since the filtering by the header analysis is completed, the processing load of the μP 341 can be reduced.

The routing process in the μP341 is as follows.
This is performed by referring to the routing table of the memory 342 registered in advance. In the present embodiment, the routing table is referred to by the hash method. FIG. 6 shows a logical configuration of a routing table (hereinafter referred to as a hash management table) based on the hash method. By using a predetermined hash function, I
Project 24 bits of the network address of the P address into an 8-bit hash value. The hash management table uses the hash value as a pointer to register the routing information at the corresponding position. When the hash values are the same, they are further linked by a pointer. In FIG. 6, the data for route registration has a list structure in which entries (registrations) are made in the order of occurrence. In FIG.
∧ indicates the end of the list, and ● indicates a pointer. The registered routing information data is data as shown in FIG. 7. The hash circuit 34317 calculates a hash value when accessing the memory having the configuration of the hash management table as shown in FIG. The hash circuit 34317 accesses the hash management table, and searches / registers by tracing the list from here. The μP 341 can obtain a hash value at high speed by giving a key to the hash circuit 34317.
In this case, the key is the destination IP address, TOS, or the like. As shown in FIG. 7, the data structure of the routing table dedicated to IP relay includes a network address indicating the destination network, a subnet mask indicating the subnet information of the destination network, and a next hop address (the IP address of the next router required for routing). ), The interface number (routing processor number and port number of the routing processor) used to send to the next hop, and a pointer to the next entry to create the list structure. μP341 is the memory 3
The destination IP address in the frame header is read from 42. Destination IP address hash generation circuit 3431
7, the hash value is obtained, and the hash management table shown in FIG. 6 is accessed by this value to search for the desired entry. The next-hop IP address and interface number are obtained by accessing the above-mentioned relay-only routing table.

Further, by replacing the hash generation circuit 34317 with a circuit for obtaining the desired entry by performing the above hash generation and list search by hardware,
Allows routing table lookups to be handled by hardware. FIG. 11 shows a block diagram of the hash circuit in this case, and FIG. 12 shows a processing flow of hardware search.

In FIG. 12, the hash circuit has a destination I
The P address is set as a table search key in the table search key setting register (step 121). The hash value calculation circuit obtains the hash value and obtains the entry number of the hash management table (step 122). The pointer calculation circuit of the head table calculates the pointer (address) of the corresponding entry from the entry number (step 123). The memory 342 using the calculated pointer
To obtain a pointer to the routing information (step 124). In parallel with the above processing, the address calculation circuit for the "pointer to the next entry" calculates the "pointer to the next entry" indicating the head of the next entry in the table from the pointer of the routing information (step 125). The network address of the first entry of the routing information is read (step 126). It is compared whether the read network address and the table search key match (step 127). If they match, the routing information is read to obtain the next hop IP address and interface number. If they do not match, the memory is accessed by the "pointer to the next entry" obtained by the address calculation circuit of the "pointer to the next entry", and the pointer to the next routing information is obtained (step 128). The process is transferred to 125. As a result, the μP 341 only starts the search, the load is further reduced, and the routing process can be further speeded up.

The μP 341 is the routing assist unit 3
4 stores the header analysis / routing result, the next hop address, and the interface number in the dual port memory 34316, and notifies the μP 31 of them. μP3
1 transfers the packet already stored in the memory 33 to the routing processor corresponding to the destination interface based on this result.

Next, from the assist circuit 343 to the μP31
The routing information is accumulated in the dual port memory 34316 when the header analysis information is transferred to the μP31.
Reads the routing information by accessing the dual port memory 34316. At that time, in the dual port memory 34316, the routing information is stored as a routing table in a cache configuration. The configuration and operation of the routing table cache will be described with reference to FIG. Note that FIG. 10 shows an example of a cache configured by using the direct map method. The configuration of the routing table accumulated in the dual port memory 34316 is the tag unit 34321.
And an entry section 34320.

In FIG. 10, if the received packet is an IP packet when the packet is received and the header analysis is completed, the result register 343156 stores the destination IP address, information necessary for routing, and the like. However, the routing assist circuit 343, here, the μP341
Is not notified that a header determination result has been output. First, of the information stored in the result register 343156,
The key (IP address, TOS, etc.) necessary for the routing table search is taken out, and the tag unit 34321 is accessed using a plurality of bits of the key. The pointer of the entry at this time is i. The hit determination is performed by determining whether the output of the tag and the remaining bits of the key not used for tag access match. When the hit determination is completed, the routing assist circuit 343 notifies the μP 341 of the determination result. The hit indicates that the routing information for the destination IP address is already stored in the entry i of the routing table cache, and the miss hit indicates that the information is not yet entered. When a packet for the destination IP address is received for the first time, there is nothing registered in the cache, so there is always a miss-hit. When the hit determination is completed, the routing assist circuit 343 notifies the μP 341 of the determination result. If there was a mishit, μP3
41 obtains a result (routing information) by the procedure for searching the above-mentioned routing table based on the above-mentioned key, and thereafter stores the routing information and the sequence number in the corresponding entry i of the entry part 34320 of the dual port memory 34316a. At the same time as storing the information, the portion of the key not used for tag access is registered in the tag portion 34321, and the μP 31 is notified that the data is ready for the entry i. Accordingly, the μP 31 determines that the entry i
The routing information of is retrieved and processed. μP31
Does not purge (release) the entry i even if the processing is completed. Next, consider a case where a packet to be subjected to the same routing process as the packet just processed is received. This may occur when the packet destination devices and TOS are the same. In this case, since it was registered in the cache when the processing was performed before, a hit occurs if the hit determination is performed after the reception and the header processing. When the hit determination is completed, the routing assist circuit 343 notifies the μP 341 of the determination result. If there was a hit, μP34
1 indicates that the reusable information such as the routing information among the information stored in the hit entry i is left as it is and only a part of the non-reusable information such as the sequence number is updated. Notify that the data is ready. Thus, each entry of the routing table cache is composed of a plurality of fields, and each field can be individually rewritten. In accordance with this, the μP 31 takes out the routing information of the entry i and performs a process. By configuring the cache memory using the key for routing in this way, when the routing information up to the destination IP address of the received packet is already registered in the cache memory and can be reused, the routing table Since the search for can be omitted, the speed can be increased.

Although the routing table cache has a direct map system here, an n-way associative system and a full associative system can be used to construct a routing table cache having a higher hit rate. In this case, the cache entry update method is LRU (Least Recently Use).
d) Method is suitable.

Next, in the configuration shown in FIG. 1 or 2, a state of performing packet transfer between the routing processors via the router bus 1 will be described below. FIG. 9 shows a packet format when a packet is transferred from the routing processor to the destination routing processor.

As shown in FIG. 9, the μP 31 transfers a packet with a transfer length, a destination interface number (a routing processor number and a port number of the routing processor), a source interface number, a communication protocol, a media type, and a next hop ID (communication). Protocol is TCP /
If it is IP, a transfer header consisting of IP address) is added to the received data and transferred to the destination routing processor via the router bus 1. For example, from the received routing processor 3 (a) to the routing processor 3 (a)
Transfer to (c). The destination interface number, communication protocol, media type, and next hop ID in the transfer header are information obtained from the routing associator 34.

First, the routing processor on the side of transmitting a packet to the router bus 1 adds the transfer header shown in FIG. 9 to the packet received from the network (port). A packet added with a transfer header is called a data block here. To simplify the process,
The data block and transfer header are preferably fixed length. For example, the data block length is fixed at 1024 bytes,
The transfer header is fixed at 48 bytes. Therefore, the number of bytes of the packet to be transferred is the maximum length of data that can be stored in the data block (976 bytes in the above example).
Longer, the packet is divided into multiple data blocks and transferred. Also in this case, the transfer header is added to all the data blocks. For example, F that is 2500 bytes including the protocol header part and the data part together
When transferring a DDI packet, the packet is divided into three data blocks. Since the transfer header includes the transfer length (effective data length) information, anything may be included in the portion of the third data block that does not include the data.

Next, a procedure for dividing a packet into data blocks and a procedure for integrating the data blocks after transfer and returning them to packets will be described. FIG. 15 shows the correspondence between packets and data blocks in this case. When a packet is divided into blocks, each routing processor (relay processing unit) divides the packet information from the network into blocks of fixed length, and based on the destinations in each block divided by the dividing unit. Means for adding the identification information of the corresponding routing processor, a sending means for sending the block to which the identification information is added by the adding means to the bus, and a block to which the identification information of the own device is added from the bus. Receiving means for receiving,
When the block received by the receiving means is divided information, the integrating means integrates the divided blocks. Each of these means can be processed by the control circuit. Alternatively, when the routing assist unit is provided, the destination information may be analyzed in the routing assist unit. As for the information, the capacity of the information is added in advance, and the integrating means refers to the capacity added in advance to the information and integrates the divided blocks. The routing processor, when receiving information from the other routing processor, performs exclusive control to exclude the reception of the other information, and when transmitting to the other routing processor, the other of the receiving side. And a transfer control unit for confirming whether or not the information is received to the exclusive control means of the routing processor, and notifying that the information is transmitted when the information is not received. Upon receiving the notification from the transfer control unit of the other routing processor on the transmission side, the means can receive only the information from the routing processor. Exclusive control will be described later.

First, before writing the packet received from the network (port) to the buffer memory 33, the inside of the buffer memory 33 is divided into areas for each data block length in advance. Here, this divided area is called a block. An area equal to the transfer header length is secured at the beginning of each block, and control is performed so that no received packet is written in that area. When the packet received from the port is transferred to the block in the buffer memory 33, the received packet length is longer than (block length-transfer header length) × n (n is a natural number), and the packet needs to be divided into n + 1 blocks. If there is, the control circuit 32 divides the packet and stores it in an area other than the area in which the transfer header is written in the block. After that, the μP 31 adds a transfer header to the beginning of each block and the division is completed. After transferring the divided packets in the data block between the routing processors,
Contrary to the above processing, the control circuit 32 skips the transfer header portion in the block and sends the packet to the port while the packet is divided into blocks.

As described above, the packet division / integration processing is performed by each means of the control circuit 32 when the packet is transferred between the port and the buffer memory.

The destination interface number included in the transfer header is not a physical address or slot number indicating the routing processor on the packet receiving side, but a logical number indicating the routing processor on the packet receiving side. And a logical number combination indicating the port that actually sends the packet to the network. The logical number indicating a port is included in order to uniquely transfer data to a destination port even when a plurality of ports are connected to one routing processor. As described above, in the present embodiment, the logical address of the destination module is embedded in the transfer header to send the logical address using the data bus. In a real router bus, for example,
An address bus may be provided for sending control data.
The routing processor on the side transmitting the packet first declares in advance that the data block is transmitted to the routing processor on the receiving side by using the address bus and the data bus for control, and then Then, the data block is sent using only the data bus. After that, the routing processor on the receiving side checks the transfer header of the received data block to confirm that it is transferred to the correct destination. The data bus for sending control data and the data bus for sending data blocks may be separate.

In order to realize such transfer, for example, the following configuration can be adopted. That is,
A dual port D-RAM is used as the memory 33 to separate a control path and a packet transfer path between the routing processors to specialize a packet transfer bus.
As a result, the packet transfer between the routing processors can be speeded up, and the performance of the entire router device can be improved.
FIG. 16 shows a hardware configuration example in the case where the control path and the packet transfer path are separated, and the dual port D-RAM is used as the memory 33 to speed up the packet transfer. In the routing processor shown in FIG. 16, the serial access port (SAM port) of the dual port D-RAM is used exclusively for the purpose of packet transfer, and the random access port (RAM port) is used for other purposes.

In FIG. 16, at the time of transfer, the μP31 of the transmission side routing processor adds a transfer header to the packet and forms it into a data block. At this time, if the packet length is longer than the maximum length of the data block, the packet is divided into a plurality of data blocks. After that, μP
31 is a control circuit 32 of the transmission side routing processor
To the memory 33 of the sender routing processor
Notify that the data block to be transferred is ready. In response to this, the control circuit 32 of the routing processor on the transmitting side notifies the control circuit 32 of the routing processor on the receiving side of the packet transfer, and then transfers the data block by DMA.

The transfer is performed by directly connecting the SAM ports of the dual port D-RAMs of the sending side routing processor and the receiving side routing processor with a router bus, reading from the SAM port of the sending side routing processor, and receiving side routing. This can be realized by writing data to the SAM port of the processor in synchronization with each other. The control circuit 32 of each routing processor controls the DMA transfer and the SAM port. Once initialized, the SAM port can operate independently of the RAM port until all data is output, so packet transfer between routing processors and other processing that uses the memory 33 are processed in parallel. It becomes possible to speed up the whole process. The SAM port is controlled by RAM
Although it is more complicated than the control of the port, if the number of bytes of the SAM port is set as the length of the data block which is the unit of packet transfer, the control of the dual port D-RAM can be relatively easy.

When all the data blocks have been transferred,
The control circuit 32 of the receiving side routing processor notifies the μP 31 of the receiving side routing processor to that effect. In response to this, the μP 31 deletes the transfer header from the data block stored in the memory 33, and if one packet is divided into a plurality of data blocks, returns it to one packet again. Whether or not the data block is divided into a plurality of data blocks is determined by referring to the transfer length information included in the transfer header. Alternatively, in the routing processor on the sending side, when dividing the transfer data, a serial number is added to each data block and an end mark is added to the last block, and the routing processor on the receiving side stores the added information. The divided blocks may be integrated with reference to each other. After that, after performing protocol processing such as correctly rewriting the physical address of the next hop device, the packet is sent to the network.

Next, the arbitration protocol for DMA transfer in the hardware configuration shown in FIG. 16 in which the control path and the packet transfer path are separated will be described with reference to FIG.

The control circuit 32 controls the data transfer D
It has an MA transfer control unit 321 and an exclusive control register 322 for performing exclusive control of DMA transfer destined for another module having the control circuit 32. First, the DMA control unit 321 of the sending side module 3a uses the router bus 1
The exclusive control register 322 of the receiving side module 3b is read using the control bus of
Make sure that no module is transferring. After that, the DMA control unit 321 of the sending side module 3a
A flag that the module 3a is performing the DMA transfer is written in the exclusive control register 322 for the module 3b. The DMA control unit 3 of the sending side module 3a
21 to the exclusive control register 32 of the receiving side module 3b
A series of accesses from 2 to write to 2 must not be divided by accesses from other modules. This is to prevent the same receiver module from simultaneously permitting DMA transfer from a plurality of sender modules. By setting the hardware structure of the exclusive control register 322 so that the flags are written at the same time by performing reading,
Reading and writing can also be performed simultaneously.
If another module is in the process of performing a DMA transfer to the receiving side module 3b, the DM
The sending module 3a waits until the A transfer is completed. After declaring the execution of the DMA transfer to the receiving side module 3b, the sending side module 3a performs the DMA transfer using the data transfer dedicated bus of the router bus 1. The bus right arbitration is performed in the same manner as the bus arbitration procedure normally used. It is more efficient if the control bus and the data transfer bus can operate independently,
Since the control becomes complicated, it is not necessary to operate independently.
After all data transfer is completed, the sending module 3a
D in the exclusive control register 322 of the receiving module 3b
The flag indicating that the MA transfer is being performed is cleared, and the end of the DMA transfer is declared. By adopting such a procedure, it is possible to limit the number of sending side modules that perform the DMA transfer to the receiving side module. Therefore, even when one packet is divided into a plurality of data blocks and transferred, the receiving side module The data blocks transferred from a plurality of sending side modules are not mixed in the buffer memory of the above. This can simplify and speed up the process.

Next, the processing operation of the routing processor when a packet is received via the router bus 1 will be described by taking the receiving side routing processor 3 (c) as an example.

Receiving side routing processor 3 (c)
Receives the transfer header and the packet in the memory 33. Although the configuration of the routing processor 3 (c) on the receiving side is omitted in FIG. 1, it is the same as that of the routing processor 3 (a). The receiving side routing processor 3 (c) converts the packet format according to the sending interface. For example, the FDDI frame has been described above as an example. Here, assuming that the transmission interface is IEEE802.3 (CSMA / CD), it is created in conformity with the frame format of IEEE802.3. For example, an MTU having a frame length of IEEE802.3
When a packet exceeding (Maximum Transfer Unit) is received from another routing processor, it is necessary to fragment the frame. The μP 31 of the receiving-side routing processor 3 (c) performs such frame processing and transfer processing for subsequent transmission. Also, the necessary address information is received by the receiving side routing processor 3
It is obtained from the routing assist unit 34 of (c) as follows.

In the receiving side routing processor 3 (c), the necessary address information is the physical address corresponding to the next hop logical address (eg IP address in case of TCP / IP). The μP 31 transfers the next hop logical address included in the transfer header to the dual port memory 3
It is passed to the μP 341 via 4316. The address resolution table shown in FIG. 8 is constructed in the memory 33 in the list structure as shown in FIG. 6, like the above-mentioned IP relay dedicated routing table. The μP 341 obtains a hash value using the next hop logical address as a key, and obtains an entry obtained by the same algorithm as the above-mentioned search of the IP relay dedicated routing table. The obtained physical address is returned to the μP 31 via the dual port memory 34316.
As in the case of searching the routing table dedicated to IP relay described above, the load on the μP 341 can be reduced by adding a circuit for processing hash generation and list search by hardware.

The μP 31 changes the destination physical address of the packet whose format is converted according to the transmission interface to the physical address obtained from the routing assist unit 34. After that, the frame is transferred to the communication control unit and transmitted.
The packet is relayed as described above.

If the physical address corresponding to the required next hop logical address is not registered in the address resolution table, the routing processor 3
(C) uses ARP (Address Resolution Protocol) to make an inquiry to the network that is going to send the packet, and as a result, obtains the required physical address. In addition, the information obtained as a result of the inquiry is registered in the address resolution table as needed. In this way, the physical address can be obtained.

As described above, the routing assist unit 3
It can be said that 4 is a routing assist means aiming at improving the performance by reducing the processing of the μP 31. Therefore, it is also possible to perform the processing only by the μP31 without providing the assisting means.
Explained in. It is also possible to first realize such a low-cost router and then take the approach of realizing a high-speed router with improved performance by adding assisting means as in the above-described embodiment.

In the above embodiments, the example of IP routing has been described, but it goes without saying that routing of other protocols such as OSI can be similarly realized. It is also possible to realize a multi-protocol by supporting a plurality of protocols at the same time.

Further, by supporting the bridge filtering also by the routing assist unit 34, it is possible to realize a brouter device. That is, the analysis processing unit of the routing assist unit 34 determines whether or not the destination stored in the routing table of the storage unit and the destination of the information from the network match at the time of analyzing the output destination, and they match. If it is, the routing information is output as the analysis result, and if the addresses do not match, it outputs that the destinations do not match, and the transfer processing means outputs the analysis processing means when the destinations do not match. Even in this case, the information from the network is transferred to another routing processor. As a result, even when the destinations do not match, the packet can be transferred to another routing processor without being discarded.

Next, FIG. 14 shows a mounting example of a router.
The router has a base substrate and a plurality of routing processor substrates mounted on the base substrate. The management unit 2 may be provided on the base board or may be mounted. The board of the routing processor is connected via the connector of the router bus 1. Example 1
As shown in, the communication controller may be provided on the board of the routing processor. Further, the routing assist unit 34 can be added to the substrate of the routing processor. Alternatively, as shown in Example 2, the communication control unit and the routing assist unit 34 may be added to the board of the routing processor. In this way, when processing as a medium to low speed router, processing is performed without mounting the routing assist unit 34, and when improving performance as a high speed router, the routing assist unit 34 is added and parallel processing is performed. It can be processed faster.

As described above, according to the present embodiment, since the packet processing for transferring the data of the received packet and the routing processing for the route selection by the header analysis can be performed in parallel / shared processing, a high speed router can be realized. You can Further, since the basic parts of the medium-low speed router and the high-speed router can be shared, the development cost can be reduced. Since a high-speed router can be realized by adding routing assist to the medium-low speed router, the version upgrade is easy.

Further, by providing the routing table cache, the search of the routing table can be omitted if the routing information for the destination for which the routing processing has been performed previously remains, so that the packet can be relayed at high speed.

[0096]

As described above, according to the present invention, it is possible to enable high-speed routing processing in an internetwork device and easily improve performance.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a high-speed router.

FIG. 2 is a configuration diagram showing a configuration of a medium to low speed router.

FIG. 3 is a configuration diagram showing a routing assist circuit.

FIG. 4 is an explanatory diagram showing a flow of relay processing.

FIG. 5 is an IP ove sent from the communication control unit when receiving.
r Explanatory drawing showing the format of an FDDI packet.

FIG. 6 is an explanatory diagram showing a configuration of a routing table.

FIG. 7 is an explanatory diagram showing a data structure of an IP relay dedicated routing table.

FIG. 8 is an explanatory diagram showing a data structure of an address resolution table.

FIG. 9 is an explanatory diagram showing a packet transfer format between routing processors.

FIG. 10 is an explanatory diagram showing a configuration example of a routing table cache.

FIG. 11 is a circuit configuration diagram for searching a routing table.

FIG. 12 is a flowchart for searching a routing table.

FIG. 13 is a configuration diagram of a header analysis unit.

FIG. 14 is an explanatory diagram showing a mounting example of a router.

FIG. 15 is an explanatory diagram when a packet is divided into a plurality of data blocks.

FIG. 16 is a configuration diagram when a dual port D-RAM is used as the memory 33.

FIG. 17 is an explanatory diagram of arbitration of DMA transfer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Router bus, 2 ... Management part, 3 ... Routing processor, 31 ... Microprocessor, 32 ... Control circuit, 3
3 ... memory, 34 ... routing assisting section, 341 ...
Microprocessor, 342 ... Memory, 343 ... Routing assist circuit, 51-53, 61-63 ... Communication control section.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuyoshi Onishi, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Kanagawa Microelectronics Development Laboratory (72) Inventor Hiroshi Sato Imai Shimoizumi, Ebina, Kanagawa 810 Incorporated Hitachi, Ltd. Office Systems Division (72) Inventor Masato Tsukagoshi 1099 Ozenji, Aso-ku, Kawasaki, Kanagawa Hitachi, Ltd. System Development Laboratory (72) Inventor Toshihiko Murakami 1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture Hitachi System Development Laboratory

Claims (14)

[Claims] 1. An internetwork device for connecting a plurality of networks to each other and relaying information from one network to another network, which is provided corresponding to each network, and the information from the network is associated with the information. A relay processing unit that relays the relay route information based on the destination, the relay processing unit refers to the storage unit that stores the relay route information corresponding to the destination, And a transfer processing unit for transferring the information from the network to another corresponding relay processing unit based on the output of the analysis processing unit. Internetwork equipment. 2. The internetwork apparatus according to claim 1, wherein the analysis processing means and the transfer processing means perform parallel processing. 3. The analysis processing means according to claim 2,
An internetwork apparatus, wherein relay path information is output as the analysis result, and the transfer processing means adds the relay path information of the analysis processing means to information from the network and transfers the information. 4. The storage means according to claim 3, further storing identification information regarding a network of an output destination of the relay processing section as the relay route information, and the transfer processing means from another relay processing section. Upon receiving the transferred information, the analysis processing means analyzes the output destination based on the relay route information added to the transferred information and the identification information on the output destination network of the storage means, and the transfer processing is performed. The means outputs the information transferred from the other relay processing section to the output destination network analyzed by the analysis processing means, the internetwork apparatus. 5. The analysis processing means according to claim 1,
When the output destination is analyzed, it is determined whether the destination stored in the storage means and the destination of information from the network match. If they match, the analysis result is output and the transfer is performed. An internetwork device characterized in that the processing means transfers information from the network to another relay processing unit even when the output of the analysis processing means does not match the destination during the transfer processing. 6. The relay processing unit according to claim 2, further comprising a shared storage unit that can be read and written by the analysis processing unit and the transfer processing unit, and the shared storage unit is analyzed by the analysis processing unit. An internetwork device which stores relay route information corresponding to a destination. 7. The determination unit according to claim 6, wherein the relay processing unit determines whether or not the destination stored in the shared storage unit and the destination of the information newly received from the network match. The analysis processing means further performs the analysis processing when the determination means determines that they do not match, and stores the shared storage means when the determination means determines that they match. An internetwork device characterized by performing processing for rewriting only relay route information that cannot be reused for existing relay route information. 8. The transfer processing means according to claim 1,
An internetwork device further having a function of analyzing a destination of information from a network and outputting an analysis result. 9. The relay processing unit according to claim 2, further comprising a storage unit for storing information from the network and a holding unit for holding a destination of the information from the network, wherein the analysis processing unit comprises: An internetwork apparatus, characterized in that the destination held in the holding means is analyzed, and the transfer processing means transfers the information accumulated in the accumulating means. 10. The storage means according to claim 1, wherein a value based on a predetermined hashing function is used as an address based on a numerical value representing a destination, and the analysis processing means, when referring to the storage means, An internetwork device characterized by obtaining and referring to a hashing value based on a numerical value representing a destination. 11. The relay processing unit according to claim 1,
A plurality of ports connected to the network are provided, and the storage unit stores the logical identification number of the relay processing unit corresponding to the destination and the logical identification information of the port of the relay processing unit as relay route information, and the analysis processing unit. Outputs the relay route information as the analysis result, and the transfer processing unit outputs the information transferred from another relay processing unit by adding the relay route information output by the analysis processing unit. An internetwork device which outputs to the preceding network. 12. An internetwork device for connecting a plurality of networks to each other and relaying information from one network to another network, the internetwork device being provided corresponding to each network and receiving the information from the one network as a destination. Has a relay processing unit that relays based on the above, the relay processing unit refers to the storage unit that stores the relay route corresponding to the destination, and analyzes the destination of the information from the network by referring to the storage unit. And a second processor for outputting information from the network to another corresponding relay processing unit based on the analysis result of the first processor. Characterized internetwork device. 13. A relay processing circuit which is mounted on an internetwork device for connecting a plurality of networks to each other and relaying information from one network to another network, the relay processing circuit provided corresponding to each network, The relay processing circuit includes a storage unit that stores a relay route corresponding to a destination, a first processor that refers to the storage unit, analyzes a destination of information from a network, and outputs an analysis result, A relay processing circuit comprising: a second processor that transfers information from the network to another corresponding relay processing unit based on an analysis result of the first processor. 14. A network system comprising a plurality of networks and an internetwork device which connects the networks to each other and relays information from one network to another network, wherein the internetwork device is connected from the network. Has a relay processing unit for relaying the information on the basis of the destination corresponding to each network, the relay processing units are respectively connected by a bus, and the relay processing unit analyzes the destination of the information from the network. And a transfer process for transferring information from the network to another corresponding relay processing unit based on the analysis result of the analysis processing means are distributedly processed. Network system.