JPH06196566A - Intermetal antifuse containing silicified and implanted metal layer - Google Patents

Abstract

PURPOSE: To provide the title anti-fuse in high reliability easy to manufacture. CONSTITUTION: The anti-fuse between metals is manufactured by using a metallic layer 14 silicified to be implanted as an anti-false lower electrode 22. An anti-fuse aperture is formed inside an inter metallic insulator 16 formed on the lower electrode 22. An anti-fuse material 28 is formed inside the anti-fuse aperture, while an upper electrode 30 including the second metallic layer is formed on the anti-fuse material 28. In such a constitution, a nitride layer may be formed on the lower electrode 22 so as to fill the etch-blocking role of the intermetallic insulator 16.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to user programmable antifuse structures. More specifically, the present invention provides an antifuse structure using two metal interconnect layers in an integrated circuit or the like, a bottom electrode including a silicided and implanted metal layer, and a silicided and implanted metal layer. It relates to intermetallic antifuses used to make connections.

[0002]

Antifuse structures are known in the prior art. A typical example of prior art antifuses is US Pat. 4,823,181
And Hamdy et al., US Patent No. 4,899,205. These examples use a multilayer dielectric structure as an antifuse material between two conductive electrodes. One electrode can be a doped activation region within the semiconductor substrate. US Patent N by Gordon et al.
o. 4,914,055 discloses an antifuse structure provided between a metal interconnect layer and an intermediate metal layer.

European patent application No. 9 by Whitten et al.
0309731.9, European Patent Publication No. 0416903A2,
An antifuse structure is disclosed that uses an amorphous silicon antifuse material that can be placed between two electrodes that include a portion of a metal interconnect layer. US Pat. No. 5,070,384 to McCollum et al. Discloses an antifuse having a bottom electrode formed of refractory metal silicide or arsenic doped polysilicon. .

[0004]

One problem in antifuse manufacturing is the flatness of the upper surface of the bottom electrode. This problem is a major problem for antifuses placed in layers provided on the surface of the substrate on which they are formed. The lack of appreciable flatness of the surface causes manufacturing and reliability problems. The flatness of the upper surface of the lower antifuse electrode is
The problem is in metal antifuses arranged between two connection layers in an integrated circuit or interconnect matrix.

Two occurring in intermetallic antifuse technology
One other problem is the electromigration and diffusion of metal ions from the antifuse electrodes into the antifuse material between the antifuse electrodes. These phenomena can cause reliability problems in circuits containing antifuses as described above.

Finally, if the antifuse is used as a connecting element in high performance circuits, the antifuse must exhibit a low resistance after programming. After programming, it is always sought to have antifuses with low resistance values.

It is an object of the present invention to provide an antifuse which is able to address the above mentioned manufacturability and reliability issues.

Another object of the present invention is to provide an intermetallic antifuse that includes a lower electrode having a substantially planar upper surface.

Yet another object of the present invention is to provide an intermetallic antifuse that includes a bottom electrode having a substantially planar upper surface with substantially no metal ion diffusion and electron transfer into the antifuse material. Is.

Yet another object of the present invention is to have a substantially flat upper surface that is substantially free of metal ion diffusion and electron transfer into the antifuse material and exhibits a very low resistance after programming. Providing an intermetallic antifuse that includes a bottom electrode.

These and other objects of the invention will be apparent from the following description, drawings and claims.

[0012]

According to the present invention, a bottom electrode structure for an intermetallic antifuse can include a silicided and implanted metal layer. The metal layer can be formed of a metal that can withstand the silicide temperature, such as Ti, W 2, TiW 2, Mo, Pt, or Cu. The silicide materials are Ti silicide, W silicide,
It can be Mo silicide, and silicides such as Pt silicide. The silicon layer used to form the silicide layer and the silicide metal deposit are metal,
It is exchangeable depending on the solid solubility of silicon and the silicide material. The implant material is arsenic, phosphorus or other impurities that can reduce antifuse resistance.

According to a second aspect of the invention, an intermetallic antifuse includes a bottom electrode formed from an implanted and silicided metal layer that includes a first metal layer. The intermetal insulator is formed on the lower electrode and the antifuse opening is formed therein. An antifuse material is formed within the antifuse opening and a top electrode including a second metal layer is formed over the antifuse material. In a modification of the structure according to the invention, a layer of nitride is formed on the lower electrode and an intermetallic insulator is formed on the layer of nitride. An antifuse opening is then formed in the intermetal insulator, using the nitride as an etch stop. The antifuse opening is etched through the nitride layer to expose the lower electrode silicide layer. An antifuse material is formed in the antifuse opening and a top electrode including a second metal layer is formed over the antifuse material.

The process of forming the antifuse structure of the present invention comprises the steps of forming a lower antifuse electrode including a silicided and implanted metal layer, forming an intermetal insulating layer, and forming an intermetal insulating layer. A step of forming an antifuse opening therein; a step of forming a layer of antifuse material in the antifuse opening; and a step of forming an upper electrode on the layer of antifuse material. One embodiment of the present invention includes the additional step of forming an etch stop layer over the lower antifuse electrode.

[0015]

EXAMPLES It will be appreciated by those skilled in the art that the following description of the invention is illustrative rather than limiting and other embodiments will be readily suggested.

The antifuse structure of the present invention can be manufactured using well known semiconductor and material processing techniques.
In the following description, details of well-known processes used in manufacturing the antifuse structure of the present invention have been omitted to avoid complicating the description. Although each layer is described as having a constant thickness as a guide to those skilled in the art, it is possible to manufacture the antifuse of the present invention with a thickness outside these ranges.

According to a first aspect of the invention, as shown in FIG. 1, the silicided and implanted metal layer can be used as the lower electrode of an intermetallic antifuse. The antifuse including the lower electrode structure of the present invention is a substrate 10
Can be manufactured on. The antifuse can be a semiconductor substrate or other structure containing active circuitry, and can also be an insulating substrate made from a variety of known substrate materials, depending on the end use application.

In the embodiment shown in FIG. 1, the substrate 10
Can be covered with an insulating layer 12 of, for example, silicon dioxide, for the purpose of electrically isolating the antifuse bottom electrode, for promoting the sticking of the bottom electrode, or for both purposes.

Metal layers are formed using conventional semiconductor processing techniques.
14 is formed on the insulating layer 12. Preferably, the metal layer 14
Includes a portion of an existing metal connection layer in an existing integrated circuit manufacturing process. However, it will be readily appreciated by those skilled in the art that in principle the invention does not require the metal layer 14 to be combined with a metal connection layer.

Preferably, the metal layer 14 is typically
Formed to 5,000 to 10,000 angstroms from a metal that can withstand the silicidation process at temperatures in the range of ~ 1,000 ° C. Typical metals suitable for use as the metal layer 14 in the antifuse structure of the present invention are Ti, W 2, TiW 2, Mo, Pt, or Cu. Preferably, metal layer 14 is a Ti or TiW layer having a thickness of 5,000 to 10,000 Angstroms.

Next, a silicide layer 16 is formed on the surface of the metal layer 14. Those skilled in the art will appreciate that the silicide layer 16
Puts known techniques into conditions such as forming a first layer of material to be silicided, forming a layer of silicon on the first layer and forming these layers as a silicide layer. It can be formed by using the known technique.

Typical silicide materials suitable for the present invention are:
Examples include Ti silicide, W silicide, Mo silicide, and Pt silicide. Preferably Ti silicide or TiW silicide is used.

Those skilled in the art will appreciate that as a material for making a silicide layer, the temperature at which the silicidation process is performed is such that the metal layer 14 and other structures on the substrate (ie, the implant / diffuse active transistor regions) can withstand. It will be appreciated that there needs to be something like this. . One of ordinary skill in the art could readily select a suitable metal for layer 14. For example, tungsten silicide has a temperature of 550 to 800 ° C.
Can be formed in the temperature range of. The metal layer 14 should be formed of a material that can withstand temperatures in this range, for example TiW or Cu.

According to a preferred embodiment of the present invention, 300-
Silicon layer 18 with a thickness of 1,000 Å
Are formed on the surface of the metal layer 14.

Next, a Ti layer 20 having a thickness of 300 to 1,000 angstroms is formed on the surface of the silicon layer 18. The structure is converted to Ti silicide by a rapid thermal anneal, as is well known in the art.

Those skilled in the art will appreciate that the above example is merely exemplary and that the order of forming the silicon layer and the material to be silicided can be interchanged depending on the degree of melting of the metal layer 14, silicon and the silicide material. It will be clear. For example,
When forming titanium silicide on the tungsten metal layer 14, silicon can be formed either before or after titanium. When forming tungsten silicide on titanium, a metal layer is formed so that silicon reacts with tungsten to form tungsten silicide.
14 is formed on the upper surface of the tungsten. It is also possible to form a silicide forming barrier layer, for example TiW 3 nitride on titanium. Once the barrier layer is formed,
The order of silicon and tungsten formation is not critical, as silicon does not form silicide with TiW nitride. The metal layer 14 and the silicide layer 16 form the lower antifuse electrode 22.

In accordance with the present invention, the silicided metal antifuse bottom electrode 22 is implanted with a dopant. The dopant may be of a type that reduces the resistance of the programmed antifuse. For example, it may be arsenic, phosphorus or other impurities known to reduce antifuse resistance. In this embodiment, arsenic is used as the dopant. The implant may be performed immediately after the formation of the silicide layer, or it may be performed at a later point in the process following the formation of the bottom electrode 22.

Intermetallic dielectric layer comprising a layer of oxidized PECVD, preferably having a thickness of 5,000 to 13,000 angstroms
24 is formed on the lower electrode 22. An antifuse opening 26 is formed through the intermetal dielectric layer 24 in the area where the antifuse needs to be located. Preferably, the silicide layer is doped through the antifuse opening 26 while using the aperture mask as an implant mask. Preferably, arsenic is implanted through the antifuse opening 26 at a dose in the range of 5 × 10 ¹⁴ to ² × 10 ¹⁶ atoms / cm ² with an energy of about 20 KeV.

A layer of antifuse material 28 is placed in the antifuse opening 26. In an embodiment of the invention,
The antifuse material layer comprises an amorphous silicon layer having a thickness in the range of approximately 1,000 to 3,000 angstroms. The antifuse material layer 28 may include a silicon nitride layer above or below the amorphous silicon layer, or may include a silicon nitride layer both above and below the amorphous silicon layer. One of ordinary skill in the art will appreciate that the thickness and composition of antifuse material layer 28 determines the voltage at which the antifuse of the present invention is programmed.

A top electrode 30 is disposed on the antifuse material layer 28. Preferably, the antifuse upper electrode
30 includes a layer of TiW having a thickness in the range of 1,000 to 3,000 Angstroms.

2a-2c show the metal silicide bottom electrode 22 described above.
FIG. 6 is a cross-sectional view of an antifuse structure including various aspects of the antifuse structure including various points in the manufacturing process according to the first process of the present invention. First, referring to FIG. 2a, antifuse electrode 22 is made by forming metal layer 14 and silicide layer 16 using conventional semiconductor processing techniques. Conventional photolithography and etching steps can be used to define the antifuse bottom electrode 22. Figure
1 indicates a structure obtained by using the photomask 32 as a corrosion mask for defining the lower electrode 22.

In FIG. 2b, an intermetal dielectric layer 24 is formed on the surface of the silicide layer. In the present embodiment, the intermetal dielectric layer 24 is formed by PECVD using silane reductio.
n) or TEOS and may be planarized using conventional techniques. Using photomask 34, antifuse opening 26 is etched into intermetal dielectric layer 24 to expose the upper surface of silicide layer 16 of bottom electrode 22 using conventional photolithography and etching techniques. It

Antifuse openings 26 in the intermetal dielectric layer 24.
After etching, while the photomask 34 is still in place, a dopant such as arsenic is implanted in the silicide layer 16 as described above. Figure 2b shows the structure after these steps have been performed and before removing the photomask 34.

Those skilled in the art will recognize that great care must be taken when performing the etching process to minimize damage to the bottom of the silicide layer 16. It will also be appreciated by those skilled in the art that, because the silicide layer 16 withstands high temperatures, an annealing process may be performed to repair the silicide layer damage caused by the etching and implanting steps. Further, using a combination of a silicide material and metal for the bottom electrode 22, a reflow process can be performed if it is desired to planarize the intermetal dielectric layer.

In FIG. 2 c, a layer of antifuse material 28 in antifuse opening 26 is formed on intermetal dielectric layer 24. The antifuse material layer 28 is on top of that layer,
Alternatively, it may include an amorphous silicon layer having a layer of silicon nitride of about 100 angstroms or less formed by PECVD method below or both. Standard photolithography and etching steps can be performed to define a layer 28 of antifuse material within antifuse opening 26.

Finally, the upper electrode 30 is formed on the antifuse material 28. The top electrode 30 may be part of the second metal connection layer used in the integrated device containing the antifuse. The layer may include a conductive material such as TiW. Conventional photolithography and etching processes can then be used to define the upper electrode 30 and the remainder of the metal connection layer that may form part of the electrode. 2c shows the upper electrode 30
Shows the photomask 36 used to define

As shown in FIG. 2c, the metal connection layer may include a sandwich structure including an antifuse top electrode 30 covered with a metal layer 38 such as aluminum. Those skilled in the art will appreciate that the definition of antifuse material layer 28 and top electrode 30 is preferably antifuse material layer 28.
It will be appreciated that they are performed simultaneously to minimize the process and eliminate photolithographic sequences. FIG. 2c shows top electrode 30 and antifuse material layer 28 after being simultaneously defined using a single masking layer.

The antifuse structure of the present invention solves some prior art antifuse problems. First, the silicided and implanted metal layer that functions as the antifuse bottom electrode is substantially planar, contributing to an antifuse structure that is easy and reliable to manufacture. In addition, the antifuse structure of the present invention is substantially free of metal ion diffusion into the antifuse layer 24, and metal ion migration of the antifuse electrode material, and exhibits a very low resistance after programming as shown in FIG. FIG. 6 shows a cross-sectional view of an antifuse structure according to a modified embodiment of the present invention. As in the embodiment described with reference to FIGS. 1 and 2a-2c, the antifuse of this embodiment is provided on the substrate 10, optionally on the insulating layer 12.

The lower electrode 22 includes the metal layer 14 covered with the silicide layer 16. However, unlike the first embodiment of the present invention, an etch stop layer 40, preferably comprising a layer of PECVD silicon nitride having a thickness of about 500 to 1,500 Angstroms, is provided over the antifuse bottom electrode 22. To be

An intermetal dielectric layer 24 is provided on the bottom electrode 22 and includes an antifuse opening 26 etched in the layer. The etch stop layer 40 provides an etch stop for the etching process used to form the antifuse opening 26 in the metal dielectric layer 24 due to the selectivity between the metal dielectric layer 26 and the etch stop layer 40. Allows more process control. An additional etching step is used to extend the antifuse opening 26 through the etch stop layer 40. An antifuse material layer 28 is provided in the antifuse opening 26,
A top electrode 30 is provided on the antifuse material layer 28.

FIGS. 4a-4c are cross-sectional views of the manufacturing process for the antifuse structure of FIG. 3 at various points in time, illustrating how a second antifuse structure of the present invention is formed. .

In FIG. 4 a, an antifuse bottom electrode 22 including a metal layer 14 and a silicide layer 16 are formed on the insulating layer 12 on the substrate 10. Conventional photolithography and etching steps can be used to define the bottom electrode. Etching stop layer 40
Is preferably a layer of PECVD nitrogen compound having a thickness of 500 to 1,500 angstroms and is deposited over antifuse bottom electrode 22. An intermetal dielectric layer 18 is formed on the surface of the etch stop layer 40. As in the embodiment shown in FIGS. 1 and 2a-2c, the intermetal dielectric layer 18 can be formed from PECVD silane removal or TEOS.

In FIG. 4b, next the antifuse opening
26 shows a metal dielectric layer by using a two-step etching method using a photomask 34 as an etching mask.
Formed in 18. In the first etching step,
An antifuse opening 26 is formed through the intermetal dielectric layer 18. The etch stop layer 40 provides an end point for the first etch step if an etchant with selectivity between the material including the intermetal dielectric layer 24 and the nitride is used. Those skilled in the art will appreciate that the use of the etch stop layer 40 protects the upper surface of the silicide layer 16 from damage during the etching step.

In the second etching step, a part of the etching stopper layer 40 exposed in the antifuse opening 24 is removed to expose the upper surface of the silicide layer 16 of the lower electrode 22.

At this point in the process, the dopant material is preferably implanted into the silicide layer 16 through the antifuse opening 26 using the photomask 34 as an implantation mask. As in the first embodiment of the present invention, by using the combination of the silicide material for the lower electrode and the metal, it is possible to planarize the intermetal insulator and repair the implantation damage of the silicide layer 16. If necessary, the reflow step can be performed at this point in the process.

In FIG. 4c, the photomask 34 is removed and an antifuse material layer 28 is formed on the intermetal dielectric layer 24. Preferably, antifuse material layer 28
Can include a layer of amorphous silicon formed by a PECVD method. Standard photolithography and etching steps can be performed to define antifuse layer 28.

Finally, the upper electrode 30 is formed on the antifuse material layer 28. As in the first embodiment disclosed herein, the top electrode 30 may be part of the second metal connection layer used in the integrated device containing the antifuse. The layer may include a conductive material 38, for example TiW. An etching step using conventional photolithography and photomask 36 may be performed to define the top electrode 30 and also the rest of the metal layer containing the electrode.

While embodiments and applications of the present invention have been described and illustrated, it will be apparent to those skilled in the art that many variations can be made without departing from the concept of the invention. Therefore, the present invention should not be limited except as set forth in the following claims.

[Brief description of drawings]

1 is a cross-sectional view of a portion of a semiconductor substrate including a silicided and implanted metal layer suitable for an antifuse bottom electrode according to a first embodiment of the present invention.

2 is a cross-sectional view of the antifuse of FIG. 1 after completing selected processing steps, illustrating a first process of the present invention.

FIG. 3 is a cross-sectional view of a portion of a semiconductor substrate having an antifuse structure including a lower antifuse electrode made of silicided and implanted metal according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of the antifuse of FIG. 2 after completing selected processing steps, showing a second process of the present invention.

[Explanation of symbols]

 10 substrate 12 insulating layer 14 metal layer 16 silicide layer 22 lower electrode 24 intermetal dielectric layer 28 antifuse material 30 upper electrode

Claims (13)

[Claims] 1. A first layer made of a material selected from a group containing Ti, W, TiW, Mo, Pt, and Cu, and a group containing a silicide of Ti silicide, W silicide, Mo silicide, or Pt silicide. A second layer made of a material selected from the group consisting of: and a dopant selected from the group including arsenic and phosphorus. 2. The antifuse bottom electrode of claim 1, wherein the first layer comprises a layer of TiW, the second layer comprises a layer of Ti silicide and the dopant is arsenic. 3. The first layer has a thickness of 500 to 1,500 angstroms, and the second layer has a thickness of 300 to 1,
The antifuse bottom electrode according to claim 1, having a thickness of 000 angstroms. 4. The arsenic is 5 × 10 ¹⁴ to 2 × 10 ^l6 atoms /
The antifuse lower electrode according to claim 2, which has a concentration of CM ² . 5. A portion of the first metal contact layer made of a material selected from the group including Ti, W 3, TiW 3, Mo, Pt, and Cu, and Ti silicide, W silicide, Mo.
A lower electrode including a silicide and a second layer selected from a group including a silicide of Pt silicide, and a dopant selected from a group including arsenic and phosphorus, and a lower electrode formed on the lower electrode. An intermetal dielectric layer having an antifuse opening formed therein, an antifuse material layer provided in the antifuse opening, and an upper electrode formed of a part of the second connection layer. Characteristic intermetallic antifuse. 6. The intermetallic antifuse of claim 5 including an etch stop layer between the metal dielectric layer and the bottom electrode, the antifuse opening extending through the layer. 7. The dopant is 5X10 ¹⁴ to 2xl0 ^l6
The intermetallic antifuse according to claim 5, which is arsenic at a concentration of atoms / CM ² . 8. A step of forming a first layer of a material selected from the group including Ti, W 3, TiW 3, Mo, Pt, and Cu, and Ti silicide, W silicide, Mo silicide, and Pt.
Forming a second layer of a material selected from the group including silicide silicide, and doping the lower electrode with a dopant selected from the group including arsenic and phosphorus. And a method for forming a lower electrode for an antifuse element. 9. The step of forming the first layer is TiW.
Forming a second layer, the step of forming the second layer includes the step of forming a layer of Ti silicide, and the step of doping the bottom electrode is selected from the group including arsenic and phosphorus. 9. The method of claim 8 including the step of implanting a dopant. 10. The method of claim 9, wherein the step of doping the bottom electrode comprises doping the bottom electrode with arsenic at a concentration of 5xl0 ¹⁴ to 2xl0 ¹⁶ atoms / CM ² . 11. A first metal interconnect layer manufactured from a material selected from the group including Ti, W 2, TiW 2, Mo, Pt, and Cu and a Ti silicide, a W silicide, a Mo silicide, and a Pt silicide. Forming a bottom electrode consisting of a second layer selected from the group comprising: an intermetal dielectric layer on the bottom electrode; and a dopant selected from the group comprising arsenic and phosphorus. Doping a bottom electrode, forming an antifuse opening in the intermetal dielectric layer disposed on the bottom electrode, and forming an antifuse material layer in the antifuse opening. Forming an upper electrode comprising a second interconnect layer on the antifuse material layer. Method of manufacturing a tee fuse element. 12. The method further comprises the step of forming an etch stop layer between the intermetal dielectric layer and the bottom electrode, wherein the step of forming the antifuse opening comprises opening the etch stop layer through the etch stop layer. The method of claim 11 including the step of forming. 13. The method of doping the lower electrode, 5xl0 ^l4 to 2Xl0 ^l6 method according to claim 11 in which the arsenic concentration of atoms / CM ² which comprise doping the lower electrode.