JPH06195301A - Data transfer method - Google Patents

Abstract

PURPOSE:To simplify a data transfer processing of synchronous data. CONSTITUTION:When a full state of a dual port memory is detected by a deviation counter 60, generation of data of an (image) data generating circuit is stopped by an operation stop signal from a latch 63, and write to the dual port memory 10 is inhibited. When the data is read out of the dual port 10 and the deviation counter 60 detects a fact that the full state is obviated, an operable signal is generated from the latch 63, generation of the data of the data generating circuit is started, and write of the data to the dual port memory 10 is permitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method for transferring a digital signal generated asynchronously to a signal processing circuit for synchronous processing.

[0002]

2. Description of the Related Art In recent years, in order to store image information in a storage medium, it has been performed in recent years to store a large amount of image information in the storage medium by compressing the image information. The compressed image is read and decompressed during reproduction. The bit amount per pixel of the compressed image is affected by the high frequency components included in the video signal in the vicinity of the pixel, and the bit amount differs for each pixel.
Therefore, the reading of the compressed image data read from the storage medium is asynchronous. On the other hand, in order to display the expanded image data on the display device, the compressed image data must be expanded in synchronization with the scan signal of the display device.
For this reason, conventionally, asynchronously generated image data to be expanded is temporarily stored in a buffer, and the image data is read from the buffer in synchronization with a scan cycle to perform synchronization adjustment.

If the asynchronous image data generation speed, that is, the writing speed to the buffer and the reading speed from the buffer are too different from each other, the buffer overflows or underflows, resulting in a drop in the transferred image data. Will occur. Therefore, in the conventional method, the generation rate of the image data is controlled so that the storage capacity of the buffer falls within, for example, 1/4 to 3/4 of the maximum storage capacity.

[0004]

However, the circuit configuration for changing the generation rate of image data is complicated and expensive. Also, all storage areas of the buffer are
Since it is not used all the time, the use efficiency of the memory is wasted.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a data transmission method that does not require complicated control processing and has a high memory usage efficiency.

[0006]

In order to achieve such an object, according to the present invention, a plurality of first data, which are sequentially and asynchronously generated in a data generating circuit, are temporarily stored in a buffer, and a fixed number of them are stored. Asynchronous first by reading in a cycle
In the data transfer method of converting the data of the above item into the synchronous second data and transferring the data, it is detected whether or not the storage state of the buffer is full, and the buffer is full based on the detection result. In some cases, the generation of the first data by the data generation circuit is permitted, and when the buffer is not full, the generation of the first data by the data generation circuit is prohibited. .

[0007]

According to the present invention, when the buffer is full, the generation of data is stopped, so that the buffer overflow is prevented.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings.

A feature of the present invention is that the buffer is filled in advance and writing to the buffer is permitted each time image data is read from the buffer.

An example of a circuit for realizing such a function is shown in FIGS. 1 and 2.

FIG. 1 shows a circuit configuration for controlling writing into the buffer after the buffer is full, and FIG. 2 shows a circuit configuration for filling the buffer as an initial process.

(A) Initial processing In FIG. 2, image data from a circuit (not shown) that generates asynchronous image data is transferred to the dual port memory 10 via the data bus 20. In addition to the image data, an address signal is transferred to the decoder 22 via the address bus 21 and a write signal (hereinafter abbreviated as W signal) to the decoder 22 via a dedicated signal line. The decoder 21 generates a pulse signal when the W signal is generated and the address indicated by the address signal corresponds to the address space assigned to the dual port memory 10.

The counter 23 increments (updates) the count value by inputting the pulse signal of the decoder 22, and inputs the count value to the dual port memory 10 as an address.

A ring counter is used as the counter 23. When the counter 23 counts the same address value as the highest address of the dual port memory 10, the counter 2
The count value of 3 is automatically reset to the same address value as the lowest address of the dual port memory 10. The count value of the counter 23 is also input to the comparator 25. The comparator 25 stores the value stored in the register 24, that is,
The highest address value of the dual port memory 10 is input, and the comparator 25 compares the count value of the counter 23 with the register 24. Comparator 2
When the coincidence signal is output from 5, the designated address of the counter 23 for the dual port memory 10 is the highest address of the dual port memory 10.
Therefore, the coincidence signal (level on) of the comparator 25 is held by the latch 52 and then converted to level off by the gate 53. This level-off signal is supplied to the image data generation circuit as an operation stop signal.

Further, the coincidence signal of the comparator 25 is held in the latch 34 and supplied to the decoder 32 as an enable (operable) signal.

As a result, the decoder 32 starts the identification of the second address signal from the decompression circuit (not shown), the read signal (abbreviated as R signal) is generated, and the second address signal is the address space of the dual port memory 10. , The pulse signal is supplied to the counter 31. Counter 31
The counter 32 increments the count value by inputting a pulse signal from the decoder 32, and supplies the count value to the dual port memory 10 as a read address.

In the circuit of FIG. 2 described above, the level-off mismatch signal is output from the comparator 25 when the power is turned on, and is converted into the level-on operable signal by the gate circuit 53. The image data generating circuit sequentially generates image data (first data signal) in response to the operable signal and supplies the image data to the dual port memory 10. This image data is sequentially written into the address of the dual port memory 10 designated by the counter 23.

When the image data is written up to the highest address of the dual port memory 10, the comparator 25 outputs a level-on coincidence signal. As a result, a level-off operation stop signal is output from the gate circuit 53, and the image data generation circuit stops the generation of image data.

It should be noted that the latch 52, after the above initial processing,
Since the level-off signal is held and output, the operable / stop signal generated in the circuit of FIG. 1 is supplied to the image data generation circuit via the gate circuit 53.

(B) Image data transfer process In FIG. 1, when the dual port memory 10 becomes full, the coincidence signal of the comparator 25 of FIG. 2 is held in the latch 64, and the deviation counter 60 starts its operation. The deviation counter 60 increments the count value by +1 each time the R signal generated on the decompression circuit side is input, and decrements the count value by -1 each time the W signal generated on the image data generation circuit side is input. A plurality of bits of OR logic indicating the count value of the deviation counter 60 are held in the latch 63 and supplied as an enable / disable signal after initial processing to the image data generating circuit.

In such a configuration, when the dual port memory 10 is full, that is, when the initial processing is completed, the data generating circuit stops its operation and the dual port memory 10 can be read. . Each time the decoder 32 receives the second address signal and the R signal from the decompression circuit, the counter 31 increments the count value, for example, “0” → “1” → “2”.
As a result, the dual port memory address “0” →
The image data is read in the order of “1” → “2” in synchronization with the scan timing. When the counter 31 counts up to the same value as the highest address value of the dual port memory 10, the counter 31 resets the count value to "0" and repeats the same counting process as above.

When the image data of the first address "0" is read, the deviation counter counts "1". The count value "1" is converted into an ON signal by the OR gate 61, and the operable / stop signal held and output from the latch 63 becomes a signal indicating that the level is ON. As a result, the image data generation circuit starts generating image data. At this time, since the instruction address of the counter 23 which generates the read address indicates "0", the dual port memory 1
Image data is newly written in the address "0" of 0.

Thereafter, image data is written in the order of address "1" .fwdarw. "2" every time an operable signal is sequentially generated.

What is noteworthy here is that the image data is written to the address "0" of the dual port memory 10, for example, after the image data of the address "0" is read. Since the deviation counter 60 calculates the difference between the number of generated R signals and the number of generated W signals, the output signal of the latch 63 outputs a level-off operation stop signal while the number of generated signals is equal. Therefore, in the above example, when the image data at the address "0" of the dual port memory 10 is read and new image data is written next, the deviation counter becomes "0" and the image data generating circuit stops the operation. To do.

Next, the time when the image data generating circuit resumes the operation is the time when the image data of the address "1" of the dual port memory 10 is read, that is, the count value of the deviation counter 60 is "0" to "1". It is the time when it became ".

Further, this means that writing to the dual port memory 10 is prohibited while the storage state of the dual port memory 10 is full, and writing to the dual port memory 10 is stopped when the full state is cleared. It has been approved. In addition, dual port memory 10
It does not overtake the read address for the write address.

In this embodiment, if the normal image data average generation speed is set slightly higher than the read speed of the dual port memory 10, it is possible to prevent the read address from overtaking the write address. When the dual port memory is used as the image buffer of the display device, even if the same stored data is read, there is no problem. Therefore, there is no problem even if the average generation rate of image data is set lower than the read rate of the dual port. Does not happen.

Besides the present embodiment, the following example can be realized.

1) In this embodiment, an example in which a dual port memory is used as a buffer for synchronization adjustment has been shown, but the present invention can be realized by using a shift register or the like.

2) In this embodiment, the deviation counter 60 is used as means for detecting the full state of the dual port memory 10.
However, it is preferable to use an appropriate circuit according to the form of a memory circuit used as a buffer.

[0031]

As described above, according to the present invention, since data is transferred while the buffer is kept full, the memory usage efficiency is good and the buffer memory capacity can be made smaller than in the prior art. Further, it is not necessary to change the data generation speed of the data generation circuit as in the conventional case, and only the generation / inhibition of data generation is simply permitted, so that the operation control of the data generation circuit is simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a partial circuit configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a partial circuit configuration of an embodiment of the present invention.

[Explanation of symbols]

 10 Dual Port Memory 20, 30 Data Bus 21, 33 Address Bus 22, 32 Decoder 23, 31 Counter 24 Register 34, 52, 63, 64 Latch 53, 61 Gate Circuit

Claims (1)

[Claims] 1. A plurality of first data, which are sequentially generated asynchronously in a data generating circuit, are temporarily stored in a buffer and are read out at a constant cycle to synchronize the asynchronous first data with a second synchronous data. In the data transfer method for converting the data into data and transferring the data, it is detected whether or not the storage state of the buffer is full, and based on the detection result, when the buffer is full, the data A data transfer method, wherein generation of the first data of the generation circuit is permitted, and generation of the first data of the data generation circuit is prohibited when the buffer is not full.