JPH06180668A - Computer system - Google Patents

Abstract

PURPOSE:To efficiently extend a power management function and control periph eral equipments by effectively utilizing a memory to be overlaid on a main memory. CONSTITUTION:A device driver for an extension suspending/resuming processing is stored inside an SM-RAM 14 utilized for saving a system status and the suspending/resuming processing of an optional device not supported by BIOS is realized by the device driver. In this case, the SM-RAM 14 shares a prescribed address space with the main memory 13 and becomes accessible only when SMI signals are inputted. Thus, even when the device driver for the extension suspending/resuming processing is incorporated, a required memory space is not increased. Thus, the function extension of a suspending/resuming function can be realized in a state where memory resources are effectively utilized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system such as a laptop type or notebook type portable computer and a pen input type portable computer.

[0002]

2. Description of the Related Art In recent years, portable laptop or notebook type portable computers,
Various pen input type portable computers have been developed.

This type of portable computer is constructed so that various peripheral devices can be attached thereto. Some peripheral devices are standard equipment in the computer main body, and some are optionally connected. The management of these peripheral devices is executed by a dedicated program called a device driver resident in a specific address space of the main memory.

In addition, this type of portable computer is provided with a power management function for saving power in order to extend the battery-operable time. This power management function provides various power save modes.

A suspend mode is one of the power saving modes that consumes the least power. In this suspend mode, except for the memory that stores the data required to restart the application program,
Almost every unit in the computer system is powered down.

The data saved in the memory is C just before the computer system is set to the suspend mode.
The status of PU and the status of various peripheral LSIs.

The saving of the status is executed by a suspend routine incorporated in the BIOS (basic input / output program). The BIOS is for controlling the hardware in the system according to a request from the operating system, and includes a group of programs for controlling various hardware devices in the system.

The BIOS suspend routine is a system management interrupt (SMI).
It is configured to be activated in response to an interrupt signal called upt). Since the system management interrupt is the highest priority interrupt, the use of this interrupt enables quick suspend processing.

As described above, the system management interrupt is very effective for activating power control processing such as suspend processing. However, the system management interrupt is not suitable for activating a process using a program resident in the main memory, for example, a peripheral device control process using a device driver.

This is because when a system management interrupt occurs, SM-RAM (System Management RAM)
The memory called is overlaid on the main memory,
This is because a part of the address space of the main memory is prohibited. Therefore, if the device driver resides in the access-prohibited address space, control of the peripheral device cannot be executed.

Further, in recent computers, in order to support the suspend processing of a hardware device connected as an option, it is required to extend the function of the suspend processing. The function expansion of the suspend process can be realized by adding a program for executing power management of each hardware device to the BIOS side.

However, there is a limitation on the address space that can be assigned to the memory (BIOS-ROM) for storing the BIOS. Further, since the optional device is connected as necessary, it is wasteful of memory resources to equip such a program for executing the suspend process of the optional device as standard equipment.

Further, recently, an operating system having a dedicated driver program for the power control function has been developed. This driver program is BI
This is for performing system power management in conjunction with the OS. For example, APM (Advanced Power Management) developed by Intel Corp. and Microsoft Corp.
t) The driver is well known.

Microsoft MS-WINDOW
An operating system such as S can easily and accurately detect the idle state of the CPU such as waiting for a key input. Therefore, utilizing the power control features provided by such operating systems, in response to detecting the idle state of the system,
When the power control of hardware is performed, the performed function can be easily realized.

By cooperating with the hardware control function provided by the BIOS, the power control function of such an operating system can be adapted to a system-specific hardware configuration. In order to cooperate with the hardware control function provided by the BIOS, it is necessary to provide an interface function between the power control function of the operating system and the BIOS. However, as described above, it is actually difficult to add a program for realizing the interface function on the BIOS side due to the problem of the memory space.

[0016]

In the conventional system,
When an overlay memory is used as the main memory, the device driver cannot be started and the peripheral devices cannot be controlled. In addition, it is difficult to expand the function of the power management function provided by the BIOS.

The present invention has been made in view of the above circumstances, and makes it possible to effectively use a memory that overlays a main memory, and efficiently implement peripheral device control and power management function expansion. The purpose is to provide a computer system.

[0018]

Means and Actions for Solving the Problems
In a computer system in which various peripheral devices can be mounted, a part of the address space allocated to the main memory is mapped, and an overlay memory that is permitted access in response to a predetermined interrupt signal and manages the peripheral devices. And a means for activating the device driver program stored in the overlay memory and controlling the peripheral device in response to the interrupt signal. Is the first feature.

In this computer system, since the device driver is stored in the overlay memory, the device driver can be activated in a state where the overlay memory is used. Therefore, even if the device driver in the address space of the main memory cannot be started, it becomes possible to execute the control of the necessary peripheral device.

Further, according to the present invention, in a computer system to which various optional devices can be connected, a part of the address space allocated to the main memory is mapped, and access is permitted in response to a predetermined interrupt signal. And an overlay memory storing a device driver program for executing an extended suspend process for saving the data of the optional device, and a status of the computer system is saved in the overlay memory and the computer system is powered off. Suspend means for executing a suspend process, and an extended suspend for executing an extended suspend process for the option device by activating the device driver program stored in the overlay memory. Suspending means for causing the extended suspending means to execute the extended suspend processing in response to the interrupt signal, and ending the execution of the extended suspend processing by the extended suspending means in response to the interrupt signal. The second feature is that it comprises a means for executing.

In this computer system, the overlay memory stores a device driver program for extended suspend processing for an optional device, and this program realizes functional extension of the suspend processing. In this case, the overlay memory is an overlay of the main memory, and when the interrupt signal is input, a part of the address space allocated to the main memory is mapped to the memory means,
Access allowed. Therefore, even if the device driver program is incorporated, the memory space of the main memory is not affected at all. Therefore, the function extension of the suspend function can be realized while the memory resources are effectively used, and more efficient power control can be performed.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the system configuration of a portable computer according to an embodiment of the present invention.

This portable computer is a pen input type personal computer having a liquid crystal display panel and a transparent tablet provided integrally therewith, and this system includes a CPU 11 and an input / output gate array (I / O).
GA) 12, main memory 13, system management RAM
(SM-RAM) 14 is provided. Main memory 13
The system management RAM (SM-RAM) 14 is connected to the local bus 1.

The system also includes a BIOS-RO.
M15, real time clock (RTC) 16, super integration circuit (SI) 26, liquid crystal controller (liquid crystal CNT) 27, first and second IC card controllers (IC-CNT) 28 and 29, keyboard controller (keyboard CNT) 30. Is provided,
These are ISA (International Standard Associa)
option) system bus 2.

The CPU 11 is a microprocessor 80386SL manufactured and sold by Intel Corporation of the United States.
Or its compatible processor is used. This CPU1
1 is three different operation modes, namely real mode,
It can operate in protected mode and virtual 86 mode. The real mode is a mode in which a maximum 1 Mbyte memory space can be accessed, and the physical address is determined by the offset value from the base address represented by the segment register. Up to 16M protect mode per task
This is a mode in which a memory space of bytes can be accessed, and a physical address is determined using an address mapping table called a descriptor table. The virtual 86 mode is a mode for operating a program configured to operate in the real mode in the protect mode, and the program in the real mode is treated as one task in the protect mode.

The SMI is used as an interrupt for the CPU 11.
(SMI; System Management Interrupt)
Non-maskable interrupt (NMI)
rupt) and maskable interrupt (INTR; Maska)
ble Interrupt). The SMI is a kind of non-maskable interrupt, but it is the highest priority interrupt having a higher priority than the above-mentioned NMI and INTR, and various SMIs related to power saving are activated by activating the interrupt request input SMI of the CPU 11. Service routines can be invoked.

The SMI service routine is roughly classified into a suspend processing routine and a resume processing routine. The suspend process routine is for setting the system to suspend mode as described above.
The saving of the system status in the SM-RAM 14 is executed. The resume processing routine is for returning the system from the suspend mode and restarting the application program from the state before the suspend mode, in which the saved system status and user data are restored.

The I / O gate array 12 is a dedicated logic for realizing the support function of the CPU 11 and the memory, and is the main memory 1 connected to the local bus 1.
3, SM-RAM14, additional memory card 25, CP
Input / output control between U11 and various units connected to the system bus 2 and CPU 11 is performed. Further, the I / O gate array 12 is a unit for realizing a function necessary for system control, that is, a DMA controller for direct memory access control and an interrupt controller (PIC; Programmable).
Interrupt Controller, timer (PIT; Progr)
ammable Input Timer), serial I / O controller (SIO; Serial Input / Output Control)
r) is built in.

CPU 11 and I / O gate array 12
Communication between them is performed via a dedicated interface line. Interface signals between the CPU 11 and the I / O gate array 12 include, for example, signals for controlling the SMI function of the CPU 11.

That is, the interrupt request input SMI of the CPU 11 is supplied with the active-low SMI signal output from the I / O gate array 12. This SMI signal is generated, for example, in response to a request from an internal timer of the I / O gate array 12 or a request from an external unit such as a real time clock (RTC) 16 and a power supply controller (PSC) 31. For example, a request from the power supply controller (PSC) 31 turns on / off the system power.
It is generated when the power switch 311 for the off control is turned off, or when the capacity reduction of the battery 312 (low battery state) is detected. The SMI signal is also generated by a software factor such as a request from the operating system.

The I / O gate array 12 is provided with an SMI factor register 121. This SMI factor register 121 is used for SMI factor register 121 depending on the factor from which device
It is for indicating whether a signal is generated, and is composed of an 8-bit register as shown in FIG. For example, SM is requested by a power supply controller (PSC) 31.
When the I signal is generated, bit 7 (B7) of the SMI factor register 121 is set to "1".

The main memory 13 is, for example, a standard 4M memory.
It has a storage capacity of bytes, and stores an operating system, an application program to be processed, user data created by the application program, and the like. The operating system includes an I / O system that supports pen input, and is configured to operate in the protected mode of the CPU 11. In addition, this operating system includes an APM (Advanced P
OWER Management) driver is installed. This APM driver is an interface for realizing power management in cooperation with the BIOS, and is an extension of the conventional function for calling the BIOS (INT 15h) related to the system service.

The SM-RAM 14 is provided to realize the power management function of the system and has a storage capacity of 32 Kbytes. The SM-RAM 14 has addresses of 60000H to 67FFFH of the main memory 13.
Are mapped to the address spaces up to and are accessible only when the SMI signal is input to the CPU 11. When the system shifts to the suspend mode, the system status necessary for restarting the application program, that is, the status of the CPU 11 registers and various peripheral hardware when the SMI is generated is saved in the SM-RAM 14 in a stack format. It

Further, the SM-RAM 14 is provided with a device driver resident area, and the device driver resident area is provided with a suspend / suspended area provided by the BIOS.
A device driver for expanding the resume function is resident. The SM-RAM 14 can be configured by using a part (empty area) of the main memory 13.

The additional memory card 25 is optionally connected to an 88-pin dedicated card slot provided in the computer body. This additional memory card 25 is a dedicated DRAM card, and has 2M bytes, 4M bytes, and 8M bytes.
There are types such as byte and 16 MB.

The BIOS-ROM 15 is the above-mentioned BIOS.
It is for storing (Basic I / O System) and is composed of a flash memory so that the program can be rewritten. The BIOS is configured to operate in real mode. This BIOS includes an IRT routine for testing and initializing memory and various hardware devices at power-on, various programs for controlling various hardware devices according to a request from the operating system, a suspend SMI routine, and Resume SMI
It includes an SMI service program including routines and the like, and an SMI handler for determining an SMI service routine to be executed.

The SMI handler is a program in the BIOS which is first activated when an SMI occurs, whereby the cause of the SMI is checked and the SMI service routine corresponding to the cause is executed. .

The real time clock (RTC) 16 is
It is a timepiece module having its own battery for operation, and has a CMOS static RAM (hereinafter referred to as a CMOS memory) to which power is constantly supplied from the battery. This CMOS memory is used to store setup information indicating the system configuration. Further, the CMOS memory is provided with an SMI factor flag register 161. This SMI factor flag register 161 stores SM
A flag or the like indicating the result of the SMI factor check by the I handler is set. SMI factor flag register 161
An example of the contents of the above is shown in FIG.

As shown in the figure, the SMI factor flag register 161 is composed of an 8-bit register, and the 4-bit value of bit 3 to bit 0 (B3 to B0) indicates the SMI factor. For example, “0000” indicates that no SMI has occurred, “0001” indicates that a suspend SMI has occurred due to the power switch 311 being turned off, and “100”.
1 "is the resume SM when the power switch 311 is turned on.
Indicates that I has occurred.

Super Integration (SI) 26
Is connected to a power supply controller (PSC) 31 and an RS232C connector 34 and controls communication with these by serial data, while a floppy disk connector (FDD connector) 32 and a printer / floppy disk connector (PRT / FDD connector). 33, a hard disk drive (HDD) 35, and a tablet controller 26, and communication control is performed between them by parallel data.

In addition, the super integration (S
The I) 26 is provided with a status register 261. The status register 261 is for indicating the state of the power supply controller (PSC) 31, and is composed of an 8-bit register as shown in FIG.

Bit 7 of this status register 261
(B7) shows the presence or absence of the low battery state, and is set to "1" when the low battery state is set and to "0" when the low battery state is not set. Bit 6 (B6)
Indicates whether or not the AC adapter 313 is connected, and is set to "1" when the AC adapter is connected and set to "0" when the AC adapter is not connected. Bit 5 (B5)
Indicates ON / OFF of the power switch 311 and is set to “1” when turned off and set to “0” when turned on.

The power supply controller (PSC) 31 is a CP
It is for controlling power supply to each unit according to an instruction from U21, and communication with the CPU 21 is executed via a command register in the super integration (SI) 26. This power controller (PS
C) 31 supplies the SMI generation request signal to the I / O gate array 12 and sets bit 5 of the status register 261 to "0" when detecting the OFF operation of the power switch 311. In addition, the power controller (PS
When C) 31 detects a low battery, it supplies an SMI generation request signal to the I / O gate array 12 and sets bit 7 of the status register 261 to "1".

Further, the power supply controller (PSC) 31
Generates a backup power supply BK even when the system is in a power-off state, and supplies it to the main memory 13, SM-
It is supplied to the RAM 14 and the image memory (VRAM) 38.

The floppy disk connector 32 is a connector used when the floppy disk drive (first FDD) 42 is optionally connected, and the printer / floppy disk connector 33 is used when the printer or floppy disk device (second FDD) 43 is optionally connected. This is the connector used.

The tablet controller 36 detects a coordinate point input by the stylus pen through the transparent tablet 37 and superimposes it on the coordinate point.
6. I / O gate array 12 via system bus 2B
Send to.

The liquid crystal controller 27 controls the display of the liquid crystal display panel 39, expands the display data sent from the CPU 11 via the system bus 2 into the image memory (VRAM) 38, and displays it on the liquid crystal display. Display on panel 39. The liquid crystal display panel 39 has, for example, a vertical length of 64.
The backlight 40 is a transmissive type composed of a dot matrix of 0 dots × horizontal 480 dots, and a backlight 40 using, for example, a fluorescent display tube (hereinafter abbreviated as “FL”) is arranged on the back side thereof.

The IC card controllers 28 and 29 are 6
8-pin PCMCIA (Personal Computer Memory)
Card Alternativeal Associatuon) Card 44, 4
5 read / write control is performed. The keyboard controller 30 controls the key input of the keyboard 46 connected as an option. Next, referring to FIG. 5, the suspend SM of the BIOS after the power switch 311 is turned off.
The operation flow until the I routine is called will be described.

When the power switch 311 is turned off by the operator, the power controller 31 switches it to the CPU.
In order to notify 11, the bit 5 of the status register 261 of the super integration (SI) 26 is set to "1" and the SMI request signal is supplied to the I / O gate array 12. I / O gate array 12
Responds to the SMI request signal from the power supply controller 31, sets bit 7 of the SMI factor register 121 to "1" and supplies a low level SMI signal to the SMI pin of the CPU 11.

A low level S is added to the SMI pin of the CPU 11.
When the MI signal is input, the CPU 11 firstly outputs SM-
RAM14 is the main memory 13 address 60000
It is mapped to 32K bytes from (H) to 67FFF (H) (step S11). As a result, the banks are switched, and the address 600 in the main memory 13
00H to 67FFFH are inaccessible, and SM-RAM 14 is accessible instead.

The memory map of the SM-RAM 14 is shown in FIG.
As shown in. That is, SM-RAM1
4, a CPU state storage area, a hardware state storage area, an SMI device driver area 14
1. An SMI handler work area is provided, and a jump code (JMP) that designates the SMI handler of the BIOS-ROM 15 as an interrupt destination is set.

Next, the CPU 11 saves the contents (CPU state) of various registers of the CPU 11 when the SMI signal is input to the CPU state storage area of the SM-RAM 14 in a stack format (step S12). If the SMI signal is input while the operating system is operating, the CPU state in the protected mode will be saved in the SM-RAM 14. Then, the CPU 11 changes the operation mode of the CPU to the real mode and fetches the jump code (JMP) set at the predetermined address of the SM-RAM 14 (step S13). The processes of steps S11 to S13 up to this point are executed by the microprogram of the CPU 11.

Next, the CPU 11 executes the SMI handler of the BIOS-ROM 15 designated by the jump code (step S14). The SMI handler first checks the cause of the SMI occurrence in order to determine the cause of the SMI occurrence (step S1).
5).

In this processing, the SMI factor register 121
And the contents of the status register 261 are checked. If the SMI is caused by turning off the power switch 311, both bit 7 of the SMI factor register 121 and bit 5 of the status register 261 are "1" as described above.
Is set to. In this case, the SMI handler determines that the SMI is an SMI caused by turning off the power switch 311 and requests execution of the SMI service routine in the BIOS corresponding to the SMI, that is, the suspend SMI routine (step S16). These steps S14 to S
The processing of 16 is executed by the SMI handler. Next, with reference to FIG. 7, a specific structure of the SMI device driver area 141 provided in the SM-RAM 14 will be described.

As shown in FIG. 7, the SMI device driver area 141 includes a device driver address table area 141a and a device driver resident area 14.
1b and a reserved area 141c. Address information corresponding to each device driver is stored in the device driver address table area 141a. This address information is used as a pointer indicating the storage position of each device driver in the device driver resident area 141b. The device driver resident area 141b includes a suspend device driver and a resume device driver for expanding the functions of the suspend / resume processing of the BIOS, and an SM device.
A plurality of other device drivers and the like for power management used at the time of I interrupt reside. Reserved area 141c
Is an area reserved for resident when another SMI handler needs to be provided in the future.

FIG. 8 shows a concrete example of the device driver address table area 141. Here, it is assumed that two device drivers, a suspend device driver and a resume device driver, are stored in the device driver resident area 141b.

Device driver address table area 1
The 41a stores two pieces of address information corresponding to two device drivers, a suspend device driver and a resume device driver. Each piece of address information is composed of an offset address and a segment address.

That is, in FIG. 8, the suspend start offset address and the segment address are address information corresponding to the suspend device driver, and the resume start offset address and the segment address are address information corresponding to the resume device driver. Is. In this way, each address information is composed of the offset address and the segment address because the BI that calls the device driver.
This is because the OS is configured to operate in the real mode of the CPU 11, and the addressing in the real mode uses the offset address and the segment address. Further, by using the segment address, it is possible to access another segment on the main memory 13 other than the address space of the SM-RAM 14. Therefore, add another device driver to the main memory 13 and install it in the BIOS
It is also possible for the MI routine to call.

If the suspending start offset address and the segment address are both 0000 (h), it means that the suspending device driver is not set. Similarly, if the suspending start offset address and the segment address are both 0000 (h), it indicates that the suspending device driver is not set.

Further, an address table valid / invalid flag is set in the device driver address table area 141a. This address table valid / invalid flag is set in the device driver address table area 141.
It indicates whether or not the address information of a is valid. The flag "AA55h" indicates valid, and the others indicate invalid. The following address information is meaningful only when the flag indicates valid. When disabled, it means that the SMI device driver area 141 is used for another purpose other than the function extension of the suspend / resume processing of the BIOS. In this case, the following address information has meaning. Absent.

Next, the operation executed by the suspend SMI routine of the BIOS will be described with reference to FIG. Here, a case where the address information in the device driver address table area 141a is valid will be described as an example.

Device driver address table area 1
If the suspend start offset address and the segment address are set in 41a, the suspend SMI routine calls the suspend device driver prior to the suspend process. This call
Call the address corresponding to the suspend device driver obtained from the suspend start offset address and the segment address read from the device driver address table area 141a (FARCALL)
It is done by doing. At this time, the register contents of the CPU 11 are not changed.

As a result, the suspend device driver is activated and the extended suspend process is executed (step S31). In this extended suspend process, BIO
Data saving is executed for optional devices such as the memory card 25 and the IC card 44, which are not supported in the S suspend routine. In this data save, the user data of the memory card 25, the status of its controller, etc. are saved in the hard disk drive (HDD) 35. Also, memory card 2
Some 5 have a built-in battery and have a backup function, but in this case, only the status is saved. Since the storage space required for saving the status is small, it is possible to save the status in the SM-RAM 14.

When the execution of the extended suspend process is completed, the control is returned to the suspend SMI routine of the BIOS again. Then, the suspend SMI routine executes suspend processing (step S21). In this suspend process, the CPU state and the hardware state are saved in the SM-RAM 14. At this time, the CPU state saved is the value of the CPU register in the real mode. Next, the suspend SMI routine supplies a power-off command to the power supply controller (PSC) 31 via the I / O gate array 12, the system bus 2, and the super integration (SI) 26 (step S22). As a result, the system is set to the suspend mode, and almost all the devices in the system are powered off except for the main memory 13, SM-RAM 14, and image memory (VRAM) 38 to which the backup power BK is supplied. Become.

If the address information in the device driver address table area 141a is not valid, the extended suspend process (step S31) is not executed, but the suspend process of the suspend SMI routine (step S31).
Only 21) will be activated.

Next, the flow of operation from when the power switch 311 is turned on to when the resume SMI routine of the BIOS is activated will be described with reference to FIGS. 10 and 11.

When the power switch 311 is turned on by the operator, the power controller 31 first powers on the system and then notifies the CPU 11 that the power switch 311 has been turned on, in order to notify the super integration (SI) 26. Status register 261
Bit 5 is set to "0" and a reset request signal is supplied to the I / O gate array 12. The I / O gate array 12 supplies a reset signal to the CPU 11 in response to the reset request signal from the power supply controller 31.

When the reset signal is input to the CPU 11, the CPU 11 is automatically set to the real mode.
And the BIO to start up the system
An S IRT (Initial Reliability Test) routine is executed.

The BIOS IRT routine first refers to the system setup information set in the CMOS memory of the real time clock (RTC) 16 to determine which mode, resume mode or boot mode, is designated by the user. Judge (step S4)
1).

If in boot mode, the IRT routine
After performing memory test and hardware test,
The hardware is initialized according to the system setup information set in the CMOS memory, then the operating system is boot loaded into the main memory 13, and the CPU 11 is changed to the protect mode (step S42).

On the other hand, in the resume mode, IRT
The routine issues a software SMI by setting the value of a predetermined internal register of the CPU 11 to "1" and setting the value of a predetermined register of the I / O gate array 12 to "1" (step S43). . Even in this software SMI, the I / O gate array 1
An SMI interrupt signal is supplied from 2 to the CPU 11.

When the SMI signal is issued, the CPU 11
First, the SM-RAM 14 is mapped to 32K bytes from the address 60000H to 67FFFH of the main memory 13 (step S51).
Fetch the jump code (JMP) set at the predetermined address of.

Next, the CPU 11 executes the SMI handler of the BIOS-ROM 15 designated by the jump code (step S52). The SMI handler first checks the cause of the SMI occurrence in order to determine the cause of the SMI occurrence (step S5).
3).

In this processing, the SMI factor register 121
And the contents of the status register 261 are checked. If the SMI is caused by turning off the power switch 311, as described above, the bit 7 of the SMI factor register 121 is set to "1" and the bit 5 of the status register 261 is set to "0". In this case, the SMI handler
It is determined that the SMI is caused by turning on the power switch 311, and a request is made to execute a predetermined SMI service routine of the BIOS corresponding to the SMI, that is, a resume SMI routine (step S54). Next, with reference to FIG. 12, an operation executed by the resume SMI routine of the BIOS will be described.

In the resume SMI routine, first, the suspend SMI flag indicating that the suspend SMI caused by turning on the power switch 311 has occurred is set in the SMI factor flag register 161 of the real time clock (RTC) 16. At this time, the lower 4 bits B3, B2, B1, B0 of the SMI factor flag register 161 are 1,
It is set to 0,0,1.

Next, the resume SMI routine restores the CPU state and hardware state saved in the SM-RAM 14 in the suspend SMI routine (step S61). After this, resume SMI
Routine is the device driver address table area 1
If the resume activation offset address and the segment address are set in 41a, the resume device driver is called prior to the end of the resume process. This call is performed by calling (FAR CALL) an address corresponding to the resume device driver obtained from the resume activation offset address and the segment address read from the device driver address table area 141a. At this time, the register contents of the CPU 11 are not changed.

As a result, the resume device driver is activated and the extended resume process is executed (step S71). In this extended resume process, the data of the optional device such as the memory card 25 saved in the hard disk drive (HDD) 35 is restored.

When the execution of the extended resume process is completed, the control shifts to the resume SMI routine of the BIOS again. The resume SMI routine then executes a predetermined return instruction to return control to the operating system.

As described above, in this embodiment, the SM-RAM 1 used for saving the system status is used.
4 stores a device driver for extended suspend / resume processing, and the device driver realizes suspend / resume processing of an optional device that is not supported by the BIOS.

In this case, the SM-RAM 14 is an overlay memory that shares a predetermined address space with the main memory 13 and can be accessed only when the SMI signal is input. Therefore, even if the device driver for the extended suspend / resume processing is incorporated, the required memory space is not increased. Therefore, the extension of the suspend / resume function can be realized with effective use of memory resources.
More efficient power control can be performed.

Here, the case where the system is set to the suspend mode by turning off the power switch 311 has been described, but not only when the power switch 311 is turned off, but also when the low battery state is detected by the power controller 31. , Which puts the system in suspend mode. The suspend process in this case is also the same as that executed by turning off the power switch 311. The extended suspend process for the optional device and the normal suspend process by the BIOS are jointly executed.

Further, as the device driver stored in the SM-RAM 14, not only the one for power control as described above, but also a device driver for controlling various peripheral devices such as a printer, a mouse and a keyboard is incorporated. You can also With this configuration, the control processing of the peripheral device can be activated by the SMI, and the peripheral device can be quickly controlled without affecting the application program being executed. Next, a second embodiment of the present invention will be described.

In the second embodiment, the interface driver between the APM driver of the operating system and the BIOS is stored in the SM-RAM 14, and the interface driver is used to realize the power management of the system. Is. First, the principle of power management using the APM driver will be described with reference to FIG.

Power management using the APM driver is performed by the APM driver (APM-) of the operating system.
S), the BIOS APM-SMI routine, and SM-
It is realized by the device driver (APM-M) for the APM interface stored in the RAM 14.

The APM driver (APM-S) of the operating system is an extension of the function for calling the BIOS (INT 15h) related to the conventional system service. Such an APM driver (APM
In the system using -S), the following power management is executed.

For example, when the application program is waiting for key input, etc., the APM driver (AP
M-S) notifies the BIOS of the idle state of "waiting for key input". This allows the BIOS
The power management function of is started, and power control for various hardware is executed. In addition, the APM driver (APM
-S) periodically calls the power control function of the BIOS regardless of the idle state of the system,
Checks if it requires power control processing.
APM driver (APM-S) if required
Notifies the application program or various device drivers in the system of the fact and checks whether or not the power control process can be executed. If it is executable, the BIOS is notified of that fact and the power control process is performed. The power control process of the BIOS executed in conjunction with the APM driver (APM-S) is executed by the APM-SMI routine.

Communication between the APM-SMI routine of this BIOS and the APM driver (APM-S) is performed by the APM.
Interface device driver (APM-M)
Through. That is, the BIOS calls a device driver (APM-M) for the APM interface to receive a request from the APM driver (APM-S) and notify the APM driver (APM-S).

The APM driver (APM-S) in the operating system in this embodiment is, for example, MS-WIN developed by Microsoft Corp.
It is the same as the APM driver installed in DOWS3.1. Also, device driver (APM-M)
Is installed when the APM driver (APM-S) is installed.

FIG. 14 shows a concrete example of the device driver address table area 141 when the APM interface device driver (APM-M) is stored in the device driver resident area 141b of the SM-RAM 14.

The APM interface device driver (APM-M) is composed of an APM-SMI preprocessing unit and an APM.
-SMI post-processing unit. In this case, two address information corresponding to the APM-SMI pre-processing unit and the APM-SMI post-processing unit are stored in the reserved area of the device driver address table area 141. Each piece of address information is composed of an offset address and a segment address.

That is, in FIG. 14, APM-SM
The I preprocessing start offset address and segment address are address information corresponding to the APM-SMI preprocessing section, and the APM-SMI postprocessing start offset address and segment address are APM-S.
It is address information corresponding to the MI post-processing unit.

In this way, when the APM interface device driver (APM-M) is stored in the SM-RAM 14, the address information corresponding to it is added to the device driver address table area 141.

Next, referring to FIG. 15, APM-SMI
The specific operation of the routine will be described. Here, it is assumed that the APM-SMI routine of the BIOS is activated by a request from the APM driver (APM-S) of the operating system.

The APM driver (APM-S) uses various interfaces (IN) to notify the idle notification from the kernel.
When received via the T15h interface, 16-bit interface, 32-bit interface (steps S81 to S83), BIOS APM-SM
The I routine is activated (step S84). This APM
In the SMI routine start-up process, a flag indicating the generation of the APM-SMI request is set in a predetermined register of the CMOS memory, and the software SMI is issued. The BIOS SMI handler is a software SMI.
, Which indicates that an APM-SMI request has occurred, the APM-SMI routine is activated.

Device driver address table area 1
If address information is set in 41a, A
The PM-SMI routine performs APM-SMI pre-processing call, APM-corresponding processing, and APM-SMI post-processing call (steps S91, S92, S93).

The APM-SMI preprocessing call is performed by calling (FAR CALL) an address obtained from the APM-SMI preprocessing start offset address and segment address read from the device driver address table area 141a.

This call causes the APM-SMI pre-processing unit to execute, and the APM-SMI pre-processing unit executes BI
Various statuses are notified to the APM-SMI routine of the OS (step S95). APM-SM
The I routine executes the corresponding power control process according to the request from the APM driver (APM-S) notified by the status notification (step S).

For example, when the generation of the suspend request from the upper program is notified by the preprocessing call,
The APM-SMI routine executes suspend processing (saving of system status) regardless of boot mode / resume mode. In this case, no APM-SMI post-processing call is made.

When the generation of the HDD ready request is notified by the preprocessing call, the APM-SMI routine executes
Set the HDD motor to the ON state, then APM-S
Make a post-processing call to MI.

When the generation of the HDD off request is notified by the preprocessing call, the APM-SMI routine returns H
Set the DD motor to the off state, then APM-SM
I post-process call.

When the generation of the display ready request is notified by the pre-processing call, the APM-SMI routine sets the liquid crystal display panel 39 to the ON state (lighting of the backlight unit, etc.), and then the APM-SMI routine. Make a post-processing call to SMI.

When the generation of the display-off request is notified by the pre-processing call, the APM-SMI routine sets the liquid crystal display panel 39 to the off state (turning off the backlight unit, etc.), and then the APM-SMI routine. Make a post-processing call to SMI.

When the tablet ready request is notified by the pre-processing call, the APM-SMI routine sets the tablet 37 to the ON state (power-on for tablet), and then the APM-SMI post-processing. Make a call.

When the occurrence of the tablet-off request is notified by calling the pre-processing, the APM-SMI routine sets the tablet 37 to the off state (power-off for tablet), and then the post-processing of APM-SMI. Make a call.

The post-processing call is executed by the APM-SM read from the device driver address table area 141a.
I Call address obtained from start offset address for post-processing and segment address (FAR CAL
L) is performed.

By this call, the APM-SMI post-processing section is executed, and the APM-SMI post-processing section returns an end status and the like to the APM driver (APM-S). After that, the process returns from the APM-SMI routine of the BIOS to the APM driver (APM-S) and returns to the upper program (steps S85 and S86).

As described above, in the second embodiment, the device driver (APM-S) for the interface between the BIOS and the APM driver (APM-S).
Since M) is registered in the SM-RAM 14, it is possible to achieve both effective use of memory resources and realization of an advanced power management function.

[0108]

As described above in detail, according to the present invention,
By storing the device driver in the memory that overlays the main memory, the overlay memory can be effectively used, and the peripheral device control and power management function expansion can be efficiently realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of a portable computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary view showing an example of an SMI factor register provided in the computer system of the embodiment.

FIG. 3 is an exemplary diagram showing an example of an SMI factor flag register provided in the computer system of the embodiment.

FIG. 4 is an exemplary diagram showing an example of a status register provided in the computer system of the embodiment.

FIG. 5 shows the SM in the computer system of the embodiment.
BIOS Suspend SMI after I interrupt occurs
The figure for demonstrating operation until a routine is called.

FIG. 6 is a diagram showing an example of a memory map of the SM-RAM provided in the computer system of the embodiment.

7 is a diagram showing the configuration of an SMI device driver area of the SM-RAM shown in FIG.

8 is a diagram showing a specific example of a device driver address table area provided in the SMI device driver area shown in FIG. 7. FIG.

FIG. 9 is a BI in the computer system of the embodiment.
6 is a flowchart illustrating an OS suspend SMI routine.

FIG. 10B in the computer system of the embodiment
6 is a flowchart illustrating an IRT routine of IOS.

FIG. 11 is an S diagram of the computer system of the embodiment.
BIOS resume SM after MI interrupt occurs
The figure for demonstrating operation until I routine is called.

FIG. 12B in the computer system of the same embodiment
6 is a flowchart illustrating a resume SMI routine of IOS.

FIG. 13A in the computer system of the same embodiment
The flowchart explaining the power management operation using a PM driver.

FIG. 14 S in the computer system of the embodiment
The figure which shows the specific example of the device driver address table area at the time of incorporating the interface driver corresponding to an APM driver in M-RAM.

FIG. 15A in the computer system of the same embodiment
6 is a flowchart illustrating an example of a specific power management process using a PM driver.

[Explanation of symbols]

11 ... CPU, 12 ... I / O gate array, 13 ... Main memory, 14 ... SM-RAM, 15 ... BIOS-RO
M, 16 ... Real-time clock, 31 ... Power supply controller, 141 ... SMI device driver area, 141
a: device driver address table area, 141b
... Device driver resident area, 141c ... Reserved area.

Claims (7)

[Claims] 1. An overlay memory in which a part of an address space allocated to a main memory is mapped in a computer system to which various peripheral devices can be attached and which is permitted access in response to a predetermined interrupt signal, An overlay memory storing a device driver program for managing the peripheral device, and means for activating the device driver program stored in the overlay memory and executing control for the peripheral device in response to the interrupt signal. A computer system comprising: 2. In a computer system to which various optional devices can be connected, an overlay memory in which a part of an address space allocated to a main memory is mapped and access is permitted in response to a predetermined interrupt signal, An overlay memory that stores a device driver program for executing an extended suspend process that saves the data of the optional device, and a suspend process that saves the status of the computer system in the overlay memory and powers off the computer system Suspending means for executing, and an extended suspending means for activating the device driver program stored in the overlay memory to execute extended suspend processing for the optional device, A unit for causing the extended suspending unit to execute the extended suspending process in response to the interrupt signal; and a unit for causing the suspending unit to execute the suspending process in response to completion of execution of the extended suspending process by the extended suspending unit. A computer system comprising: 3. The means for causing the suspend means to execute the suspend process detects whether or not the device driver program is stored in the overlay memory, and when the device driver program is not stored, the suspend means causes the suspend means to suspend. The computer system according to claim 2, further comprising means for executing a process. 4. The computer system according to claim 2, wherein the suspending means includes a basic input / output program for controlling hardware of the computer system. 5. A power supply switch means for controlling on / off of the power supply of the computer system, and means for detecting an off operation of the power supply switch means and generating the interrupt signal in response to the detection. The computer system according to claim 2, wherein: 6. A power management method in a computer system to which various optional devices can be connected, the step of detecting an off operation of a power switch, and a predetermined overlay on the main memory in response to the detection of the off operation of the power switch. Responding to the step of permitting access to the overlay memory, the step of starting a predetermined device driver program stored in the overlay memory to save the data of the option device, and the end of the save processing of the data of the option device. And saving the status of the computer system in the overlay memory, and powering off the computer system. 7. A computer system, which is a system management means located between hardware of the computer system and an application program and managing the operation of the system, wherein various power save requests are issued in accordance with an idle state of the system. A system management means having a power management means for issuing, a hardware control means for executing power control of the hardware of the computer system, and a part of the address space allocated to the main memory are mapped, and a predetermined interrupt signal And an overlay memory for storing an interface program for an interface between the power management means provided in the system management means and the hardware control means. A means for generating the interrupt signal in response to a power save request from the power management means provided in the system management means, and an interface program activated in response to the interrupt signal for the hardware control means. And a means for executing hardware power control according to the power save request.