JPH06188400A - Photoelectric conversion device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To provide a photoelectric converter at a low cost by simplifying the production process, improving the yield of process and efficiently utilizing the materials. CONSTITUTION:In a photoelectric converter having at least a MIS type photodiode 10 and a switch element 11 on the same substrate, a semiconductor layer for MIS type photodiode 10 and switch element 11 is made of the same semiconductor material deposited in the same process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device used in facsimiles, image readers, digital copying machines and the like, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Next, the prior art of the photoelectric conversion device of the present invention will be described. Conventionally, a reading system using a reduction optical system and a CCD type sensor has been used as a reading system of a facsimile, an image reader, a digital scanner, etc., but in recent years, hydrogenated amorphous silicon (hereinafter referred to as a
-Si: H) represented by a thin film semiconductor material has been developed to form a photoelectric conversion element and a switching element on a long substrate and read by an optical system at the same magnification as the original, a so-called long contact type. The development of this photoelectric conversion device is remarkable.

This a-Si: H is used not only as a semiconductor for photoelectric conversion but also as a field effect thin film transistor (hereinafter, referred to as T
Since it can also be used as a semiconductor material of FT),
A method has also been devised in which a TFT is used as a switching element, a semiconductor layer of the photoelectric conversion element and a semiconductor layer of the TFT are both formed using a-Si: H, and they are formed on the same substrate together with a wiring matrix. ing.

Further, in order to increase the reading speed and realize high gradation reading, a pin type photodiode using a-Si: H is used as a photoelectric conversion element, and an image reading is made on a substrate together with a TFT and a wiring matrix. The device is also being developed.

FIG. 52 is a partial cross-sectional view showing the structure of the conventional photoelectric conversion device described above.

In the figure, 30 is a pin using a-Si: H.
Is a photoelectric conversion element formed of a photodiode, 31 is a switch element formed of an inverse stagger type thin film transistor having a-Si: H as a semiconductor layer, and 3
2 is a wiring matrix.

The photodiode has a metal lower electrode 22-
1, n-type a-Si: H layer 25, intrinsic a-
Si: H layer 24, p-type a-Si: H layer 23, and ITO (Indium Tin Oxide) 26- as an upper electrode
1. The TFT includes a metal gate electrode 22-2, an insulating layer 27, and an intrinsic aS.
The i: H layer 28-1, the n-type a-Si: H layer 28-2, the source electrode 29-6, and the drain electrode 29-5 are included. The wiring matrix has the same layer structure as that of the TFT, and aims at simplification of the process.

A method of operating a photoelectric conversion device using such a photodiode and TFT will be briefly described. Fig. 53
Is the single-bit equivalent circuit.

Normally, the photodiode S is reverse biased by V _S , and its parasitic capacitance C _S is accumulated and charged. When light is applied to the photodiode in this state,
The charged electric charge is discharged. Then turn on the switch SR
By setting the state, a charging current flows so as to supplement the discharged charge, and C _s is charged again. At the same time, the load capacitor C _L is charged at an amount commensurate with the discharge current. Switch SR is turned off, switch ST
Is turned on, the charge accumulated in C _L is read out to the outside and is output from Sout.

The manufacturing process of such a conventional photoelectric conversion device will be described below with reference to the drawings.

54 to 64 show the flow of each step.

First, as shown in FIG. 54, a first metal Cr is deposited on the cleaned glass substrate 21 by a vacuum evaporation method at 1000 angstrom.

Next, as shown in FIG. 55, a resist pattern having a desired shape is formed by using photolithography, and C is formed by wet etching using the resist pattern as a mask.
Etching r, lower electrodes 22-1, 22-2, 22-
3 is formed.

Next, as shown in FIG. 56, plasma CV
Using the D method, an n-type a-Si: H layer 25 of 1000 angstrom is deposited using PH ₃ gas and SiH ₄ gas as raw materials. Subsequently the SiH ₄ gas as a raw material, the intrinsic semiconductor layer 24 was 5000 Å is deposited, then, B ₂ H ₆ gas, a SiH ₄ gas as a raw material, boron-doped p-type a-Si: H layer 23 10
Deposit 0 Å.

Next, as shown in FIG. 57, ITO of 1000 Å is formed as a transparent electrode by a sputtering method.

Next, as shown in FIG. 58, a desired resist pattern is formed by photolithography, and unnecessary ITO is removed by wet etching using the resist pattern as a mask to form an upper electrode 26-1 of the photodiode.

Next, as shown in FIG. 59, using the resist pattern used in FIG. 45 as it is as a mask, unnecessary portions of the n layer, i layer and p layer are removed by dry etching to form a photodiode 30.

Next, as shown in FIG. 60, plasma CV
According to the D method, using NH ₃ gas and SiH ₄ gas as raw materials,
Insulating layer Amorphous silicon nitride layer 27 is deposited to 3000 angstroms. Further, an intrinsic a-Si: H layer 28-1 is deposited using SiH ₄ gas as a raw material. Subsequently, the n-type a-Si: H layer 28-2 is deposited to 500 angstroms using PH ₃ gas and SiH ₄ gas as raw materials.

Next, as shown in FIG. 61, a desired resist pattern is formed by using photolithography, and the silicon nitride layer, i layer and n layer are etched by dry etching using the resist pattern as a mask to form a TFT and a wiring matrix. The silicon nitride layer, i layer, and n layer are patterned, and the contact hole 33 is formed.

Next, as shown in FIG. 62, Al is deposited as a second metal layer at 15000 angstrom by the vacuum evaporation method.

Next, as shown in FIG. 63, a desired resist pattern is formed by photolithography, and unnecessary Al is removed by wet etching using the resist pattern as a mask.
The source electrode 29-6, the drain electrode 29-5 of the TFT,
An upper electrode 29-7 of the wiring matrix is formed.

Next, as shown in FIG. 64, using the resist mask shown in FIG. 63 as it is, the unnecessary n-type a-Si: H layer such as the channel portion of the TFT is removed by dry etching.

Finally, a protective layer is formed using an organic resin or the like (not shown).

A photoelectric conversion device is produced by the above steps.

[0025]

The problems of the above-mentioned photoelectric conversion device will be described below.

In the photoelectric conversion device of the above-mentioned conventional example, the semiconductor layer of the photodiode and the semiconductor layer of the TFT are manufactured in separate steps, and since patterning is performed by photolithography in each step, the formed a- S
The utilization efficiency of the i: H film is very poor. Moreover, the number of manufacturing steps is large and complicated, which leads to a decrease in yield and an increase in cost, and there is a problem that the advantage of integrally forming on the same substrate cannot be utilized.

[0027]

A first photoelectric conversion device of the present invention is a photoelectric conversion device having at least a MIS type photodiode and a switch element on the same substrate, wherein the MIS type photodiode and the It is characterized in that the switch element and the semiconductor layer are made of the same semiconductor material deposited in the same step.

According to the first method of manufacturing a photoelectric conversion device of the present invention, at least M of the MIS type photodiode is formed on the substrate.
A step of forming a metal layer to be an electrode forming an IS junction and a gate electrode of a switch element; and forming a first insulating layer on the metal layer to form a first insulating layer on the electrode forming a MIS junction of the MIS photodiode. The method further includes the steps of forming a second insulating layer after removing the first insulating layer, and forming a semiconductor layer on the second insulating layer.

A second photoelectric conversion device of the present invention is a photoelectric conversion device having at least a Schottky type photodiode and a switch element on the same substrate, and a semiconductor layer of the Schottky type photodiode and the switch element. Is composed of the same semiconductor material deposited in the same step.

The second method for manufacturing a photoelectric conversion device of the present invention comprises a step of forming at least an electrode forming a Schottky junction of a Schottky type photodiode and a metal layer serving as a gate electrode of a switch element on a substrate, and the metal layer. A step of forming an insulating layer on the insulating layer, removing the insulating layer on the electrode forming the Schottky junction of the Schottky type photodiode, and then forming a semiconductor layer on the insulating layer.

A third photoelectric conversion device of the present invention is a photoelectric conversion device comprising at least a Schottky type photodiode, a switch element and a wiring matrix on the same substrate, wherein the Schottky type photodiode and the switch element are provided. And the wiring matrix and the semiconductor layer are made of the same semiconductor material deposited in the same step.

A third method of manufacturing a photoelectric conversion device according to the present invention comprises an intrinsic hydrogenated amorphous silicon layer,
The n-type hydrogenated amorphous silicon layer is formed on the substrate in this order and then patterned to simultaneously form the semiconductor layers of the Schottky type photodiode, the switch element and the wiring matrix.

[0033]

According to the first photoelectric conversion device of the present invention and the method of manufacturing the same, the manufacturing process is simplified by forming the semiconductor layers of the MIS photodiode and the switch element from the same semiconductor material deposited in the same process. The present invention provides a photoelectric conversion device that is low in cost and low in cost in combination with the improvement of manufacturing process yield, efficient use of materials.

In the second photoelectric conversion device of the present invention and the method for manufacturing the same, the manufacturing process is simplified by forming the semiconductor layers of the Schottky type photodiode and the switch element from the same semiconductor material deposited in the same process. The present invention provides a photoelectric conversion device that is low in cost and low in cost in combination with the improvement of manufacturing process yield, efficient use of materials.

The third photoelectric conversion device of the present invention and the method for manufacturing the same are manufactured by configuring the Schottky type photodiode, the switch element, and the semiconductor layer of the wiring matrix with the same semiconductor material deposited in the same step. The present invention provides a low-cost and inexpensive photoelectric conversion device, which simplifies the process, improves the yield of the manufacturing process, and efficiently uses materials.

[0036]

Embodiments of the first photoelectric conversion device of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, 10 is a MIS type photodiode, 11 is a TFT, and 12 is a wiring matrix.
On the substrate 1, a photodiode lower electrode 2-1, a wiring matrix lower electrode 2-3, and a TFT gate electrode 2-2 are formed by the first metal layer. The first amorphous silicon nitride film 3- is formed on the lower electrode and the substrate 1.
A first amorphous silicon nitride film 3-2, an intrinsic a-Si: H layer 4 and an n-type a-Si: H layer 5 are formed in this order. The first amorphous silicon nitride layer 3-1 is an interlayer insulating layer in the wiring matrix, T
The main purpose is to function as a gate insulating layer in the FT, and the second amorphous silicon nitride layer 3-2 is mainly intended to function as an insulating layer that constitutes a MIS connection in a MIS type photodiode.

However, in the MIS type photodiode portion, the first amorphous silicon nitride layer is removed before the second amorphous silicon nitride layer is formed, and the lower electrode 2-1 and the semiconductor layer 4 are removed. Two amorphous silicon nitride layers 3-2 are sandwiched to form a MIS connection. Furthermore, after forming a via hole for connecting the first and second metal layers, a second metal layer is formed. Second
The metal layer and the n-type a-Si: H layer are selectively removed by appropriate patterning to form a wiring matrix, source and drain electrodes in the TFT, another semiconductor of the MIS type photodiode portion, and an electrode junction. . M
Although the second metal layer is removed in the IS type photodiode portion, the n-type a-Si: H layer is left as it is, and the ohmic junction is made with the semiconductor, and the incident light L receives the n-type a-Si: H.
Through the i layer.

The feature of this embodiment is that the i layer is commonly used for the MIS type photodiode and the TFT, and is formed in the same manufacturing process.

FIG. 2 shows a 1-bit equivalent circuit for operating the photoelectric conversion device having the configuration shown in FIG. To briefly explain the operation, the MIS photodiode S is applied with the reverse bias V _s through the switch SR, and the parasitic capacitance C _{s of the} photodiode is charged. next,
When the switch SR is turned off and the bias is removed, the light causes
The electric charge stored in the parasitic capacitance Cs is discharged according to the discharge time. After a certain discharge time, connect the switch ST, and transfers to the capacitor C _x for reading out the residual charges of the parasitic capacitance C _s. Then, switch ST is closed and switch S
By opening Wout, the voltage appearing at the resistor R is output. In the figure, the switch SWout and the resistor R are external ICs. Others are built on the substrate.

A contactless one-dimensional photoelectric conversion device of lensless type having the cross-sectional structure shown in FIG. 1 and constituted by using a plurality of single-bit circuits shown in FIG. 2 using a matrix switch array is shown in FIGS. It is FIG.

FIG. 3 shows a plan view of two pixels, FIG. 4 is a sectional view taken along line BB in FIG. 3, and FIG. 5 is a sectional view taken along line CC of FIG.

3 to 5, 10 is a photodiode, 11-a is a transfer TFT, and 11-b is a charging TF.
T, 12-1 is a TFT gate wiring matrix, 12-2
Indicates a signal wiring matrix, and W indicates a lighting window. In addition, in order to avoid complexity in the drawing, the semiconductor layer and the insulating layer are not shown.

As shown in FIG. 4, the lensless type here means that light enters from the side opposite to the sensor surface of the substrate and illuminates the original surface P through the light-collecting window W of the substrate. However, the scattered light is received by the sensor without using a special optical system.

FIG. 6 shows an equivalent circuit of the photoelectric conversion device. FIG. 7 shows a timing chart of the gate voltage pulse.

In FIG. 6, S _i1 , S _i2 , ..., S _iN
(Hereinafter referred to as S _i ) is the photoelectric conversion element 1 in the i block.
It is a photodiode showing 0. C _i1 , C _i2 , ...
., C _iN (hereinafter, referred to as C _i ) represents the parasitic capacitance of the photodiode. ST _i1 , ST _i2 , ..., ST _iN (hereinafter referred to as ST _i ) are for transfer for transferring the charge of the parasitic capacitance C _i to the load capacitors C _x1 , C _x2 , ..., C _xN . Switch, SR _i1 , SR _i2 , ..., SR _iN (hereinafter,
It is referred to as SR _i . ) Is a charging switch for charging the parasitic capacitance C _i in advance. TF in this example
The switch 11 using T includes a transfer switch ST _i ,
And a charging switch SR _i . Sig _i1 , Si
g _i2 , ..., Sig _iN are individual electrodes in the i block forming the signal line matrix.

These photodiode S _i , parasitic capacitance C _i , transfer switch ST _i and charging switch SR _i
Are arranged in a single row array and are divided into N × M blocks.

Transfer switches ST arranged in an array
_i and the gate electrode of the charging switch SR _i are connected to the wiring 12-1 formed in the matrix. The gate electrodes of the charging switches SR _i in the same block are commonly connected to G _i , and the gate electrodes of the transfer switches ST _i are the common line G of the gate electrodes of the charging switches SR _{i + 1 in} the next order. It is commonly connected to _{i + 1} .

[0049] In the timing shown in FIG. 7, the gate driving line _{(G 1, ···, G M} ) sequentially selects a pulse from the gate driver 14 to _{(V G1, V G2, ···} , V GM) is Is applied. When the gate drive line G ₁ is selected, the charging switches SR ₁₁ , SR ₁₂ , ..., SR _1N for the first block are turned on.
A reverse bias is applied to the photodiodes S ₁₁ , S ₁₂ , ..., S _1N through the bias V _s , and the parasitic capacitances C ₁₁ , C ₁₂ , ..., C _1N are charged.

Next, through the gate driving line G _1, charging switch SR _11, SR _12, · · ·, the SR _1N becomes OFF state, during the subsequent predetermined time T _s, the parasitic capacitance C _11,
The charges charged in C ₁₂ , ..., C _1N are discharged by light, and charges corresponding to the amount of light remain. When the gate drive line G ₂ is selected after a certain time T _s , the transfer switch ST ₁₁ ,
ST ₁₂ , ..., ST _1N are turned on, and parasitic capacitance C
_11, C _12, · · ·, charges remaining in the C _1N is the individual electrode Sig _11, Sig _12, · · ·, through Sig _1N, load capacitor C _x1, C _x2, · · ·, a C _XN Transferred.
The charges are sequentially sent to the signal processing unit 15, converted into a serial signal, and output. The same operation is performed for each block, and the information on the line is read.

The method for manufacturing the photoelectric conversion device of this embodiment will be described below. 8 to 17 are partial cross-sectional views schematically showing each manufacturing process of this embodiment.

First, as shown in FIG. 8, C was formed on the cleaned glass substrate having good flatness by the vacuum deposition method.
r (first metal layer) 2 is deposited to 1000 angstroms.

Next, as shown in FIG. 9, the resist pattern is processed into a desired shape by photolithography,
Using it as a mask, unnecessary Cr is removed by wet etching, whereby the lower electrodes 2-3 of the wiring matrix and MI are removed.
The lower electrode 2-1 of the S-type photodiode and the gate electrode 2-2 of the TFT are formed.

Next, as shown in FIG. 10, plasma CVD
Method using SiH ₄ gas and NH ₃ gas as raw materials
Insulating layer amorphous silicon nitride 3-1 is deposited to 3000 angstroms. This functions as an interlayer insulating film in the wiring matrix and as a gate insulating film in the TFT.

Next, as shown in FIG. 11, the resist pattern is processed into a desired shape by photolithography,
Using that as a mask, the first amorphous silicon nitride layer 3-1 in the portion that will become the MIS type photodiode portion is removed by wet etching.

Next, as shown in FIG. 12, plasma CVD
Of the second insulating layer amorphous silicon nitride 3-2 using SiH ₄ gas and NH ₃ gas as raw materials by the method of 50 .ANG., And then using the H ₂ gas and SiH ₄ gas as raw materials, intrinsic a-Si: H (i layer) 4 to 6000 Å, followed by H ₂ gas, SiH ₄ gas, PH
₃ gas as a raw material a high concentration phosphorus-doped a-Si: H (n
⁺ Layer) 5 is deposited to 500 angstroms. These three layers are continuously deposited while maintaining a vacuum. Especially the second
Of the insulating layer amorphous silicon nitride 3-2 and the intrinsic a-Si: H (i layer) 4 are continuously formed, so that the MIS interface in the channel portion and the photodiode portion of the TFT is stably formed. Created.

Next, as shown in FIG. 13, the resist pattern is processed into a desired shape by photolithography,
Using this as a mask, the silicon nitride, the i layer, and the n ⁺ layer in the portion that will become the via hole are removed by CDE. Next, FIG.
As shown in FIG. 3, Al is deposited as the second metal layer 6 by the vacuum evaporation method at 10000 angstrom.

Next, as shown in FIG. 15, the resist pattern is processed into a desired shape by photolithography,
Using that as a mask, unnecessary portions of Al are removed by wet etching.

Next, as shown in FIG. 16, photolithography
Add a new resist pattern to the desired shape by
Then, using it as a mask, n⁺ Layer
With i-layer 500 angstrom of bar etching amount
To remove by RIE. The process shown in FIG. 15 and FIG.
Al and n which are unnecessary in the wiring matrix part
⁺ Both layers are removed. The same applies to the TFT section,
Source and drain electrodes are formed. MIS type photoda
In the ion part, Al is removed but n ⁺ Layer remains
Has been done, n⁺ Layer is ohmic contact to semiconductor layer
Will function as a transparent electrode.

Next, as shown in FIG. 17, the resist pattern is processed into a desired shape by photolithography,
Using this as a mask, the n ⁺ layer, the i layer, and the amorphous silicon nitride layer in unnecessary portions are separated by RI for the purpose of separating elements.
Remove with E. The window W is also formed in this step.

Next, plasma CV is used for the purpose of protecting the device.
Amorphous windowed silicon layer 10000 using method D
Angular deposition (not shown), unnecessary portions for external connection are removed, and an annealing process is performed to complete a photoelectric conversion device.

In the present invention, the semiconductor forming process that requires the most time is only the process shown in FIG. 10, and the time required for the entire manufacturing process is shortened as compared with the conventional method.

An embodiment of the second photoelectric conversion device of the present invention will be described below in detail with reference to the drawings. The same components as those in FIG. 1 are designated by the same reference numerals.

In FIG. 18, 10 'is a Schottky type photodiode, 11 is a TFT, and 12 is a wiring matrix. On the substrate 1, the lower electrode 2-1 of the photodiode, the lower electrode 2-3 of the wiring matrix, and T are formed by the first metal layer.
The FT gate electrode 2-2 is formed. An amorphous silicon nitride film 3, an intrinsic a-Si: H layer 4, an n-type a-S are formed on the lower electrode and the substrate 1.
The i: H layer 5 is formed in this order.

However, in the Schottky type photodiode portion, the amorphous silicon nitride layer is removed before the intrinsic a-Si: H layer (hereinafter, i layer) is formed, and the lower electrode 2-1 and the semiconductor are removed. The layers 4 are in direct contact and form Schottky connections. Further, after forming a via hole for connecting the first and second metal layers, a second hole is formed.
Forming a metal layer of. Second metal layer and n-type a-Si: H
The layers are selectively removed by appropriate patterning to form the wiring matrix, the source and drain electrodes in the TFT, the other semiconductor of the Schottky type photodiode portion, and the electrode junction. Although the second metal layer is removed in the Schottky type photodiode section, the n-type aS
The i: H layer is left as it is and is in ohmic contact with the semiconductor, and the incident light L is applied to the i layer through the n-type a-Si: H.

The feature of this embodiment is that the i layer is commonly used for the Schottky type photodiode and the TFT, and is formed in the same manufacturing process.

FIG. 19 shows a 1-bit equivalent circuit for operating the photoelectric conversion device having the configuration shown in FIG. The operation is briefly described as follows: Schottky photodiode S
Is applied with a reverse bias V _s through the switch SR, and the parasitic capacitance C _{s of the} photodiode is charged. Next, when the switch SR is turned off and the bias is removed, light causes the electric charge stored in the parasitic capacitance Cs to be discharged according to the discharging time. After a certain discharge time, switch S
T is connected to transfer the residual charge of the parasitic capacitance C _s to the reading capacitor C _x . Subsequently, the switch ST is closed and the switch SWout is opened to output the voltage appearing in the resistor R. In the figure, the switch SWout and the resistor R are external ICs. Others are built on the substrate.

20 to 20 show a lensless-type contact type one-dimensional photoelectric conversion device having the cross-sectional structure shown in FIG. 18 and comprising a plurality of single bit circuits shown in FIG. 19 using a matrix switch array. FIG. 22.

FIG. 20 shows a plan view of two pixels, and FIG. 21 is a sectional view taken along line BB in FIG.
22 shows a sectional view taken along the line CC of FIG.

20 to 22, 10 'is a photodiode, 11-a is a transfer TFT, 11-b is a charging TFT, 12-1 is a TFT gate wiring matrix, 1
Reference numeral 2-2 indicates a signal wiring matrix, and W indicates a lighting window. In addition, in order to avoid complexity in the drawing, the semiconductor layer and the insulating layer are not shown.

The lensless type referred to here is shown in FIG.
As shown in FIG. 3, light enters from the side opposite to the sensor surface of the substrate, illuminates the document surface P through the light-collecting window W of the substrate, and scatters the light without using a special optical system. ,
The light is received by the sensor.

FIG. 23 shows an equivalent circuit of the photoelectric conversion device. FIG. 24 shows a timing chart of the gate voltage pulse.

In FIG. 23, S _i1 , S _i2 , ..., S
_iN (hereinafter referred to as S _i ) is a photodiode showing the photoelectric conversion element 10 ′ in the i block. C _i1 , C _i2 , _...
.., C _iN (hereinafter, referred to as C _i ) represents the parasitic capacitance of the photodiode. ST _i1 , ST _i2 , ..., ST
_iN (hereinafter referred to as ST _i ) is a transfer switch for transferring the charge of the parasitic capacitance C _i to the load capacitors C _x1 , C _x2 , ..., C _xN , SR _i1 , SR _i2 ,. , SR
_iN (hereinafter referred to as SR _i ) is a charging switch for charging the parasitic capacitance C _i in advance. In this example, the switch 11 using the TFT includes a transfer switch ST _i and a charging switch SR _i . Si
, g _i1 , Sig _i2 , ..., Sig _iN are individual electrodes in the i block forming the signal line matrix.

These photodiode S _i , parasitic capacitance C _i , transfer switch ST _i and charging switch SR _i
Are arranged in a single row array and are divided into N × M blocks.

Transfer switches ST arranged in an array
_i and the gate electrode of the charging switch SR _i are connected to the wiring 12-1 formed in the matrix. The gate electrodes of the charging switches SR _i in the same block are commonly connected to G _i , and the gate electrodes of the transfer switches ST _i are the common line G of the gate electrodes of the charging switches SR _{i + 1 in} the next order. It is commonly connected to _{i + 1} .

[0076] In the timing shown in FIG. 24, gate drive lines _{(G 1, ···, G M} ) sequentially selects a pulse from the gate driver 14 to _{(V G1, V G2, ···} , V GM) is Is applied. When the gate drive line G ₁ is selected, the charging switches SR ₁₁ , SR ₁₂ , ..., SR _1N for the first block are turned on.
A reverse bias is applied to the photodiodes S ₁₁ , S ₁₂ , ..., S _1N through the bias V _s , and the parasitic capacitances C ₁₁ , C ₁₂ , ..., C _1N are charged.

Next, through the gate driving line G _1, charging switch SR _11, SR _12, · · ·, the SR _1N becomes OFF state, during the subsequent predetermined time T _s, the parasitic capacitance C _11,
The charges charged in C ₁₂ , ..., C _1N are discharged by light, and charges corresponding to the amount of light remain. When the gate drive line G ₂ is selected after a certain time T _s , the transfer switch ST ₁₁ ,
ST ₁₂ , ..., ST _1N are turned on, and parasitic capacitance C
_11, C _12, · · ·, charges remaining in the C _1N is the individual electrode Sig _11, Sig _12, · · ·, through Sig _1N, load capacitor C _x1, C _x2, · · ·, a C _XN Transferred.
The charges are sequentially sent to the signal processing unit 15, converted into a serial signal, and output. The same operation is performed for each block, and the information on the line is read.

The method for manufacturing the photoelectric conversion device of this embodiment will be described below. 25 to 34 are partial cross-sectional views schematically showing each manufacturing process of this embodiment.

First, as shown in FIG. 25, a clean glass substrate having a good flatness, which is the substrate 1, is formed by a vacuum evaporation method.
Cr (first metal layer) 2 is deposited to 1000 angstroms.

Next, as shown in FIG. 26, the resist pattern is processed into a desired shape by photolithography, and unnecessary Cr is removed by wet etching using the resist pattern as a mask to form the lower electrode 2- of the wiring matrix. 3,
Lower electrode 2-1 of Schottky type photodiode, TFT
Forming the gate electrode 2-2.

Next, as shown in FIG. 27, plasma CVD
By the method, the insulating layer amorphous silicon nitride 3 is deposited to 3000 angstrom using SiH ₄ gas and NH ₃ gas as raw materials. This is an interlayer insulating film in the wiring matrix,
The TFT functions as a gate insulating film.

Next, as shown in FIG. 28, the resist pattern is processed into a desired shape by photolithography,
Using this as a mask, the amorphous silicon nitride in the portion that will become the Schottky photodiode portion is removed by wet etching.

Next, as shown in FIG. 29, plasma CVD
By law, H ₂ gas, an intrinsic a-Si and SiH ₄ gas as a raw material: H (i layer) 4 and 6000 Å, followed by H ₂ gas, high concentration phosphorus-doped SiH ₄ gas, PH _{3 is} gas as a raw material a- Si: H (n ⁺ layer)
5 is deposited to 500 angstroms.

Next, as shown in FIG. 30, the resist pattern is processed into a desired shape by photolithography,
Using this as a mask, the silicon nitride, the i layer, and the n ⁺ layer in the portion that will become the via hole are removed by CDE. Next, FIG.
As shown in FIG. 3, Al is deposited as the second metal layer 6 by the vacuum evaporation method at 10000 angstrom.

Next, as shown in FIG. 32, the resist pattern is processed into a desired shape by photolithography,
Using that as a mask, unnecessary portions of Al are removed by wet etching.

Next, as shown in FIG. 33, a resist pattern is newly processed into a desired shape by photolithography, and using it as a mask, an n ⁺ layer at an unnecessary portion is formed together with an overetching amount of i layer of 500 Å. Remove by RIE. In the steps shown in FIGS. 32 and 33, unnecessary Al and n in the wiring matrix portion are used.
Both ⁺ layers are removed. The same applies to the TFT section,
Source and drain electrodes are formed. In the Schottky photodiode part, Al is removed, but the n ⁺ layer is left, and the n ⁺ layer functions as a transparent electrode that makes ohmic contact with the semiconductor layer.

Next, as shown in FIG. 34, the resist pattern is processed into a desired shape by photolithography,
Using this as a mask, the n ⁺ layer, the i layer, and the amorphous silicon nitride layer in unnecessary portions are separated by RI for the purpose of separating elements.
Remove with E. The window W is also formed in this step.

Next, plasma CV is used for the purpose of protecting the device.
Amorphous windowed silicon layer 10000 using method D
Angular deposition (not shown), unnecessary portions for external connection are removed, and an annealing process is performed to complete a photoelectric conversion device.

In the present invention, the semiconductor forming process that requires the most time is only the process shown in FIG. 27, and the time required for the entire manufacturing process is shortened as compared with the conventional method.

An example of the third photoelectric conversion device of the present invention will be described in detail below with reference to the drawings.

FIG. 35 is a view best showing the features of the present invention, and is a schematic view showing the structure of a partial sectional view of an embodiment of the photoelectric conversion device according to the present invention. The same components as those in FIG. 1 are designated by the same reference numerals.

In FIG. 35, 10 "is a Schottky type photodiode, 11 'is a TFT, and 12-1 and 12-2.
Indicates a wiring matrix. On the substrate 1, a photodiode lower electrode 2-1 and a wiring matrix lower electrode 2-3 are formed of the first metal layer. These lower electrodes,
On the substrate 1, the intrinsic a-Si: H layer 4, n
The type a-Si: H layer 5 is formed in this order. Further, the photodiode, the TFT, and the wiring matrix are made of ITO, and the upper electrode 6-1, the source electrode 6-2,
The drain electrode 6-3 and the individual electrode 6-4 are formed. An amorphous silicon nitride layer 7 is formed on the ITO and the semiconductor layer. In the photodiode, the passivation layer 7-2 and in the wiring matrix, the interlayer insulating layer 7-.
1, 7-4, the TFT functions as a gate insulating layer 7-3.

Next, the upper electrodes 9-1 and 9-3 of the wiring matrix and the gate electrode 9-2 of the TFT are formed using the second metal layer through the insulating film.

The feature of this embodiment is that at least two layers, i layer and n layer, are Schottky type photodiode and TFT.
The wiring matrix and the wiring matrix have a common layer structure and are formed in the same manufacturing process.

In the wiring matrix, the first metal layer and the second metal layer
The case of forming a two-layer wiring with the metal layer of
It may be possible to form a two-layer wiring with the metal layer of the above and the transparent electrode ITO. Considering wiring resistance, process easiness, etc.,
You can choose the combination as appropriate. Further, in the former case, the semiconductor layer is partially left between the upper and lower wirings, but the upper and lower wirings only need to maintain the insulating property, and the existence of the semiconductor layers 3 and 4 affects Don't give.

The TFT is made to perform n-channel operation, which is advantageous in the characteristics of amorphous silicon.

FIG. 36 shows a 1-bit equivalent circuit for operating the photoelectric conversion device having the configuration shown in FIG. When the operation is briefly shown, the Schottky photodiode S is
A reverse bias V _s is applied through the switch SR, and the parasitic capacitance C _{s of the} photodiode is charged. Next, when the switch SR is turned off and the bias is removed,
The light causes the electric charge stored in the parasitic capacitance Cs to be discharged according to the discharge time. After a certain discharge time, connect the switch ST, and transfers to the capacitor C _x for reading out the residual charges of the parasitic capacitance C _s. Then, close the switch ST,
By opening the switch SWout, the voltage appearing at the resistor R is output. In the figure, the switch SWout and the resistor R are external ICs. Others are built on the substrate.

37A to 37C show a lensless contact type one-dimensional photoelectric conversion device having the sectional structure shown in FIG. 35 and having the single bit circuit shown in FIG. 36 formed by using a plurality of matrix switch arrays. FIG. 39.

FIG. 37 shows a plan view of two pixels, and FIG. 38 is a sectional view taken along line BB in FIG.
FIG. 39 is a sectional view taken along line CC of FIG.

37 to 39, 10 ″ is a photodiode, 11-a is a transfer TFT, 11-b is a charging TFT, 12-1 is a TFT gate wiring matrix, 1
Reference numeral 2-2 indicates a signal wiring matrix, and W indicates a lighting window. In addition, in order to avoid complexity in the drawing, the semiconductor layer and the insulating layer are not shown.

The lensless type referred to here is shown in FIG.
As shown in FIG. 3, light enters from the side opposite to the sensor surface of the substrate, illuminates the document surface P through the light-collecting window W of the substrate, and scatters the light without using a special optical system. ,
The light is received by the sensor.

FIG. 40 shows an equivalent circuit of the photoelectric conversion device. FIG. 41 shows a timing chart of the gate voltage pulse.

In FIG. 40, S _i1 , S _i2 , ..., S
_iN (hereinafter referred to as S _i ) is a photodiode showing the photoelectric conversion element 10 ″ in the i block. C _i1 , C _i2 , ...
.., C _iN (hereinafter, referred to as C _i ) represents the parasitic capacitance of the photodiode. ST _i1 , ST _i2 , ..., ST
_iN (hereinafter referred to as ST _i ) is a transfer switch for transferring the charge of the parasitic capacitance C _i to the load capacitors C _x1 , C _x2 , ..., C _xN , SR _i1 , SR _i2 ,. , SR
_iN (hereinafter referred to as SR _i ) is a charging switch for charging the parasitic capacitance C _i in advance. In this example, the switch 11 using the TFT includes a transfer switch ST _i and a charging switch SR _i . Si
, g _i1 , Sig _i2 , ..., Sig _iN are individual electrodes in the i block forming the signal line matrix.

These photodiode S _i , parasitic capacitance C _i , transfer switch ST _i and charging switch SR _i
Are arranged in a single row array and are divided into N × M blocks.

Transfer switches ST arranged in an array
_i and the gate electrode of the charging switch SR _i are connected to the wiring 12-1 formed in the matrix. The gate electrodes of the charging switches SR _i in the same block are commonly connected to G _i , and the gate electrodes of the transfer switches ST _i are the common line G of the gate electrodes of the charging switches SR _{i + 1 in} the next order. It is commonly connected to _{i + 1} .

[0106] In the timing shown in FIG. 41, gate drive lines _{(G 1, ···, G M} ) sequentially selects a pulse from the gate driver 14 to _{(V G1, V G2, ···} , V GM) is Is applied. When the gate drive line G ₁ is selected, the charging switches SR ₁₁ , SR ₁₂ , ..., SR _1N for the first block are turned on.
A reverse bias is applied to the photodiodes S ₁₁ , S ₁₂ , ..., S _1N through the bias V _s , and the parasitic capacitances C ₁₁ , C ₁₂ , ..., C _1N are charged.

Next, the gate drive line G₁For charging through
Switch SR₁₁, SR₁₂, ..., SR_1NIs OFF
Then, for a certain period of time T_sBetween the parasitic capacitance C₁₁,
C₁₂, ..., C_1NThe electric charge charged in the
However, a charge corresponding to the amount of light remains. Fixed time T_sAfter
Drive line G₂Is selected, the transfer switch ST₁₁,
ST₁₂・ ・ ・, ST_1NTurns on and the parasitic capacitance C
₁₁, C₁₂, ..., C _1NThe electric charge remaining in the
Pole sig₁₁, Sig₁₂, ..., Sig_1NThrough negative
Load capacitor C_x1, C_x2, ..., C_XNTransferred to.
This charge is sequentially sent to the signal processing unit 15, and the serial signal
Is converted to and output. The same operation is performed for each block.
The information on the line is read.

The method of manufacturing the photoelectric conversion device of this embodiment will be described below. 42 to 51 are partial cross-sectional views schematically showing each manufacturing process of this embodiment.

First, as shown in FIG. 42, a cleaned glass substrate having good flatness, which is the substrate 1, is formed by a vacuum deposition method.
Cr (first metal layer) 2 is deposited to 1000 angstroms.

Next, as shown in FIG. 43, the resist pattern is processed into a desired shape by photolithography, and unnecessary Cr is removed by wet etching using the resist pattern as a mask to form the lower electrode 2- of the wiring matrix. 3,
The lower electrode 2-1 of the Schottky type photodiode is formed.

Next, as shown in FIG. 44, plasma CVD
By law, the SiH ₄ gas as a raw material, an intrinsic a-Si: H4 to 5000 Angstroms deposited. Subsequently, a high-concentration phosphorus-doped a-Si: H layer 5 of 1000 angstrom is deposited using SiH ₄ gas and PH ₃ gas as raw materials.

Next, as shown in FIG. 45, 100% ITO (Indium Tin Oxide) was deposited by vacuum deposition.
Deposit 0 Å.

Next, as shown in FIG. 46, a resist pattern is formed in a desired shape by photolithography. Using this as a mask, unnecessary ITO is removed by wet etching using FeCl ₃ / HCl aqueous solution to form the upper electrode 6-1 of the Schottky photodiode, the source electrode 6-2 of the TFT, and the drain electrode 6-3. .

Next, as shown in FIG. 47, the pattern forming resist of ITO is left as it is, and the unnecessary n layer is removed using this as a mask. As a result, the channel portion of the TFT is formed.

Next, as shown in FIG. 48, plasma CVD
By the method, the insulating layer amorphous silicon nitride is deposited using SiH ₄ gas and NH ₃ gas as raw materials. This is the interlayer insulating layer 7-1 in the wiring matrix, the passivation film 7-2 in the photodiode, and the gate insulating film 7 in the TFT.
It is used as -3.

Next, as shown in FIG. 49, a resist pattern is processed into a desired shape by photolithography,
By using CF ₄ gas as a reaction gas, the three layers of silicon nitride and in are etched by dry etching to form contact holes 13 of the wiring matrix, and patterning for element isolation is performed.

Next, as shown in FIG. 50, as a second metal layer, Al is deposited to 10000 angstrom by the vacuum evaporation method.

Next, as shown in FIG. 51, a resist pattern is formed in a desired shape by photolithography. Using this as a mask, HNO ₃ / H ₃ PO ₄ / CH
Unnecessary Al is removed by wet etching using a ₃ COOH aqueous solution, and the upper electrodes 9-1, 9- of the wiring matrix are removed.
3. Form the gate electrode 9-2 of the TFT.

Finally, a protective layer (not shown) is formed using an organic resin, and a photoelectric conversion device is manufactured.

In the present invention, the semiconductor forming process that takes the longest time is only the process shown in FIG. 44, and the time required for the entire manufacturing process is shortened as compared with the prior art. Further, since the patterning is performed only by the step shown in FIG. 49, the semiconductor raw material gas is not wasted and the utilization efficiency is higher than that in the conventional semiconductor formation and patterning which are separately performed twice. .

[0121]

As described above in detail, according to the first photoelectric conversion device and the method of manufacturing the same of the present invention, the semiconductor layers of the MIS type photodiode and the switch element are deposited in the same step. By using a material, the manufacturing process can be simplified, the yield of the manufacturing process can be improved, and the photoelectric conversion device can be provided at a low cost and at a low cost in combination with the efficient use of the material.

According to the second photoelectric conversion device and the method of manufacturing the same of the present invention, the semiconductor layers of the Schottky type photodiode and the switch element are made of the same semiconductor material deposited in the same step. It is possible to provide a low-cost, low-cost photoelectric conversion device by simplifying the manufacturing process, improving the yield of the manufacturing process, and efficiently using the material.

According to the third photoelectric conversion device and the method of manufacturing the same of the present invention, the semiconductor layers of the Schottky photodiode, the switch element and the wiring matrix are made of the same semiconductor material deposited in the same step. The manufacturing process can be simplified, the yield of the manufacturing process can be improved, and the photoelectric conversion device can be provided at low cost at low cost in combination with efficient use of materials.

[Brief description of drawings]

FIG. 1 is a diagram showing a partial cross-sectional structure of an embodiment of a first photoelectric conversion device of the present invention.

FIG. 2 is a single-bit equivalent circuit diagram showing an operation of the photoelectric conversion device shown in FIG.

FIG. 3 is a plan view of two pixels of a long contact photoelectric conversion device in which a plurality of photoelectric conversion elements having the cross-sectional structure shown in FIG. 1 are arranged in a single-row array.

FIG. 4 is a BB cross-sectional view of the photoelectric conversion device shown in FIG.

5 is a cross-sectional view taken along line CC of the photoelectric conversion device shown in FIG.

FIG. 6 is an equivalent circuit diagram of the photoelectric conversion device shown in FIGS.

FIG. 7 is a timing chart of a gate voltage pulse.

FIG. 8 is a manufacturing process diagram of an example of a first photoelectric conversion device of the present invention.

FIG. 9 is a manufacturing process diagram of an example of the first photoelectric conversion device of the present invention.

FIG. 10 is a manufacturing process diagram of an embodiment of the first photoelectric conversion device of the present invention.

FIG. 11 is a manufacturing process diagram of an embodiment of the first photoelectric conversion device of the present invention.

FIG. 12 is a manufacturing process diagram of an embodiment of the first photoelectric conversion device of the present invention.

FIG. 13 is a manufacturing process diagram of an embodiment of the first photoelectric conversion device of the present invention.

FIG. 14 is a manufacturing process diagram of an embodiment of the first photoelectric conversion device of the present invention.

FIG. 15 is a manufacturing process diagram of an example of the first photoelectric conversion device of the present invention.

FIG. 16 is a manufacturing process diagram of an embodiment of the first photoelectric conversion device of the present invention.

FIG. 17 is a manufacturing process diagram of an embodiment of the first photoelectric conversion device of the present invention.

FIG. 18 is a diagram showing a partial cross-sectional configuration of an embodiment of a second photoelectric conversion device of the present invention.

19 is a single-bit equivalent circuit diagram showing an operation of the photoelectric conversion device shown in FIG.

20 is a plan view of two pixels of a long contact photoelectric conversion device in which a plurality of photoelectric conversion elements having the cross-sectional structure shown in FIG. 18 are arranged in a single line array.

21 is a cross-sectional view taken along line BB of the photoelectric conversion device shown in FIG.

22 is a cross-sectional view taken along line CC of the photoelectric conversion device shown in FIG.

FIG. 23 is an equivalent circuit diagram of the photoelectric conversion device shown in FIGS. 20 to 22.

FIG. 24 is a timing chart of a gate voltage pulse.

FIG. 25 is a manufacturing process diagram of an example of a second photoelectric conversion device of the present invention.

FIG. 26 is a manufacturing process diagram of an example of a second photoelectric conversion device of the present invention.

FIG. 27 is a manufacturing process diagram of an example of a second photoelectric conversion device of the present invention.

FIG. 28 is a manufacturing process diagram of an example of a second photoelectric conversion device of the present invention.

FIG. 29 is a manufacturing process diagram of an example of a second photoelectric conversion device of the present invention.

FIG. 30 is a manufacturing process diagram of an example of a second photoelectric conversion device of the present invention.

FIG. 31 is a manufacturing process diagram of an example of a second photoelectric conversion device of the present invention.

FIG. 32 is a manufacturing process diagram of an example of a second photoelectric conversion device of the present invention.

FIG. 33 is a manufacturing process diagram of an example of a second photoelectric conversion device of the present invention.

FIG. 34 is a manufacturing process diagram of an example of a second photoelectric conversion device of the present invention.

FIG. 35 is a diagram showing a partial cross-sectional configuration of an embodiment of the third photoelectric conversion device of the present invention.

FIG. 36 is a single-bit equivalent circuit diagram showing an operation of the photoelectric conversion device shown in FIG. 35.

FIG. 37 is a plan view of two pixels of a long contact photoelectric conversion device in which a plurality of photoelectric conversion elements having the cross-sectional structure shown in FIG. 35 are arranged in a single-row array.

38 is a cross-sectional view taken along line BB of the photoelectric conversion device shown in FIG.

39 is a cross-sectional view taken along line CC of the photoelectric conversion device shown in FIG. 37.

FIG. 40 is an equivalent circuit diagram of the photoelectric conversion device shown in FIGS. 37 to 39.

FIG. 41 is a timing chart of a gate voltage pulse.

FIG. 42 is a manufacturing process diagram of an example of the third photoelectric conversion device of the present invention.

FIG. 43 is a manufacturing process diagram of an example of the third photoelectric conversion device of the present invention.

FIG. 44 is a manufacturing process diagram of an example of the third photoelectric conversion device of the present invention.

FIG. 45 is a manufacturing process diagram of an example of the third photoelectric conversion device of the present invention.

FIG. 46 is a manufacturing process diagram of an example of the third photoelectric conversion device of the present invention.

FIG. 47 is a manufacturing process diagram of an example of the third photoelectric conversion device of the present invention.

FIG. 48 is a manufacturing process diagram of an example of the third photoelectric conversion device of the present invention.

FIG. 49 is a manufacturing process diagram of an example of the third photoelectric conversion device of the present invention.

FIG. 50 is a manufacturing process diagram of an example of the third photoelectric conversion device of the present invention.

FIG. 51 is a manufacturing process diagram of an example of the third photoelectric conversion device of the present invention.

FIG. 52 is a diagram showing a partial cross-sectional structure of a conventional photoelectric conversion device.

FIG. 53 shows a single-bit equivalent circuit of a conventional photoelectric conversion device.

FIG. 54 is a diagram showing a manufacturing process of a conventional photoelectric conversion device.

FIG. 55 is a diagram showing a process of manufacturing a conventional photoelectric conversion device.

FIG. 56 is a diagram showing manufacturing steps of a conventional photoelectric conversion device.

FIG. 57 is a diagram showing a process of manufacturing a conventional photoelectric conversion device.

FIG. 58 is a diagram showing manufacturing steps of a conventional photoelectric conversion device.

FIG. 59 is a diagram showing a process of manufacturing a conventional photoelectric conversion device.

FIG. 60 is a diagram showing a manufacturing process of the conventional photoelectric conversion device.

FIG. 61 is a diagram showing a process of manufacturing a conventional photoelectric conversion device.

FIG. 62 is a diagram showing a process of manufacturing a conventional photoelectric conversion device.

FIG. 63 is a diagram showing a process of manufacturing a conventional photoelectric conversion device.

FIG. 64 is a diagram showing manufacturing steps of a conventional photoelectric conversion device.

[Explanation of symbols]

1 Substrate 2 First Metal Layer 2-1 Photodiode Lower Electrode 2-2 TFT Gate Electrode 2-3 Wiring Matrix Lower Electrode 3 Amorphous Silicon Nitride Film 3-1 First Amorphous Silicon Nitride Film 3-2 Second Amorphous silicon nitride film 4 Intrinsic a-Si: H layer 5 n-type a-Si: H layer 5-1 Photodiode upper electrode 6 Second metal layer 6-1 Photodiode upper electrode (ITO) 6-2 Source Electrode 6-3 Drain electrode 6-4 Wiring matrix individual electrode 7 Insulating layer 7-1, 7-4 Wiring matrix interlayer insulating layer 7-2 Schottky photodiode passivation layer 7-3 Gate insulating film 8-1 in Trinsic a-Si: H layer 8-2 n-type a-Si: H layer 9 Second metal layer 9-1, 9-3, 9-7 Wiring matrix Electrode 9-2 Gate electrode 9-4 Upper electrode 9-5 Drain electrode 9-6 Source electrode 10 MIS type photodiode 10 'Schottky type photodiode 10 "Schottky type photodiode 11, 11' TFT 11-a Transfer TFT 11 -B Charging TFT 12 Wiring matrix 12-1 Gate wiring matrix 12-2 Signal wiring matrix 13 Contact hole 14 Gate drive unit 15 Signal drive unit P Original L Incoming light W Window

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H04N 1/028 Z 8721-5C 8422-4M H01L 31/10 E (72) Inventor Masano Yamanobe Tokyo 3-30-2 Shimomaruko, Ota-ku Canon Inc.

Claims (17)

[Claims] 1. A photoelectric conversion device comprising at least a MIS type photodiode and a switch element on the same substrate, wherein the same semiconductor is formed by depositing semiconductor layers of the MIS type photodiode and the switch element in the same step. A photoelectric conversion device comprising a material. 2. The MIS of the MIS type photodiode
The photoelectric conversion device according to claim 1, wherein the electrode forming the junction is made of the same material as the gate electrode of the switch element. 3. The structure according to claim 1, wherein the source and drain electrodes of the switch element are made of a common metal material, and a doping layer is provided between the metal material and the semiconductor layer. Photoelectric conversion device. 4. The photoelectric conversion device according to claim 1, wherein the semiconductor layer is a thin film amorphous semiconductor. 5. The photoelectric conversion device according to claim 3, wherein the doping layer forms an ohmic contact with the semiconductor layer. 6. The light to be detected is received by the semiconductor layer through the doping layer.
The photoelectric conversion device described. 7. A step of forming at least an electrode forming a MIS junction of a MIS type photodiode and a metal layer to be a gate electrode of a switch element on a substrate; and forming a first insulating layer on the metal layer, A step of forming a second insulating layer after removing the first insulating layer on the electrode forming the MIS junction of the MIS photodiode, and a step of forming a semiconductor layer on the second insulating layer; A method for manufacturing a photoelectric conversion device comprising: 8. A photoelectric conversion device comprising at least a Schottky type photodiode and a switch element on the same substrate, wherein the same semiconductor in which the semiconductor layers of the Schottky type photodiode and the switch element are deposited in the same step. A photoelectric conversion device comprising a material. 9. The photoelectric conversion device according to claim 8, wherein the electrode forming the Schottky junction of the Schottky type photodiode is made of the same material as the gate electrode of the switch element. 10. The structure according to claim 8, wherein the source and drain electrodes of the switch element are made of a common metal material, and a doping layer is provided between the metal material and the semiconductor layer. Photoelectric conversion device. 11. The photoelectric conversion device according to claim 8, wherein the semiconductor layer is a thin film amorphous semiconductor. 12. The doping layer is in ohmic contact with the semiconductor layer.
The photoelectric conversion device described. 13. The photoelectric conversion device according to claim 12, wherein light to be detected is received by the semiconductor layer through the doping layer. 14. A step of forming at least an electrode forming a Schottky junction of a Schottky type photodiode and a metal layer to be a gate electrode of a switch element on a substrate, and forming an insulating layer on the metal layer to form the Schottky type photodiode. A method of manufacturing a photoelectric conversion device, comprising the steps of: removing an insulating layer on an electrode forming a Schottky junction of a diode, and then forming a semiconductor layer on the insulating layer. 15. A photoelectric conversion device comprising at least a Schottky photodiode, a switch element, and a wiring matrix on the same substrate, wherein the Schottky photodiode, the switch element, and the wiring matrix have the same semiconductor layer. A photoelectric conversion device comprising the same semiconductor material deposited in a process. 16. The semiconductor layer is composed of two layers, an intrinsic hydrogenated amorphous silicon layer and an n-type hydrogenated amorphous silicon layer.
The photoelectric conversion device described. 17. A semiconductor of a Schottky photodiode, a switch element, and a wiring matrix by patterning after forming an intrinsic hydrogenated amorphous silicon layer and an n-type hydrogenated amorphous silicon layer on a substrate in this order. A method for manufacturing a photoelectric conversion device, which comprises simultaneously forming layers.