JPH06187800A - Analyzing device for defective mode of storage element - Google Patents

Abstract

(57) [Summary] [Objective] The defective bit map in which the operation test result of the storage element is stored in the same array as the bit layout of the storage element under test is regarded as a two-dimensional image, and the two-dimensional image of the storage element under test is used. Analyze the failure mode. The analysis unit 22 analyzes a defective mode of a storage element under test from a two-dimensional image based on a defective bit map of the storage element under test, and the analysis unit 22 follows a bit data map and a defective bit array in a small area. It is composed of an operation unit 23 that performs a sum of products operation with a line failure data template for all areas of the defect bitmap, and a determination unit 24 that determines a failure mode based on the operation result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage element which is connected to a test device for testing the operation of a storage element such as a semiconductor and which analyzes a failure mode of a storage element under test based on a test result output from the test device. The present invention relates to a failure mode analyzer.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a conventional failure mode analyzer for a memory element. In the figure, 1 is a memory element under test and 2 is a tester (testing apparatus) for performing an operation test of the memory element under test 1. ) 3 is a failure mode analyzer.
Here, 4 is an input signal input from the tester 2 to the memory device under test 1, 4a is a bit address signal of the input signal 4, and 5 is bit output data of the memory device under test 1 corresponding to the bit address signal 4a. , 6 are test results (defect information) of the bit output data 5 determined by the tester 2. The failure mode analysis device 3 is a device for analyzing the failure mode of the storage device under test 1 based on the test result 6, and takes in the test result 6 and the bit address signal 4a to obtain the failure bit map of the storage device under test 1. A defective data collection unit 11 to be created, and a defective bitmap memory 12 for storing the defective bitmap as an array having the same layout as the bit layout of the memory device under test 1, for example, defective “1” and defective “0”. And a display unit 13 for displaying the information stored in the defective bitmap memory 12 as a two-dimensional image.

Next, the operation will be described. When the input signal 4 is input from the tester 2 to the memory device under test 1, the bit output data 5 corresponding to the designated bit address signal 4a is sent to the tester 2 for determination. The determined test result 6 and the bit address signal 4a are output to the tester 2
The defective bit map sent to the defective data collection unit 11 of the defective mode analysis apparatus 3 and output from the defective data collection unit 11 has the same memory information as the bit layout of the memory device under test 1, for example, " 1 ”and good are stored as“ 0 ”in the defective bitmap memory 12.
Further, the display unit 13 displays the information stored in the defective bitmap memory 12 as a two-dimensional image.

FIG. 9 shows an example of the defective bitmap displayed by the display unit 13. The defective bitmap 1 is shown in FIG.
In FIG. 6, there are four types of defects: a column line defect 16a continuous in the vertical direction, a row line defect 16b continuous in the horizontal direction, a bit defect 16c independently existing in 1 bit, and a block defect 16d continuous in the row and column directions. The mode is displayed.
Conventionally, from this displayed defective bitmap 16,
A person visually judges the failure mode of the storage element under test 1.

[0005]

Since the conventional failure mode analysis apparatus is constructed as described above, it is necessary for a person to judge the failure mode, which requires time and judgment ability. On a mass production test line, there is a problem that it is impossible to specify a failure mode for all products. Further, since the judgment is performed visually, a considerable degree of skill is required to make a correct judgment in a short time, and there is a problem that a judgment error cannot be eliminated.

The present invention has been made in order to solve the above problems, and a storage element capable of automatically analyzing a failure mode of a storage element under test based on a result of an operation test of the storage element. It is an object of the present invention to provide a failure mode analyzer of the above.

[0007]

According to a first aspect of the present invention, there is provided a failure mode analysis apparatus for a memory element, wherein the failure mode analyzer for the memory element is one of the memory elements to be tested which is output from a test apparatus for performing an operation test of the memory element.
A defect data collection unit that takes in address information and defect information for each bit and creates a defect bitmap of the test memory element, and a defect that stores the defect bitmap as memory information in an array equal to the bit layout of the memory element under test. The bit map memory and the memory information are fetched, the defective bit map of the tested storage element is captured as a two-dimensional image based on the memory information, and the defective mode of the tested storage element is determined from the two-dimensional image using an image analysis method. And an analyzing unit for analyzing.

The analysis unit of the failure mode analyzer for a storage element according to the second aspect of the present invention analyzes a bit data map in a small area which is a part of the failure bitmap and a failure mode to be detected in this small area. A calculation unit that performs a sum-of-products operation with a data template according to the defective bit array and performs a sum-of-products operation on the entire defective bit map area And a section.

The analysis unit of the failure mode analyzer for a storage element according to the third aspect of the present invention measures the number of defective bits for each row and the number of defective bits for each column of a two-dimensional array of defective bitmaps, A calculation unit that obtains a horizontal projection from the measurement value of each row and a vertical projection from the measurement value of each column, and a determination unit that determines the failure mode of the memory element under test by combining these two projection data It is a thing.

[0010]

According to another aspect of the present invention, there is provided a defective mode analyzing apparatus for a memory device, wherein the defective data collecting unit creates a defective bit map of the tested memory device from address information and defect information for each bit of the tested memory device. Then, the defective bitmap memory stores the created defective bitmap information as memory information in an array equal to the bit layout of the storage element under test, and the analyzing unit captures the defective bitmap as a two-dimensional image based on the memory information. The failure mode of the storage element under test is analyzed from the two-dimensional image. The failure modes are four, namely, a column line failure or a row line failure in which each defective bit is continuous in the vertical or horizontal direction, a bit failure in which each bit is independent, and a block failure in which rows and columns are continuous. Represented as either species or a combination of these. As a result, it becomes possible to automatically and quickly identify the defective mode of the storage element under test.

In the analyzing unit of the failure mode analyzer for a storage element according to the second aspect of the present invention, the calculating unit has a bit data map in a partial small area of the defective bit map and a failure mode to be detected in this small area. The product-sum operation with the data template according to the defective bit array of is performed on the entire area of the defective bit map, and the determination unit extracts the defective mode bit array from the result of the product-sum operation to determine the defective mode of the memory device under test. .

Further, in the analyzing unit of the failure mode analyzer of the storage element according to the invention of claim 3, the calculating unit measures the number of defective bits for each row and each column of the defective bitmap, and measures for each row. The horizontal projection is obtained from the value and the vertical projection is obtained from the measured value of each column, and the determination unit extracts the feature of the mode of the defective bit from these projection data, and determines the defective mode of the memory device under test.

[0013]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 21 is a failure mode analyzer. This failure mode analysis apparatus 21 is an improvement of the failure mode analysis apparatus 3 of the conventional example. In FIG. 1, the same elements as those shown in FIG. 8 are designated by the same reference numerals, and the same elements will be described. The description is omitted. The failure mode analysis device 21 includes a failure data collection unit 11, a failure bitmap memory 12, a display unit 13, and an analysis unit 22.

The analysis unit 22 performs a sum of products operation of a bit data map in a partial small area of the defective bitmap and a data template according to the defective bit array of the defective mode desired to be detected in this small area, in the entire defective bitmap area. And a determining section 24 for determining the failure mode of the storage device under test 1 based on the result of the product-sum calculation.

Next, the operation will be described. When the input signal 4 is input from the tester 2 to the memory device under test 1, the bit output data 5 corresponding to the designated bit address signal 4a is sent to the tester 2 for determination. The determined test result 6 and the bit address signal 4a are output to the tester 2
Further, the defective bit map sent to the defective data collecting unit 11 of the defective mode analyzing apparatus 21 and output from the defective data collecting unit 11 has the same memory information as the bit layout of the memory device under test 1, for example, "1",
Good is stored in the bad bit map memory 12 as “0”. Further, the display unit 13 has a defective bitmap memory 12
The information stored in is displayed as a two-dimensional image.

FIG. 2 is a display example of a defective bit map displayed on the display unit 13. In the defective bit map 25, column line defects 16a continuous in the vertical direction, row line defects 16b continuous in the horizontal direction, and 1 bit. The failure modes of the independently-existing bit failure 16c and the block failure 16d continuous in the column direction are displayed. Reference numeral 26 is a small area to be processed on the defective bitmap.

In the calculation unit 23, the defective bit map 25 is made into a two-dimensional binary image as shown in FIG. 2, for example, a two-dimensional image in which the portion corresponding to the defective bit is "1" and the good is "0". From this image, as shown in FIG. 3, the sum of products calculation of the bit data map 26a in the range of the small area 26 and the line defect data template (data template) 27 of the small area of the bit array of the defect mode to be detected is calculated. Based on (1), the entire image area (1 <n, m <102
Perform 4).

[0018]

[Equation 1]

Here, the equation (1) is a calculation equation for obtaining the line defect matching degree L (n, m) of the bit of the bit address (n, m) using the line defect data template 27.

In this way, the defective mode bit array is extracted from the two-dimensional image. That is, it is converted into an image in which the calculated value L (n, m) of the defective line portion is increased. Next, the determination unit 24 compares the calculated value L (n, m) with the reference value to identify the failure mode.

The line defect data template 27
Are prepared for each failure mode, and the sum of products calculation is performed. 4 and 5 show these line defect data templates. FIG. 4 is a bit defect data template, and FIG. 5 is a block defect data template.

As described above, according to the failure mode analysis device 21, the partial small area 26 of the failure bit map.
The sum of products of the bit data map 26a in FIG.
The failure mode of the memory element under test 1 can be specified automatically and in a short time from the results obtained for all areas. Further, it is possible to specify the defective mode for all products in the mass production test line, and it is possible to eliminate the determination error.

Example 2. FIG. 6 is a diagram showing a failure mode analyzer 31 for a memory element according to another embodiment of the present invention. This failure mode analysis device 31 replaces the analysis unit 22 of the failure mode analysis device 21 of the above embodiment with an analysis unit 32 described below.

This analysis unit 32 uses the defective bit map 2
An arithmetic unit 33 that measures the number of defective bits for each row and each column of the dimensional array, obtains the horizontal projection from the measurement value of each row, and obtains the vertical projection from the measurement value of each column, and the projection data thereof. The determination unit 34 for determining the failure mode of the memory device under test 1 based on the above.

Next, the operation will be described. When the input signal 4 is input from the tester 2 to the memory device under test 1, it is sent to the bit output data 5 tester 2 corresponding to the designated bit address signal 4a for determination. The determined test result 6 and the bit address signal 4a are sent from the tester 2 to the defective data collecting unit 11 of the defective mode analyzer 31, and the defective bit map output from the defective data collecting unit 11 is used as the storage element under test. The memory information having the same arrangement as the bit layout of 1 is stored in the defective bitmap memory 12 as, for example, "1" for defective and "0" for good.
Further, the display unit 13 displays the information stored in the defective bitmap memory 12 as a two-dimensional image.

The arithmetic unit 33 measures the number of defective bits for each row and each column of the two-dimensional array of the defective bit map 35 as shown in FIG. 7, and obtains the horizontal projection 36 and the vertical projection 37. The determination unit 34 extracts the feature of the mode of the defective bit by combining the horizontal projection 36 and the vertical projection 37, and determines the defective mode of the storage element under test 1.

Also in this failure mode analysis device 31,
Similar to the failure mode analyzer 21 of the above-described embodiment, the failure mode of the storage element under test 1 can be automatically specified in a short time. Furthermore, it is possible to identify the defective mode for all products in the mass production test line and eliminate the determination error.

[0028]

As described above, according to the first aspect of the present invention, the analyzing unit captures the defective bitmap of the memory element under test as a two-dimensional image based on the fetched memory information, and the defective bit map is detected from the two-dimensional image. Since the failure mode of the test memory element is analyzed, the failure mode of the memory element under test can be automatically specified in a short time. Further, it is possible to identify the defective mode for all products in the mass production test line, and it is possible to eliminate an artificial judgment error.

According to the second aspect of the present invention, the analysis unit causes the product of the bit data map in the partial small area of the defective bitmap and the line defect data template according to the defective bit array in the small area. Since the operation unit that performs the sum operation on the entire defective bitmap area and the determination unit that determines the failure mode of the memory element under test based on the result of the product sum operation, the failure mode of the memory element under test is automatically determined. Moreover, it can be specified in a short time. Moreover,
Since the judgment is performed based on the result of the product-sum calculation, there is an effect that an artificial judgment error is eliminated.

According to the third aspect of the invention, the analyzing unit measures the number of defective bits for each row and each column of the two-dimensional array of defective bitmaps, and laterally projects from the measured value for each row. And a determination unit that determines the failure mode of the memory device under test based on these projection data and the calculation unit that determines the vertical projection from the measured value for each column. It can be specified automatically and in a short time. Moreover, since the horizontal projection and the vertical projection are combined to make the judgment, there is an effect that an artificial judgment error is eliminated.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a failure mode analysis device for a storage element according to an embodiment of the present invention.

FIG. 2 is a diagram showing a display example of a defective bitmap according to an embodiment of the present invention.

FIG. 3 is a diagram showing a bit data map of a small area and a line defect data template according to an embodiment of the present invention.

FIG. 4 is a diagram showing a bit defect data template used in an embodiment of the present invention.

FIG. 5 is a diagram showing a block defect data template used in an embodiment of the present invention.

FIG. 6 is a configuration diagram of a failure mode analyzer for a storage element according to another embodiment of the present invention.

FIG. 7 is a diagram showing projection data output from a computing unit of another embodiment of the present invention.

FIG. 8 is a block diagram of a conventional failure mode analyzer for a storage element.

FIG. 9 is a diagram showing a display example of a conventional defective bitmap.

[Explanation of symbols]

1 Test Storage Element 2 Tester (Test Device) 11 Fault Data Collection Section 12 Fault Bitmap Memory 22 Analysis Section 23 Calculation Section 24 Judgment Section 25 Fault Bitmap 26 Small Area 27 Line Fault Data Template (Data Template) 32 Analysis Section 33 Operation Unit 34 Judgment Unit 35 Bad Bitmap (Bit Data Map) 36 Horizontal Projection 37 Vertical Projection

Claims (3)

[Claims] 1. A device which is connected to a test device for performing an operation test of a memory element and analyzes a failure mode of the memory element, wherein the bit information of each bit of the memory element under test output from the test device. And take in the defect information,
A defective data collection unit that creates a defective bitmap of the storage device under test, a defective bitmap memory that stores the defective bitmap as memory information in an array that is equal to the bit layout of the storage device under test, and fetches the memory information. A defective mode analysis device for a storage element, comprising: a defective bit map of a storage element to be tested as a two-dimensional image based on the memory information, and an analysis unit that analyzes a defective mode of the storage element to be tested from the two-dimensional image. 2. The analyzing unit performs a product-sum operation of a bit data map in a partial small area of the defective bit map and a data template according to a defective bit array of a defective mode to be detected in the small area, the defective bit. 2. The failure mode analysis device for a storage element according to claim 1, further comprising: an operation section for performing the entire map area and a determination section for determining a failure mode of the storage element under test based on a result of the sum of products operation. . 3. The analyzing unit measures the number of defective bits for each row and each column of the two-dimensional array of defective bitmaps, obtains a horizontal projection from the measured value for each row, and for each column. 2. The failure mode analyzer for a storage element according to claim 1, further comprising: a calculation section for obtaining a vertical projection from a measured value and a determination section for determining a failure mode of the storage element under test based on the projection data. .