JPH06187229A - Memory control circuit - Google Patents

Abstract

PURPOSE:To provide a memory control circuit which makes possible correct high-speed access to a page memory even if a large amount of data are trans ferred by burst transfer by eliminating control by a bus master over the memory address of the transfer source, the memory address of the transfer destination, and transfer units. CONSTITUTION:The memory control circuit which uses memory elements equipped with row address input and column address input and is equipped with an access arbitrating circuit 8 for arbitrating access to a memory 12 and a memory control signal generating circuit 10 for supplying a memory control signal for performing the burst transfer to the memory 12 according to the arbitration result of the access arbitrating circuit 8 is provided with a row address change point detecting circuit 19 which detects a change point in row address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing device provided with a memory circuit using a memory device having a column address input and a row address input, operating the memory circuit in burst mode transfer, and performing high-speed processing. .

[0002]

2. Description of the Related Art An image processing apparatus is a typical apparatus that executes a large amount of data processing. An image processing apparatus is often provided with a page memory for one page to several pages therein in order to perform edit processing on image data.
When performing image processing using a host computer, workstation, or personal computer, secure a memory space that can store the image data in the memory area inside these computer devices, and input the image data in that memory space. To perform image processing.

However, the amount of image data is 1
Since the page size ranges from several megabytes to several tens of megabytes, considerable time is consumed for inputting image data to the page memory and outputting image data from the page memory. During this time, the device cannot perform processing on the image data, so that the throughput of the device is significantly deteriorated.

In order to solve this problem, conventionally, it is general to use burst transfer with good transfer efficiency as a transfer method when inputting / outputting image data to / from a page memory. Data transfer control methods using burst transfer are disclosed in Japanese Patent Application Laid-Open No. 01-271861 and Japanese Patent Application Laid-Open No. 02-2.
50137 specification, JP-A-02-250138 specification,
It is disclosed in Japanese Patent Application Laid-Open No. 03-163638.

On the other hand, as a memory device for storing image data, a dynamic memory having a low bit unit price is usually used in many cases. When the dynamic memory is used, burst transfer is realized by using the page mode, static column mode, and nibble mode of the dynamic memory. FIG. 2 shows an example of a conventional memory control circuit used in the processing apparatus as described above. In FIG. 2, the access request signal RQB14 for burst transfer output from the bus master 1 is active and the other access request signals RQA13 and RQ.
The arbitration result 9 indicating the access request of the bus master 1 by the access arbitration circuit 8 when the one having a higher priority than the access request signal RQB14 in C15 is inactive.
In response to this, the memory control signal generation circuit 10 outputs the control signal 11 and the access response signal ACKB17 at the timing of burst transfer. At this time, the memory control signal generation circuit 10 continues the burst transfer while the arbitration result 9 indicates the access request of the bus master 1.

[0006]

In the embodiment of the prior art shown in FIG. 2, there are the following problems. For normal access to the dynamic memory, first the column address strobe (RAS) signal is input, the column address is taken into the dynamic memory at the active edge of this signal, and the RAS signal is kept active. Input an address strobe (CAS) signal. The row address is taken into the dynamic memory at the active edge of the CAS signal. The page mode, static column mode, and nibble mode of the dynamic memory are used to realize the burst transfer. For example, when the page mode is used, the RAS signal is activated and the column address is taken into the dynamic memory. , While keeping the RAS signal active, continuously activate the CAS signal to fetch the row address. After that, the CAS signal is made inactive and then made active again. By this operation, another row address is fetched and an address different from the first access is accessed. In this way, continuous high-speed access, that is, burst transfer is realized by inputting the CAS signal and the row address a plurality of times.

In these burst transfer methods, since the column address is input only once at the active edge of the RAS signal, the memory space accessible during one burst transfer is within the range in which the row address can be changed. Limited To give a concrete example, if a page memory of 1 megabyte is configured by using 8 dynamic memories of 1 mega x 1 bit configuration, there are 10 bits of address line input to the dynamic memory. By changing the address, the accessible range becomes 1 kilobyte.

However, when a large amount of data ranging from several megabytes to several tens of megabytes is continuously transferred, the column address always changes. However, in this case, since the column address is input only once at the active edge of the RAS signal, the second access and the third access are executed to the already accessed address, and the normal data transfer is performed. I can't do it. In the above example, [column address = 0, row address = 0
When the burst transfer is started from the memory address of [address], the access to the memory address of [column address = 0, row address = 1023] is followed by [column address = 0, row address = 0]. Second memory address is executed.

The above example describes the case where a continuous address area of the memory is accessed in the forward direction of the address (direction from a small address to a large address). When accessing in the reverse direction (direction from large address to small address), as in the previous example,
Since the second and third accesses are executed to the addresses that have already been accessed, normal data transfer cannot be performed.

In order to avoid the above-mentioned inconvenience, conventionally, a bus master manages a memory address of a transfer source, a memory address of a transfer destination and a transfer unit, and controls so as not to perform a burst transfer across a change point of a column address. There is. This imposes restrictions on the transfer source memory address, transfer destination memory address, and transfer unit. Burst transfer between arbitrary addresses cannot be performed, and the transfer source memory address and transfer destination memory address cannot be Transfer unit management becomes complicated.

As described above, when a large amount of data is transferred by the conventional burst transfer system, the transfer cannot be normally performed at the address where the column address changes, and the original of the burst transfer system that transfers a large amount of data at high speed is essential. There is a problem that even the purpose of can not be achieved. Further, there is a problem that management of a transfer source memory address and a transfer destination memory address and a transfer unit in the bus master becomes complicated.

According to the present invention, the management of the transfer source memory address and the transfer destination memory address and the transfer unit in the bus master is eliminated, and the page memory can be correctly accessed at high speed even when a large amount of data is transferred by burst transfer. An object is to provide a possible memory control circuit.

[0013]

In order to solve the above-mentioned problems, the present invention firstly uses a memory element having a column address input and a row address input to access a memory. In a memory control circuit including an access arbitration circuit for arbitration and a memory control signal generation circuit for supplying a memory control signal for executing burst transfer to a memory according to the arbitration result of the access arbitration circuit, A column address change point detection circuit for detecting a change point is provided. That is,
The column address change point detection circuit is provided in the memory control circuit.

Secondly, in the memory control circuit, when the column address change point detection circuit detects a column address change point during burst transfer, the memory control signal generation circuit performs burst transfer. It is characterized by controlling to stop. That is, stop of burst transfer is controlled according to the detection result of the column address change point detection circuit.

Thirdly, in the memory control circuit, when the column address change point detection circuit does not detect the column address change point during the burst transfer in the burst transfer, the burst occurs in the memory control signal generation circuit. It is characterized by controlling to continue the transfer. That is, the continuation of burst transfer is controlled by the detection result of the column address change point detection circuit.

Fourth, in the memory control circuit, when the column address change point detection circuit detects a column address change point during burst transfer during burst transfer, burst transfer is performed in the memory control signal generation circuit. When the access arbitration circuit outputs an arbitration result that controls to stop and continues to request execution of the burst transfer even after the burst transfer is stopped, the memory control signal generation circuit determines the column address and the row address. Is re-input to the memory device and controlled to restart the burst transfer. That is, when the stop result of the burst transfer is controlled by the detection result of the column address change point detection circuit and the arbitration result for continuously requesting the execution of the burst transfer is output from the access arbitration circuit. In addition, the memory control signal generation circuit is controlled to re-input the column address and the row address into the memory device and restart the burst transfer.

Fifth, in the memory control circuit, the restart of the burst transfer is automatically restarted by the memory control signal generating circuit even if the bus master requesting the burst transfer does not control. To do. That is, the burst transfer is restarted automatically by the memory control signal generation circuit without involvement of the bus master.

[0018]

When the access request signal for burst transfer from the bus master is input to the access arbitration circuit, the access arbitration circuit arbitrates the access request according to a predetermined access priority and outputs the arbitration result to the memory control signal generation circuit. To do. When the arbitration result is a burst transfer access request from the bus master, the memory control signal generation circuit outputs a control signal and an access response signal at the timing of burst transfer. At this time, the column address change point detection circuit monitors the column address, and when the column address change point is detected, the detection result is output to the memory control signal generation circuit. In the memory control signal generation circuit, the arbitration result indicates an access request for burst transfer from the bus master,
The burst transfer is continued while the detection result output from the column address change point detection circuit is inactive. The burst transfer is stopped when the arbitration result does not indicate an access request for burst transfer from the bus master or when the detection result output from the column address change point detection circuit becomes active.

Further, even after the burst transfer is stopped by the detection result output from the column address change point detection circuit becoming active, the arbitration result requesting execution of the burst transfer is continuously output from the access arbitration circuit. If so, the memory control signal generation circuit re-inputs the column address and the row address into the memory element and restarts the burst transfer. The burst control is automatically restarted by the memory control signal generation circuit without any involvement of the bus master.

By performing such control, the burst transfer across the change point of the column address can be stopped / restarted, normal data transfer can be performed, and the load on the bus master can be reduced.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a memory control circuit according to an embodiment of the present invention. In FIG. 1, the bus master 1 is assumed as a device that accesses the dynamic memory 12. The bus master 1 has a data bus 2 and an address bus 3. Data bus 2 is bidirectional bus buffer 4
Through the memory data bus 6 of the dynamic memory 12
It is connected to the. The address bus 3 is connected to the time division address bus MADD7 of the dynamic memory 12 via the column address / row address switching circuit 5. Also,
The address bus 3 is also connected to the column address change point detection circuit 19, and the column address change point detection circuit 19 outputs the detection result RADD 20 to the memory control signal generation circuit 10. Access request signal RQ output from bus master 1
B14 is input to the access arbitration circuit 8 together with access request signals RQA13 and RQC15 output from other devices. The access arbitration circuit 8 arbitrates the access request signals RQA13, RQB14, and RQC15 in accordance with a predetermined access priority order, and outputs an arbitration result 9 to the memory control signal generation circuit 10. The memory control signal generation circuit 10 uses the arbitration result 9 and the detection result R.
Based on the ADD 20, the control signal 11 of the dynamic memory 12 and the access response signals ACKA16 and ACKB1
7. Control and output ACKC18.

Next, the operation of the embodiment shown in FIG. 1 will be described. It should be noted that the low-active signal in each figure is represented by adding "n" to the beginning of the symbol of each signal, and the dynamic memory 12 has a size of 1 mega x 1 for convenience of explanation.
It is assumed that eight 1-bit dynamic memories are used to form a 1-megabyte memory. A case where the bus master 1 makes a burst transfer read access to the dynamic memory 12 will be described. First, the bus master 1 outputs an address indicating the dynamic memory 12 to the address bus 3. At the same time, the bus master 1 outputs the access request signal RQB14 to the access arbitration circuit 8. When the bus master 1 is a CPU, the access request signal RQB14 is often a chip select signal obtained by decoding the address output to the address bus 3. When the bus master 1 is an input / output device such as an image processing device or a hard disk controller, this access request signal RQB14 is D
MA (direct memory access) requests and the like.

In the access arbitration circuit 8 to which the access request signal RQB14 is input, the access request signals RQA13 and RQ follow the predetermined access priority order.
Arbitration of B14 and RQC15. An example of the access arbitration circuit 8 is shown in FIG. In FIG. 3, the access request signal RQ
A13 has the highest access priority, followed by RQB1
4 and RQC15 in that order. Therefore, when the access request signal RQA13 becomes active, RQB
14, arbitration result ARA2 regardless of the state of RQC15
1 becomes active and at the same time ARB22 and ARC
23 becomes inactive. Access request signal RQB
In order for this access request signal to be accepted when 14 becomes active, the RQA 13 needs to be inactive. The state of arbitration result 9 at this time is ARA.
21 is inactive, ARB22 is active, AR
C23 becomes inactive. Access request signal RQ
In order for this access request signal to be accepted when C15 becomes active, RQA13 and RQB1
Both 4 need to be inactive. The state of arbitration result 9 at this time is that ARA21 is inactive and ARB is
22 becomes inactive and ARC 23 becomes active. Summarizing the operation of the embodiment shown in FIG. 3, the arbitration results ARA21, ARB22, and ARC23 are exclusively controlled. The following description will be made based on the access arbitration circuit of FIG. Now, assuming that the access request signal RQB14 is active and the RQA13 is inactive, the arbitration result 9 output from the access arbitration circuit 8 is that only the ARB 22 is active.
The arbitration result 9 is output to the memory control signal generation circuit 10 in the next stage as shown in FIG.

In the memory control signal generation circuit 10 shown in FIG. 1, the arbitration result 9 is received and the control signal 1 is sent at an appropriate timing.
1 and access response signals ACKA16, ACKB1
7, ACKC18 is generated. An example of the memory control signal generation circuit 10 is shown in FIG. In FIG. 4, all the signals ARA21, ARB22, and ARC23 of the arbitration result 9 are RAS.
Generation circuit 24, CAS generation circuit 25, WE generation circuit 2
6, input to the OE generation circuit 27. RAS generation circuit 24, CAS generation circuit 25, WE generation circuit 26, OE
The generation circuit 27 uses the arbitration results ARA21, ARB22, AR
When any one of C23 is activated, the control signal 11 is generated at an appropriate timing according to the access request.

FIG. 5 is a state transition diagram showing an embodiment of the RAS generation circuit 24. In FIG. 5, the arbitration results ARA21, ARB22, ARC23, which are input signals, and the detection result R
The active state of the ADD 20 is represented by not adding a "-" symbol to the beginning of each signal symbol, and the inactive state is represented by adding a "-" symbol. The "x" symbol represents a logical product, and the "+" symbol represents a logical sum. The RAS generation circuit of FIG. 5 uses the arbitration results ARA21, AR
When B22 and ARC23 are all inactive, the standby state SI is looped. Arbitration result ARA21
Becomes active, the nRAS signal 31 is generated at an appropriate timing to transition to the state SA and process the access request signal RQA13. Mediation result ARC
23 becomes active (Note: the condition in this case does not have to be "-ARA x -ARB x ARC" because ARA, ARB, and ARC are exclusively controlled). , State SC and access request signal R
NRA is executed at an appropriate timing to perform the processing of QC15.
The S signal 31 is generated. In either case, when the generation of the nRAS signal 31 is completed, the standby state SI is restored. Here, since the contents of the processing executed by the access request signals RQA13 and RQC15 are not directly related to the operation of the present invention, the operation of the states SA and SC will not be described in detail. When the arbitration result ARB22 becomes active (see "Note" above), the nRAS signal 31 is generated at an appropriate timing for processing the access request signal RQB14.

More specifically, the arbitration result ARB22
5 becomes active, the RAS generation circuit of FIG. 5 transits from the standby state SI to the state SB1 and asserts the nRAS signal 31. In state SB1, arbitration results ARA21, A
The RB 22 and the detection result RADD 20 are monitored. The detection result RADD 20 is output from the column address change point detection circuit 19 as shown in FIG. State SB in FIG.
If the detection result RADD20 is inactive and the ARB22 is active in 1, the state transitions to the state SB1 again, and the nRAS signal 31 is continuously asserted. After that, in the state SB1, the state SB1 continues to be looped until the condition that the ARB 22 is inactive or the RADD 20 is active is satisfied. When the above condition is satisfied, the state transits to the state SB2, and the nRAS signal 31 is negated.

Table 1 shows a truth table showing the transition from the state SB1 to the next state. Table 2 shows a simplified version of Table 1. The transition from the state SB1 in FIG. 5 to the next state is based on Table 2. However, ARA21 = 0 and ARB in Table 2
The condition of 22 = 1 is ARA21, AR in FIG.
Since B22 is exclusively controlled, it is equivalent to the condition of ARB22 = 1. Therefore, only the condition of ARB22 = 1 is reflected in FIG. The state SB2 unconditionally returns to the standby state SI. CAS generation circuit 2 shown in FIG.
5, the circuits of the WE generation circuit 26 and the OE generation circuit 27 can be realized in the same sequence, and therefore the details thereof will be omitted.

The arbitration result ARA21 and the detection result RADD20 are input to the access response signal A generation circuit 28 of FIG. 4, and it operates to generate the access response signal ACKA16 only when the arbitration result ARA21 becomes active. The arbitration result ARB22 and the detection result RADD20 are input to the access response signal B generation circuit 29, and operate to generate the access response signal ACKB17 only when the arbitration result ARB22 becomes active. Similarly, the arbitration result ARC23 and the detection result RADD20 are input to the access response signal C generation circuit 30 and operate to generate the access response signal ACKC18 only when the arbitration result ARC23 becomes active. The access response signal A generation circuit 28, the access response signal B generation circuit 29, and the access response signal C generation circuit 30 can be realized in the same sequence as the RAS generation circuit shown in FIG. .

Here, the RAS generation circuit 24, C in FIG.
AS generation circuit 25, WE generation circuit 26, OE generation circuit 2
7 and access response signal A generation circuit 28, access response signal B generation circuit 29, access response signal C generation circuit 3
The column address change point detection circuit 19 in FIG. 1 that generates and outputs the detection result RADD 20 input to 0 will be described. An example of the column address change point detection circuit 19 is shown in FIG.

The column address change point detection circuit shown in FIG.
It comprises a column address latch circuit 36 and a column address comparison circuit 38. The column address latch circuit 36 uses the address bus 3
An address line corresponding to the column address is input, and this is latched by the column address latch clock 35. As the column address latch clock 35, nRA shown in FIG.
The S signal 31 can be used as it is. When the bus master 1 in FIG. 1 is a CPU, it is also possible to use an address strobe signal, an address latch enable signal or the like output by the CPU as the column address latch clock 35. In the following description, the case where the nRAS signal 31 shown in FIG. 4 is used as the column address latch clock 35 will be described.

The RAS generation circuit 24 shown in FIG.
When the signal 31 is output, the column address latch circuit 36 shown in FIG. 6 latches the column address at the active edge (falling edge) of the nRAS signal 31. Here, the value of the latched 10-bit column address is set to 001 [He
x]. Latched column address, ie Figure 6
Latch address LADD37 of the column address comparison circuit 3
8 is input. This latch address LADD37 is n
It does not change until RAS signal 31 is asserted again.
That is, it is held during one burst transfer.

On the other hand, the address output to the address bus 3, especially the address line corresponding to the row address of the address bus 3 changes every moment during the burst transfer. In the column address comparison circuit 38, the latch address LAD
D37 is compared with the address line corresponding to the column address of the address bus 3. When the comparison results match, the detection result RADD20 is not output. When the burst transfer progresses and all the address lines corresponding to the row address become high (3FF [Hex]), all the address lines corresponding to the row address are low (000 [He] in the next transfer.
x]), and instead the address line corresponding to the column address changes to 002 [Hex]. In this case, the comparison result of the latch address LADD37 and the address line corresponding to the column address of the address bus 3 does not match, so that the detection result RADD20 is output from the column address comparison circuit 38.
Will be output. This signal is supplied to the memory control signal generation circuit 10 shown in FIG.

FIG. 7 is a timing chart showing the operation of the embodiment of FIG. 1 described so far, and shows the operation when the column address change point is not crossed during one burst transfer. The three-digit number in the figure represents the value of a 10-bit column address or row address in Hex. In FIG. 7, the latch address LADD37 latched at the active edge (falling edge) of the nRAS signal 31 is 001 [Hex], and the address line corresponding to the row address of the address bus 3 is 001 during burst transfer. 002, 003, 004, 005 [He
x]. During this one burst transfer, the address line corresponding to the row address of the address bus 3 does not change from 3FF [Hex] to 000 [Hex], so the address line corresponding to the column address is 001 [H
ex] does not change. Therefore, the detection result RADD2
Since 0 is not active, burst transfer continues until the access request signal RQB14 is negated,
Normal termination after negation.

FIG. 8 is a timing chart showing the operation of the embodiment of FIG. 1 described so far, and shows the operation when the column address change point is crossed during one burst transfer. The three-digit number in the figure represents the value of a 10-bit column address or row address in Hex. In FIG. 8, the latch address LADD37 latched at the first active edge (falling edge) of the nRAS signal 31 is 001 [Hex], and the address line corresponding to the row address of the address bus 3 is in burst transfer. 3FE, 3FF, 000 [Hex]. During this one burst transfer, the address line corresponding to the row address of the address bus 3 is 3FF [Hex].
From 000 [Hex] to 000 [Hex], the address line corresponding to the column address changes from 001 [Hex] to 002.
Change to [Hex]. Detection result RADD at this point
Since 20 becomes active, each signal generation circuit 24 to
Detecting this, 30 interrupts the operation for processing the access request signal RQB14, and as a result, the burst transfer is stopped. However, since the arbitration result ARB22 is still active after the burst transfer is stopped, the signal generation circuits 24 to 30 detect this and access request signal R
The operation for performing the processing of QB14 is restarted. This causes the burst transfer to be restarted, and the restart of the burst transfer is automatically performed by the memory control signal generation circuit 10 even if the bus master 1 of FIG. 1 does not perform control for restart. .

Although the memory control circuit of the embodiment of the present invention shown in FIG. 1 operates as described above, the configuration of the present invention is not limited to the configuration of FIG. 1 and does not deviate from the gist of the present invention. It is possible to apply and change the range. The general operation is the same as that of the embodiment shown in FIG. 1, so detailed description thereof will be omitted, but a configuration different from the embodiment of FIG. 1 is shown in FIG. 9 as a second embodiment of the present invention.

[0036]

[Table 1] Truth table showing transition from the state SB1 to the next state ───────────────────────────────── ──── RADD ARA ARB Meaning of input signal Next state transition (20) (21) (22) ────────────────────────── ─────────── 0 0 0 Both RADD and ARA are active Transition to SB2 but ARB is inactive, so transfer ends normally ─────────── ───────────────────────── 0 0 1 RADD and ARA are not active Transition to state SB1 and ARB is active. Continue ──────────────────────────────────── 0 1 0 RADD is inactive but transitions to state SB2 ARB is inactive, so transfer is completed normally . In this case, it doesn't make sense that ARA is active ───────────────────────────────── ──── 0 1 1 Both ARA / ARB are active and none is possible in the circuit in Fig. 3 (transition to state SB2) ────────────────── ────────────────── 1 0 0 RADD is active, but transitions to state SB2 ARA and ARB are both inactive, so transfer ends normally ─── ───────────────────────────────── 1 0 1 Since RADD is active, transition to state SB2 ARA is in active, ARB to force interrupting the transfer may be active ──────────────────────────────────── 1 1 0 RADD is active, Transition ARB to state SB2 is successful completion of the transfer because it is inactive, that the case of this ARA is Tsu Do not active is not a meaningless ─────────────── ───────────────────── 1 1 1 The ARA / ARB are both active and none in the circuit of Fig. 3 (transition to state SB2). ─────────────────────────────────── Note: In the table, 0 is inactive and 1 is active. Represent

[0037]

[Table 2] Truth table showing transition from the state SB1 to the next state (simplified table of Table 1) ──────────────────────── ─── RADD ARA ARB Next state transition (20) (21) (22) ─────────────────────────── XX 0 State SB2 Transition ────────────────────────── 0 0 (equivalent to X) 1 Transition to state SB1 ──────────── ─────────────── 1 XX Transition to SB2 ────────────────────────── Note: Table 0 represents inactive, 1 represents active, and X represents 0 or 1.

[0038]

As described above, according to the present invention, even when a large amount of data is transferred across the column address changing points, the column address changing points are detected and burst transfer is continued / stopped / restarted. By controlling so that it becomes possible to access the page memory correctly and at high speed. Also,
By controlling the restart of burst transfer to be executed automatically without the control of the bus master, it is possible to eliminate the complicated process of managing the transfer source memory address and the transfer destination memory address and the transfer unit in the bus master. Become.
As a result, it is possible to provide a highly reliable memory control circuit with low overhead.

FIG. 9 shows a second embodiment of the present invention in which some of the connections in the block diagram of FIG. 1 are modified. That is, in this embodiment, the column address change point detection circuit 19 is not connected to the address bus 3 and the time division address bus M
It is connected to ADD7.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional technique.

FIG. 3 is a circuit diagram showing an embodiment of the access arbitration circuit shown in FIGS. 1 and 2.

FIG. 4 is a block diagram showing an embodiment of the memory control signal generation circuit of FIGS. 1 and 2.

5 is a state transition diagram showing an embodiment of a RAS generation circuit of the memory control signal generation circuits of FIGS. 1 and 2. FIG.

6 is a block diagram showing an embodiment of the column address change point detection circuit of FIG.

FIG. 7 is a timing chart showing the operation of the embodiment of FIG.

FIG. 8 is a timing chart showing the operation of the embodiment of FIG.

FIG. 9 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols] 1 bus master 2 data bus 3 address bus 4 bidirectional bus buffer 5 column address / row address switching circuit 6 memory data bus 7 time division address bus (MADD) 8 access arbitration circuit 9 arbitration result 10 memory control signal generation Circuit 11 Control signal 12 Dynamic memory 13 Access request signal A (RQA) 14 Access request signal B (RQB) 15 Access request signal C (RQC) 16 Access response signal A (ACKA) 17 Access response signal B (ACKB) 18 Access response Signal C (ACKC) 19 Column address change point detection circuit 20 Detection result (RADD) 21 Arbitration result A (ARA) 22 Arbitration result B (ARB) 23 Arbitration result C (ARC) 24 Column address strobe (RAS) generation circuit 25 rows Address strobe ( AS) generation circuit 26 write enable (WE) generation circuit 27 output enable (OE) generation circuit 28 access response signal A (ACKA) generation circuit 29 access response signal B (ACKB) generation circuit 30 access response signal C (ACKC) generation Circuit 31 Column address strobe (nRAS) signal 32 Row address strobe (nCAS) signal 33 Write enable (nWE) signal 34 Output enable (nOE) signal 35 Column address latch clock 36 Column address latch circuit 37 Latch address (LADD) 38 columns Address comparison circuit

Claims (5)

[Claims] 1. A column (Row) address input and a row (Col)
umn) an access arbitration circuit for arbitrating access to the memory using a memory element having an address input,
A column address change check for detecting a column address change point in a memory control circuit having a memory control signal generation circuit for supplying a memory with a memory control signal for executing burst transfer according to the arbitration result of the access arbitration circuit A memory control circuit having an output circuit. 2. The memory control circuit according to claim 1, wherein when the column address change point detection circuit detects a column address change point during burst transfer, burst occurs in the memory control signal generation circuit. A memory control circuit characterized by controlling to stop transfer. 3. The memory control circuit according to claim 1 or 2, wherein when the column address change point detection circuit does not detect a column address change point during burst transfer, the memory A memory control circuit, wherein control is performed so that burst transfer is continued in a control signal generation circuit. 4. The memory control circuit according to claim 1, 2, or 3, wherein when the column address change point detection circuit detects a column address change point during burst transfer, If the memory control signal generation circuit controls to stop the burst transfer, and the access arbitration circuit outputs an arbitration result that continuously requests execution of the burst transfer even after the burst transfer is stopped, The control signal generation circuit is characterized in that the column address and the row address are re-input to the memory device to control the burst transfer again. 5. The memory control circuit according to claim 4, wherein the burst transfer is restarted by the memory control signal generation circuit automatically restarting without being controlled by a bus master requesting the burst transfer. Characteristic memory control circuit.