JPH06177130A - Wiring layer of semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a wiring layer of a semiconductor device having a structure capable of suppressing diffusion of an impurity region during heat treatment of a wiring layer, and a manufacturing method thereof. [Structure] The second refractory metal silicide layer 18 forming the second wiring layer 40 has a resistance lower than that of the material of the first refractory metal silicide layer 5 forming the first wiring layer 30 by heat treatment. It is formed using a material. Thereby, when the first refractory metal silicide layer 5 is heat-treated, diffusion of impurities in the impurity regions 9, 9, 13 formed in the semiconductor substrate 1 is suppressed, and deterioration of element characteristics of the semiconductor device is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring layer of a semiconductor device, and more particularly to a wiring layer of a semiconductor device having a structure that does not affect a semiconductor element formed in the semiconductor device and a manufacturing method thereof. .

[0002]

19 is a plan structural view of a memory cell of a DRAM, and FIG. 20 is a sectional structural view taken along the line A--A in FIG.

First, referring to FIGS. 19 and 20, D
The structure of the memory cell of the RAM will be described. A plurality of word lines 30 extending in a predetermined direction are formed on the surface of the silicon substrate 1.
And a plurality of bit lines 40 extending in a direction orthogonal to the bit lines are arranged in a matrix. A plurality of memory cells are arranged in a matrix along the word line 30 and the bit line 40. The memory cell is composed of one transfer gate transistor 100 and one capacitor 200.

Transfer gate transistor 100
Includes a gate electrode (word line) 30 formed on the surface of silicon substrate 1 with gate insulating layer 3 interposed, and a pair of source / drain regions 9, 9. The capacitor 200 is
It has a laminated structure of a lower electrode 23, a dielectric layer 25, and an upper electrode 26. The lower electrode 23 of the capacitor 200 is composed of a base portion 23a having a relatively flat shape and an upright wall portion 23b protruding in the vertical direction.

As a result, in such a structure, the surface area of the capacitor is increased and the capacitance of the capacitor is increased. The upper portion of the capacitor 200 is covered with the first interlayer insulating layer 27. On the surface of the first interlayer insulating layer 27,
The wiring layer 28 is formed. Further, a second interlayer insulating film 29 that covers the wiring layer 28 is formed. A wiring layer and a passivation film are present on the second interlayer insulating film 29, but they are omitted in the figure.

The bit line 40 is formed in a direction orthogonal to the word line 30 and at a position lower than the upper end of the capacitor 45. Such a structure is called a so-called embedded bit line. The bit line 40 is connected to one of the source / drain regions 9 of the transfer gate transistor 100.

The gate electrode (word line) 30 is composed of a polycrystalline silicon layer 4 containing impurities therein and, for example, a tungsten silicide layer 5 formed along the upper surface of the polycrystalline silicon layer 4. . Gate electrode 3
The upper part of 0 is the upper insulating film 6 made of a silicon oxide film or the like.
And a side surface thereof is also covered with a side insulating film 10 made of a silicon oxide film or the like. The upper insulating film 6 and the side insulating film 10 are formed on the bit line 40.
Insulation between the gate electrode 30 and the gate electrode 30 is ensured.

Like the gate electrode 30, the bit line 40 is composed of a polysilicon layer 17 and a tungsten silicide layer 38 formed along the upper surface of the polysilicon layer 17. Furthermore, this bit line 4
An upper insulating layer 19 is formed on the upper part of 0, and a side insulating layer 33 is formed on the side surface thereof. This upper insulating layer 1
9 and the side insulating layer 33 are, for example, the capacitor 200.
The insulation between the lower electrode 23 and the lower electrode 23 is secured.

Next, a manufacturing process of a memory cell including the above word line and bit line will be described with reference to FIGS. 21 to 34. 21 to 34 are manufacturing process diagrams corresponding to the sectional structure shown in FIG.

First, referring to FIG. 21, a silicon substrate 1
A field oxide film 2 made of a thick oxide film is formed on a predetermined region of the surface by the LOCOS method.

Next, referring to FIG. 22, the silicon substrate 1
A gate insulating film 3 such as an oxide film or a nitride film is formed on the surface. In addition, CVD (Chemical Vapor)
Depositing the polysilicon layer 4 to 50
Deposit to a thickness of 0-2000 Angstroms. After that, a tungsten (W) layer is formed on the polysilicon layer 4 by a CVD method or a sputtering method in an amount of 100 to 1
Form a thickness of 000 angstroms. After that, for example, when a tungsten layer is formed by using the CVD method, heat treatment is performed by diffusion furnace annealing. By this heat treatment, the tungsten layer in contact with the surface of the polysilicon layer 4 causes a silicidation reaction to form the tungsten silicide layer 5 on the upper surface of the polysilicon layer 4, and at the same time, lower the resistance of the tungsten silicide layer 5 (about 50 to 50). 80 μΩ
cm) is also planned.

Next, an insulating film 6 made of a silicon oxide film or a silicon nitride film is formed on the tungsten silicide layer 5.

Next, referring to FIG. 23, on the insulating layer 6,
A resist film 7 having a pattern of a predetermined shape is formed, the insulating layer 6 is etched using the resist film 7 as a mask, and patterning is performed in a predetermined shape.

Next, referring to FIG. 24, after removing the resist film 7, the tungsten silicide layer 5 and the polysilicon layer 4 are etched using the insulating layer 6 patterned into a predetermined shape as a mask. As a result, the word line 30 having a two-layer structure of the polysilicon layer 4 and the tungsten silicide layer 5 is completed. Then, using the gate electrode 30 and the insulating film 6 as a mask, impurities 8 are injected into the surface of the semiconductor substrate 1 to form a pair of source / source.
Drain regions 9 and 9 are formed.

Next, referring to FIG. 25, the silicon substrate 1
An insulating film 10 made of a silicon oxide film or a silicon nitride film is formed on the entire upper surface by the CVD method.

Then, referring to FIG. 26, anisotropic etching such as reactive ion etching is performed to form insulating layer 1.
0 is left only on the side wall of the gate electrode 30.

Next, referring to FIG. 27, a resist film 11 is formed on the surface of the semiconductor substrate 1 so that only one of the pair of source / drain regions 9 is opened, and the resist film 11 is used as a mask. As a result, impurities are implanted into the surface of the semiconductor substrate 1 to form the impurity regions 13.

Next, referring to FIG. 28, an insulating layer 14 such as a silicon oxide film or a silicon nitride film is formed on the entire surface of the semiconductor substrate 1 by the CVD method.

Next, referring to FIG. 29, again, a resist film 15 having an opening only above the impurity region 13 is formed on the upper surface of the semiconductor substrate 1, and the insulating layer 14 is etched using the resist film 15 as a mask. To do.

Next, referring to FIG. 30, polycrystalline silicon layer 17 is formed on the entire surface of semiconductor substrate 1 by the CVD method or the like.
Is deposited to a thickness of 500 to 2000 angstroms. Then, referring to FIG. 31, a tungsten (W) layer having a thickness of 100 to 1000 angstrom is formed on polycrystalline silicon layer 17 by the CVD method or the sputtering method. After that, for example, when the tungsten layer is formed by the CVD method, the lamp annealing method is used.
In a nitrogen atmosphere, at a temperature of 900 to 1100 ° C., 1
Heat treatment is applied for 0 to 60 seconds. By this heat treatment, the tungsten layer in contact with the surface of the polycrystalline silicon layer 17 causes a silicidation reaction to form the tungsten silicide layer 38 on the surface of the polycrystalline silicon layer 17, and at the same time, lower the resistance of the tungsten silicide layer 38 (about 50%). ~ 60μΩc
m) is also planned.

Next, referring to FIG. 32, an insulating layer 19 made of a silicon oxide film, a silicon nitride film or the like is formed on the upper surface of the tungsten silicide film 38 by the CVD method.

Thereafter, referring to FIG. 33, the resist film 2
0 is formed, and the insulating layer 19 is patterned by etching using the resist film 20 as a mask.

Next, referring to FIG. 34, the resist film 20.
Then, the tungsten silicide film 38 and the polycrystalline silicon layer 17 are patterned by etching using the insulating layer 19 as a mask to complete the bit line 40 having a two-layer structure of the tungsten silicide film 38 and the polycrystalline silicon layer 17. To do.

Thereafter, a capacitor is manufactured to complete the semiconductor device having the sectional structure shown in FIG.

[0025]

However, the above-mentioned conventional technique has the problems described below with reference to FIG. FIG. 35 is an enlarged cross-sectional view showing a contact portion between the bit line 40 and the source / drain regions 9, 9.

First, referring to FIG. 35, a polycrystalline silicon layer 17 is formed at the contact portion between the source / drain regions 9, 9 and the bit line 40, and this polycrystalline silicon layer 17 is formed.
After the tungsten layer is deposited on the upper surface of the above, the tungsten layer is silicified by performing a predetermined heat treatment to form the tungsten silicide layer 38.

However, this tungsten silicide layer 3
8 during the heat treatment by diffusion furnace annealing,
The impurities in the drain regions 9 and 9 and the impurity region 13 are
The channel width (L _{1 in the} drawing) of the transfer gate transistor 100 is shortened (L _{2 in the} drawing) due to diffusion as shown by the dotted line in the drawing, and the depletion layer in the drain region is connected to the depletion layer in the source region. However, there is a problem that the so-called punch-through phenomenon easily occurs.

The present invention has been made in order to solve such a problem, and a wiring layer of a semiconductor device having a structure capable of suppressing diffusion of impurities in an impurity region during heat treatment of the wiring layer. And a method for manufacturing the same.

[0029]

In a wiring layer of a semiconductor device according to claim 1 of the present invention, a semiconductor substrate, an impurity region formed in the semiconductor substrate, and an insulating film on the semiconductor substrate. A first wiring layer including a first refractory metal silicide layer and a second refractory metal silicide layer provided via an insulating film between the first wiring layer and the first wiring layer. And a second wiring layer including.
Further, the second refractory metal silicide layer is made of a material whose resistance is lowered by heat treatment at a temperature lower than that of the first refractory metal silicide layer or for a short time.

Next, in a wiring layer of a semiconductor device according to a second aspect of the present invention, which is the wiring layer of the semiconductor device according to the first aspect, the first refractory metal silicide layer is provided. Is made of tungsten silicide, and the second refractory metal silicide layer is made of titanium silicide.

Next, a method for manufacturing a wiring layer of a semiconductor device according to a third aspect of the present invention includes the following steps.

First, on the semiconductor substrate with an insulating film interposed,
A first wiring layer including a first refractory metal silicide layer having a low resistance at the first temperature is formed through the heat treatment at the first temperature.

Next, after forming the first wiring layer,
Impurities are introduced into the surface of the semiconductor substrate to form impurity regions.

Next, after forming the impurity region, the first wiring layer and the first wiring layer are interposed, and the first insulating layer is formed between the first wiring layer and the first wiring layer.
A second wiring layer including a second refractory metal silicide layer having a low resistance at a second temperature lower than the temperature is formed by heat treatment at the second temperature.

Next, in a method of manufacturing a wiring layer of a semiconductor device according to a fourth aspect of the present invention, the third aspect of the present invention is provided.
The method for manufacturing a wiring layer of a semiconductor device according to claim 1, wherein the first wiring layer is tungsten silicide, the second wiring layer is titanium silicide, and the first temperature is 900 to 1100 ° C. Yes, the second temperature is 600
~ 800 ° C.

[0036]

According to the semiconductor device and the method of manufacturing the same according to the present invention, the second wiring layer formed after the impurity region is subjected to heat treatment at a temperature lower than that of the first wiring layer formed before the impurity region. Formed, and the resistance is reduced. Therefore, in the heat treatment for forming the second wiring layer, the diffusion of the impurities in the impurity region formed in the semiconductor substrate into the semiconductor substrate is relatively suppressed, so that the expansion of the impurity region during the heat treatment is suppressed. To be

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment based on the present invention will be described below with reference to the drawings. The structure of the wiring layer of the semiconductor device according to this embodiment is not limited to a specific semiconductor device and can be widely applied. As an example thereof, in the following embodiments, an example applied to a word line (gate electrode) or a bit line of DRAM will be described.

FIG. 1 is a plan structural view of a DRAM memory cell, and FIG. 2 is a sectional structural view taken in a direction along a cutting line A--A in FIG. Referring to FIG. 1 and FIG.
First, the structure of the memory cell of the DRAM will be described. A plurality of word lines 30 extending in a predetermined direction and a plurality of bit lines 40 extending in a direction orthogonal to the word lines 30 are arranged in a matrix on the surface of the silicon substrate 1. Further, a plurality of memory cells are arranged in a matrix along the word lines 30 and the bit lines 40. The memory cell is composed of one transfer gate transistor 100 and one capacitor 200.

Transfer gate transistor 100
Includes a gate electrode (word line) 4 formed on the surface of silicon substrate 1 with a gate insulating layer 3 interposed, and a pair of source / drain regions 9, 9. The capacitor 200 has a laminated structure of a lower electrode 23, a dielectric film 25, and an upper electrode 26. The lower electrode 23 of the capacitor 200 is composed of a base portion 23a having a relatively flat shape and a standing wall portion 23b protruding vertically upward.

As a result, such a structure increases the surface area of the capacitor and increases the capacitance of the capacitor. The upper portion of the capacitor 200 is covered with the first interlayer insulating layer 27. A wiring layer 28 is formed on the surface of the first interlayer insulating layer 27.
Is formed. Further, a second interlayer insulating film 29 that covers the wiring layer 28 is formed. The second interlayer insulating film 2
A wiring layer and a passivation film are provided on the substrate 9, but they are omitted in the figure.

The bit line 40 is formed in a direction orthogonal to the word line 30 and at a position lower than the upper end of the capacitor 200. Such a structure is called a so-called buried bit line. The bit line 40 is connected to one of the source / drain regions 9 of the transfer gate transistor 100.

The gate electrode 30 is composed of a polycrystalline silicon layer 4 containing impurities therein, and a tungsten silicide layer 5 formed along both side surfaces of the polycrystalline silicon layer 4. The upper part of the gate electrode 30 is covered with an upper insulating layer 6 made of a silicon oxide film or the like.
The side surface is also covered with a side insulating film 10 made of a silicon oxide film or the like. The upper insulating film 6 and the side insulating film 10 ensure insulation between the bit line 40 and the gate electrode 30.

The bit line 40 is similar to the gate electrode 30 in that the polycrystalline silicon layer 17 and the titanium silicide layer 18 formed on the upper surface of the polycrystalline silicon layer 17 are provided.
It consists of and. Further, the upper insulating layer 19 is formed on the bit line 40, and the side insulating layer 33 is formed on the side surface thereof. The upper insulating layer 19 and the side insulating layer 33 ensure insulation with the lower electrode 23 in the capacitor 200, for example.

Next, a manufacturing process of the memory cell including the above word line and bit line will be described. Figure 3
16 to 16 are manufacturing process diagrams corresponding to the sectional structure shown in FIG.

First, referring to FIG. 3, field oxide film 2 made of a thick oxide film is formed in a predetermined region on the surface of silicon substrate 1 by the LOCOS method.

Next, referring to FIG. 4, a gate insulating film 3 such as an oxide film or a nitride film is formed on the surface of the silicon substrate 1. Further, a polycrystalline silicon layer 4 is deposited on its surface by a CVD method or the like to a thickness of 500 to 2000 angstroms. Then, a tungsten layer having a thickness of 100 to 1000 angstrom is formed on the polycrystalline silicon layer 4 by the CVD method or the sputtering method.
For example, when the tungsten layer is formed by the CVD method, the lamp annealing method is then used to perform heat treatment at a temperature of 900 to 1100 ° C. for 10 to 60 seconds in a nitrogen atmosphere. By this heat treatment, the tungsten layer in contact with the surface of the polycrystalline silicon layer 4 causes a silicide reaction, the tungsten silicide layer 5 is formed on the upper surface of the polycrystalline silicon layer 4, and the resistance of the tungsten silicide layer is reduced (about 50 to 80 μΩm) is achieved. Further, an insulating layer 6 made of a silicon oxide film or a silicon nitride film is formed on the tungsten silicide layer 5 by using the CVD method.

Next, referring to FIG. 5, a resist film 7 having a predetermined pattern is formed on the upper surface of the insulating layer 6, and the insulating film 6 is patterned by etching using the resist film 7 as a mask. To do. Then, referring to FIG. 6, after removing resist film 7, tungsten silicide layer 5 and polycrystalline silicon layer 4 are patterned using insulating layer 6 as a mask. As a result, the gate electrode 30 having a predetermined shape is formed. Then, using the insulating layer 6 and the gate electrode 30 as a mask, impurities 8 are implanted into the surface of the semiconductor substrate 1 to form a pair of source / drain regions 9,
9 is formed.

Next, referring to FIG. 7, an insulating layer 10 made of a silicon oxide film or a silicon nitride film is formed on the entire surface of the semiconductor substrate 1 by the CVD method.

Then, referring to FIG. 8, anisotropic etching such as reactive ion etching is performed to leave insulating layer 10 only on the side wall of gate electrode (word line) 30.

Next, referring to FIG. 9, a resist film 11 is formed on the surface of the semiconductor substrate 1 so that only one of the pair of source / drain regions 9 is opened.
Impurity 12 is implanted into the substrate surface using 1 as a mask to form an impurity region 13.

Next, referring to FIG. 10, an insulating layer 14 such as a silicon oxide film or a silicon nitride film is formed on the entire surface of the semiconductor substrate 1 by the CVD method.

Next, referring to FIG. 11, again, on the upper surface of the semiconductor substrate 1, a resist film 15 having an opening only above the impurity region 13 is formed, and the insulating layer 14 is etched using the resist film 15 as a mask. To do.

Next, referring to FIG. 12, a polycrystalline silicon layer 17 is formed on the surface of semiconductor substrate 1 by the CVD method or the like.
To a thickness of 500-2000 Angstroms.
Then, referring to FIG. 13, a titanium layer is formed on the polycrystalline silicon layer 17 by CVD to a thickness of 100 to 1000 angstroms. Then, using a lamp annealing method at a temperature of 600 to 800 ° C. in a nitrogen atmosphere,
Heat treatment is applied for 10 to 60 seconds. By this heat treatment, the titanium layer in contact with the surface of the polycrystalline silicon layer 17 causes a silicidation reaction, and the titanium silicide layer 18 is formed on the surface of the polycrystalline silicon layer 17. In addition, the heat treatment temperature (° C.) of tungsten silicide and titanium silicide shown in FIG.
As can be seen from the graph showing the relationship between the specific resistance (μΩm) and the specific resistance (μΩm), heat treatment for the silicide reaction reduces the resistance of the titanium silicide layer 17 (about 10 to 30 μΩm)
Is planned. Since the heat treatment at this time is performed at a lower temperature than in the case of tungsten silicide, the diffusion of impurities in the source / drain regions 9 and 9 and the impurity region 13 during this heat treatment can be suppressed to a relatively small scale.

Next, referring to FIG. 14, an insulating layer 19 made of a silicon oxide film or the like is formed on the upper surface of the titanium silicide layer 18 by the CVD method.

Thereafter, referring to FIG. 15, resist film 2
0 is formed, and the insulating layer 19 is patterned by etching using the resist film 20 as a mask.

Next, referring to FIG. 16, a resist film 20 is formed.
Then, the titanium silicide film 18 and the polycrystalline silicon layer 17 are patterned by etching using the insulating layer 19 as a mask.
Then, the bit line 40 including the single crystal silicon layer 17 is formed.

Thereafter, capacitors are manufactured to complete the semiconductor device having the sectional structure shown in FIG.

In the above embodiment, a titanium silicide layer may be used as the first refractory silicide layer of the gate electrode, but the workability due to etching is good and the thermal stress caused by the temperature difference from the semiconductor substrate 1 is generated. It is desirable to use a small tungsten silicide layer.

As described above, the use of the titanium silicide layer having a low resistance at a temperature lower than that of tungsten silicide for the wiring layer forming the bit line makes it possible to perform heat treatment for silicidation and resistance reduction of the titanium layer. Also, the channel length of the transfer gate transistor 100 can be maintained without diffusion of the impurities in the impurity regions 9 and 9 and the impurity region 13.

Next, a second embodiment based on the present invention will be described with reference to FIG.

FIG. 18 is a sectional structural view corresponding to the direction along the section line AA in FIG. In the second embodiment, the gate electrode 30 of the DRAM is made of tungsten silicide only, and the bit line 40 is made of titanium silicide only.

In the process of forming the DRAM having the above structure, first, the word line is formed as shown in FIG.
In the step of, the tungsten silicide is directly deposited by the CVD method without the silicide step at a temperature of about 300-
It is formed under the condition of 600 ° C. In this case, since the resistance immediately after film formation is high, a sufficiently low resistance value cannot be obtained unless heat treatment at about 800 ° C. or higher is performed, as shown in FIG.

On the other hand, in formation of the bit line, FIG.
In the step shown in FIG. 13 and FIG. 13, titanium silicide is directly formed by the CVD method at a temperature of about 350 to 700 ° C. without including the silicide step. When the film is formed at about 700 ° C., a low-resistance film can be obtained immediately after that.
If a low temperature film formation of about 300 ° C. is performed, it will be
A sufficiently low resistance value can be obtained by applying a heat treatment at about 00 ° C. In any case, unlike tungsten silicide, high temperature heat treatment of 800 ° C. or higher is not required.

Also in this second embodiment, as shown in FIG. 17 by the predetermined set temperature in the heat treatment process after the film formation process.
As can be seen from the graph showing the relationship between the heat treatment temperature (° C.) of tungsten silicide and titanium silicide and the specific resistance (μΩm), the resistance of titanium silicide can be reduced. Since the heat treatment at this time is performed at a lower temperature than in the case of tungsten silicide,
Even during the processing at the predetermined temperature, the diffusion of impurities in the source / drain regions 9 and 9 and the impurity region 13 can be suppressed to a relatively small scale.

As described above, by using this structure and the manufacturing method, it is possible to obtain the same effects as those of the DRAM of the first embodiment.

In each of the above embodiments, the present invention is applied to the DRAM.
However, the structure is not limited to this structure, and the first wiring layer including the impurity region and the first refractory metal silicide layer formed before the impurity region, and the first wiring layer A second refractory metal silicide method formed after the impurity region via an insulating film between the second refractory metal layer and the second refractory metal silicide method;
It is generally applicable to a wiring layer of a semiconductor device having a structure including a wiring layer.

Further, when the silicide layer is formed in the first and second embodiments, the CVD method is used. However, the present invention is not limited to this method, and the sputtering method may be used. It is possible to form a silicide layer and reduce the resistance of this silicide.

Although the heat treatments described so far have been described only for the purpose of silicidation and reduction of resistance thereof, an interlayer flattening film (for example, B
The heat treatment for the purpose of planarization reflow of (PSG) also affects the resistance value of the silicide. In this case, for example, in the case of a DRAM having a buried bit line structure, if titanium silicide is used for the bit line, a heat treatment for reflow is 800.
If the temperature is required to be ° C, the resistance of the bit line is sufficiently lowered, and it can also serve as a heat treatment for low resistance silicidation. On the other hand, if tungsten silicide is used for the bit line, 800 ° C. is sufficient for the reflow, but a higher temperature treatment is desired for the bit line resistance, and impurity diffusion in the impurity region cannot be avoided. Further, although the above description has described only the process of lowering the resistance of silicidation and the heat treatment temperature for silicidation, a higher temperature treatment is required as the second layer wiring silicide than the first layer silicide. The material may be such that resistance reduction and silicidation are completed in a short time, and consequently diffusion of impurities is suppressed.

[0069]

According to the semiconductor device and the method of manufacturing the same according to the present invention, the second wiring layer formed after the impurity region has a lower temperature than the first wiring layer formed before the impurity region. It is formed by heat treatment and has low resistance. Therefore, during the heat treatment for forming the second wiring layer, the diffusion of the impurities in the impurity regions formed in the semiconductor substrate into the semiconductor substrate is relatively suppressed, so that the impurity region is not expanded during the heat treatment. It can be suppressed. As a result, when applied to a DRAM or the like, it is possible to prevent punch-through and single channelization due to the expansion of the impurity region, and it is possible to improve the reliability of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a plan structural view of a memory cell of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional structural view from a direction along a cutting line AA in FIG.

3 is a first diagram showing a manufacturing process of the memory cell shown in FIG. 2;
It is a process drawing.

FIG. 4 is a second view showing a manufacturing process of the memory cell shown in FIG.
It is a process drawing.

FIG. 5 is a third process showing the manufacturing process of the memory cell shown in FIG.
It is a process drawing.

FIG. 6 is a fourth process showing the manufacturing process of the memory cell shown in FIG.
It is a process drawing.

FIG. 7 is a fifth process showing the manufacturing process of the memory cell shown in FIG.
It is a process drawing.

FIG. 8 is a sixth view showing a manufacturing process of the memory cell shown in FIG.
It is a process drawing.

9 is a seventh step showing the manufacturing process of the memory cell shown in FIG.
It is a process drawing.

10 is an eighth process chart showing the manufacturing process of the memory cell shown in FIG. 2. FIG.

FIG. 11 is a ninth process chart showing the manufacturing process of the memory cell shown in FIG. 2;

FIG. 12 is a tenth process chart showing the manufacturing process of the memory cell shown in FIG. 2;

FIG. 13 is an eleventh process chart showing a manufacturing process of the memory cell shown in FIG. 2;

FIG. 14 is a twelfth process chart showing the manufacturing process of the memory cell shown in FIG. 2;

FIG. 15 is a thirteenth process diagram showing the manufacturing process of the memory cell shown in FIG. 2;

16 is a fourteenth process diagram showing the manufacturing process of the memory cell shown in FIG. 2. FIG.

FIG. 17 is a diagram showing a relationship between a heat treatment temperature and specific resistance of tungsten silicide and titanium silicide.

FIG. 18 is a sectional structural view of a memory cell of a DRAM according to a second embodiment of the present invention.

FIG. 19 is a plan view of a memory cell of a conventional DRAM.

20 is a cross-sectional structural view taken along the line AA in FIG.

FIG. 21 is a first process chart showing the manufacturing process of the memory cell shown in FIG. 20.

22 is a second process chart showing the manufacturing process of the memory cell shown in FIG. 20. FIG.

FIG. 23 is a third process chart showing the manufacturing process of the memory cell shown in FIG. 20.

FIG. 24 is a fourth process chart showing the manufacturing process of the memory cell shown in FIG. 20.

FIG. 25 is a fifth process chart showing the manufacturing process of the memory cell shown in FIG. 20.

FIG. 26 is a sixth process chart showing the manufacturing process of the memory cell shown in FIG. 20.

FIG. 27 is a seventh process chart showing the manufacturing process of the memory cell shown in FIG. 20.

FIG. 28 is an eighth process chart showing the manufacturing process of the memory cell shown in FIG. 20.

FIG. 29 is a ninth process chart showing the manufacturing process of the memory cell shown in FIG. 20;

FIG. 30 is a tenth process chart showing the manufacturing process of the memory cell shown in FIG. 20;

FIG. 31 is an eleventh process chart showing a manufacturing process of the memory cell shown in FIG. 20.

FIG. 32 is a twelfth process chart showing the manufacturing process of the memory cell shown in FIG. 20.

FIG. 33 is a thirteenth process step showing the manufacturing process of the memory cell shown in FIG. 20.

FIG. 34 is a fourteenth process diagram showing the manufacturing process of the memory cell shown in FIG. 20.

FIG. 35 is a sectional structural view showing a problem of a memory cell in the conventional technique.

[Explanation of symbols]

 1 semiconductor substrate 2 field oxide film 3 gate insulating film 4,17 polysilicon layer 5 tungsten silicide 6,10,14,19 insulating layer 7,11,15,20 resist film 8,12 impurity 9 source / drain region 13 impurity region 16 Contact Hole 18 Titanium Silicide 23a Storage Node (Flat Part) 23b Storage Node (Standing Wall) 25 Dielectric Film 26 Cell Plate (Upper Electrode) 27, 29 Interlayer Insulating Film 28 Wiring Layer 30 Gate Electrode 40 Bit Line 100 Transfer Gate Transistor 200 capacitor Incidentally, the same reference numerals in the drawings indicate the same or corresponding portions.

Claims (4)

[Claims] 1. A semiconductor substrate, an impurity region formed in the semiconductor substrate, a first wiring layer including a first refractory metal silicide layer provided on the semiconductor substrate via an insulating film, A second wiring layer including a second refractory metal silicide layer provided between the first wiring layer and an insulating film, and the second refractory metal silicide layer includes: A wiring layer of a semiconductor device, which is made of a material whose resistance is lowered by heat treatment at a temperature lower than that of the first refractory metal silicide layer or for a short time. 2. The first refractory metal silicide layer comprises:
The wiring layer of a semiconductor device according to claim 1, wherein the wiring layer is made of tungsten silicide, and the second refractory metal silicide layer is made of titanium silicide. 3. A first substrate is formed on the semiconductor substrate via an insulating film.
Forming a first wiring layer including a first refractory metal silicide layer having a low resistance at the temperature of 1) through a heat treatment at the first temperature, and after forming the first wiring layer, A step of introducing an impurity into the surface of the semiconductor substrate to form an impurity region; and, after forming the impurity region, an insulating film is provided between the impurity region and the first wiring layer, and the temperature is higher than the first temperature. A wiring layer of a semiconductor device, comprising: forming a second wiring layer including a second refractory metal silicide layer having a low resistance at a low second temperature, through a heat treatment at the second temperature. Manufacturing method. 4. The first wiring layer is tungsten silicide, the second wiring layer is titanium silicide, the first temperature is 900 to 1100 ° C., and the second temperature is Is 600 to 800 ° C. 4. The method of manufacturing a wiring layer of a semiconductor device according to claim 3.