JPH06175860A - Microprocessor application device - Google Patents

Abstract

(57) [Summary] [Purpose] To ensure that processing requests can be made within a short time. [Structure] A plurality of circuits that output INT signal and status (ST) are connected in a daisy chain during an interrupt (INT) cause occurrence period, and the priority level (PY) of INT is increased toward the upstream side, and these circuits are higher IN
In a device in which the lower INT is held by T, and the CPU3 performs INT processing by the INT signal, the CPU3 receives the highest INT and outputs a command to generate a mask signal (MSK). ST is checked from the upper PY, and for a circuit with an INT generated ST, a means for performing the processing routine (RT) specified for that circuit according to PY, and when each predetermined RT for all circuits with an INT generated is finished, the MSK is released. Directive (CM
D) and means to release INT, and means to generate MSK until receiving CMD when receiving MSK generation command 10
c, means to delay the MSK's INT release processing time
10a, circuit to pass delayed MSK and INT signal of each circuit 10
Provide means 10 with b and.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor application device which enables control of data transfer by interruption in a short time and is optimal for use in a data terminal connection device or the like.

[0002]

2. Description of the Related Art Electronic exchanges, such as private branch exchanges (PBs)
In X), internal data transmission is performed by 64 KBPS serial transmission, while when data communication is performed by the data terminal using the telephone network, the data terminal uses a standard serial input / output interface. 4800 BPS
Since data is transmitted and received at a transmission rate of 9600 BPS, a data terminal connection device is used as an interface between the two. That is, the data terminal is connected to the PBX via the data terminal connection device to perform data communication.

By the way, the conventional data terminal connection device has a structure as shown in FIG. As shown in the figure, the data terminal connection device 1 includes a communication unit 2, a central processing unit (CPU; microprocessor) 3, a ROM 4, a RAM 5 as a data buffer, an input / output interface for serial communication (hereinafter, SIO (Serial I / O Controller)) 6
And 7, a direct memory access controller (hereinafter, referred to as DMA) 8 for supporting efficient serial transfer, a driver / receiver 9 for interfacing with a terminal, and the like. And these are mutually connected on the common bus. The driver / receiver 9 transmits the serial data output from the SIO 7 to the data terminal side, receives the data from the data terminal side, and inputs the data to the SIO 7.

The CPU 3 is responsible for overall control,
The program stored in the ROM 4 is executed for control. The communication unit 2 is for exchanging data with the PBX.

The RAM 5 is a memory for temporarily storing data, and the RAM 5 directly accesses the RAM 5 by accessing an address in a specified range by the DMA 8. The DMA 8 receives the access start address and the range information from the CPU 3, and upon receiving the access start command, controls the RAM 5 for direct memory access based on the information. This direct memory access control is normally performed by using the interval between CPU bus accesses.

SIOs 6 and 7 are serial communication interface LSIs that convert serial data (serial data) into parallel data (parallel data) and take in it, and convert parallel data into serial data and output it. As the SIOs 6 and 7, here, as an example, the SIO LSI of the Z80 family (Z80 series peripheral LSI chip), which is an 8-bit microprocessor family.
And so on. The SIO 6 is for converting the serial data received by the communication unit 2 into parallel data and transmitting the parallel data to the bus, and converting the parallel data on the bus into serial data and transmitting the serial data to the communication unit 2. The SIO 7 is for data transmission / reception, and the SIO 7 converts the serial data received and output by the driver / receiver 9 from the data terminal side into parallel data and sends the parallel data to the bus, and converts the parallel data on the bus into serial data. For transmitting to the driver / receiver 9 and for exchanging data with the data terminal side.

These SIOs 6 and 7 are connected in a daisy chain. In other words, the Z80 family of chips enables a connection method called a daisy chain in order to easily control interrupts according to the priority order of interrupts. If some of these chips have interrupt requirements, the upstream chip will have its own IEO
Set the (Interrupt Enable Output) terminal to “L” to disable the interrupt request from the chip on the downstream side, and generate the interrupt signal INT and C
It is given to PU and interrupted.

IEI (Interrupt
It has an Enable Input) terminal and an IEO terminal and connects the IEO terminal of the upstream chip and the IEI terminal of the downstream chip is called a daisy chain. If the IEI pin is "H", the interrupt request is enabled, and if it is "L", the interrupt request cannot be issued. As a result, the priority of interrupts can be determined only by the wiring order. While its own interrupt is accepted by the CPU and its processing is being performed, an interrupt request of a higher priority than itself is issued by the CPU.
If so, the CPU of the Z80 system sets the IEI of the chip in the daisy chain connection to "L", so that the peripheral LSI side of the Z80 system can know this.

The interrupt request to the CPU is maskable. When the SIO interrupt signal (/ INT; / indicates negative logic active) is input to the interrupt signal input terminal INT of the CPU3, and the SIO 6 and 7 receive or send data , SIO issues an INT interrupt to the CPU 3 and sends an interrupt vector.

Therefore, in order to enable the data transfer, as shown in FIG. 7, the SIO interrupt signal (/ INT;
However, / indicates negative logic active) is input to the interrupt signal input terminal INT of the CPU3. Then, when the SIOs 6 and 7 receive and send data, the SIO is made to perform an INT interrupt which is a maskable interrupt to the CPU 3. CP
U3 determines the type of interrupt based on this vector, and DM
In order to start data transfer to A8, the next frame address is read and a frame is set to set conditions.

In such a configuration, the transmission data from the PBX to the data equipment is received and controlled by the communication section 2 under the control of the CPU 3 and input to the SIO 6. S
When the received data is given to IO6, SIO6 becomes CPU
An interrupt signal INT is generated for 3 and C
When PU3 finishes the processing currently being executed, this SIO
Accept interrupt by 6. In response to this interrupt, all the SIOs are notified that the interrupt has been accepted.

Then, since a predetermined vector (the start address of the interrupt processing program) corresponding to the interrupt level is generated from the SIO 6 which requested the interrupt, C
PU3 will execute the address corresponding to this vector. The address determined by this vector is, for example, R
The address on the OM4, and the address area on the ROM4 is, for example, S by direct memory access.
If a processing routine (transfer instruction) for instructing the storage of the IO6 output in the RAM 5 is programmed,
The SIO6 output will be stored in the RAM5 by the DMA8.

Since the SIO 6 converts the received data obtained by the communication unit 2 into parallel data and outputs it on the bus, this parallel data is stored in a predetermined area of the RAM 5. When the reception of the communication unit 2 ends and the parallel data output of the SIO 6 ends, the cause of the interrupt disappears. Therefore, the interrupt signal I from the SIO 6
NT will disappear.

Next, the CPU 3 transfers the stored data by direct memory access so that the DMA 8 stores the start address of the data to be transferred,
The area data is set, the DMA8 is activated, and RA
Direct reading of the data to be transferred and SI in M5
Instruct to send to O7 (transfer instruction).

As a result, the SIO 7 converts the transferred data into serial data, and the driver / receiver 9
Then, the driver / receiver 9 sends this data according to the receiving speed of the data equipment.

Since the transfer by the DMA 8 is performed in the interval between the operations of the CPU 3, when the transfer instruction to the DMA 8 is completed, the CPU 3 restarts the process for the routine next to the execution routine before the interruption.

The data transmitted from the data device is the driver /
SIO7 is sent to the receiver 9 and the reception is controlled there.
Sent to. When the received data is given to SIO7, S
The IO7 generates an interrupt request signal INT to the CPU3, whereby the CPU3 accepts the interrupt by the SIO7 at the time when the currently executed process is completed. In response to this interrupt, all the SIOs are notified that the interrupt has been accepted.

Then, a predetermined vector corresponding to the interrupt level is generated from the SIO 7 which requested the interrupt, so that the CPU 3 executes the address determined by this vector.

The address determined by this vector is the address on the ROM 4 as described above, and in the address area on the ROM 4, for example, a processing routine for instructing the transfer of the SIO 7 output to the RAM 5 by direct memory access is provided. If it is programmed, the DMA8 operates according to this instruction and the SIO7 output is stored in the RAM5 by direct memory access.

The SIO 7 converts the received data into parallel data and outputs it on the bus. When the reception of the driver / receiver 9 is completed and the parallel data output of the SIO 7 is completed, the CPU 3 next issues a transfer instruction to transfer the stored data by direct memory access, and DMA
The start address in which the data to be transferred is stored and the data in the area are set in 8, and the DMA 8 is activated. As a result, the DMA 8 directly reads the data to be transferred from the RAM 5 and sends it to the SIO 6.
The SIO 6 converts the transferred data into serial data and sends the serial data to the communication unit 2. The communication unit 2 sends this data according to the reception speed of the data device.

At the time when the transfer instruction itself to the DMA 8 is completed, the CPU 3 performs processing for ending the interrupt (returning from the interrupt), and then restarts the continuation of the previous execution routine which was interrupted by the interrupt again. .

In this way, buffering and PB
Data is exchanged between X and the data device, but HDL
When data transmission is performed based on a communication rule such as C (High Level Data Link Control), as shown in FIG. There is only one flag (one byte) for a short time, but during that time, it is necessary to finish the transfer instruction of the next received data.

Even if the margin time is very short, such as about one flag, there is no problem if the transfer instruction is immediately issued by the interrupt prior to the data reception of the next frame. Is a maskable interrupt (INT interrupt), if the highest interrupt request is received before the end of the transfer instruction, this is given the highest priority for processing, and then executed before the highest priority interrupt. Since the transfer instruction program, which is the lower-order interrupt processing program, is restarted, the flag transmission period ends when the transfer instruction ends. Then, if such a situation occurs, the reception and transfer cannot be performed in time, which causes a situation of data loss.

[0024]

As described above, in an apparatus that provides an interface for exchanging data between the PBX and the data equipment, the PBX and the data equipment exchange data as serial data. Therefore, inside the interface, serial data is converted to parallel by SIO and stored in the memory in the form of parallel data, and the stored data is read by DMA and transmitted to the other party to be transferred to SIO.
It is converted into serial data via and sent out. To simplify the priority control (priority) of interrupts, use the Z80 family as SIO to connect in a daisy chain, generate a maskable interrupt request (INT) from the SIO that generated the interrupt requirement, and execute the transfer instruction to the CPU. Therefore, if NMI, which is the highest interrupt request, occurs in the CPU, if the interval between serial data frames is short, the next frame data will arrive before the next transfer instruction is issued. Received data will be lost.

Therefore, the object of the present invention is to
A processor that can reliably perform a request for processing that must be executed during a short margin time such as frame transmission in the HDLC mode to solve problems such as data loss To provide an application device.

[0026]

In order to achieve the above object, the present invention is configured as follows. That is, it has a plurality of circuits that generate an interrupt signal over the period of generation of an interrupt cause, and these circuits are daisy-chained so that the interrupt priority becomes higher toward the upstream side. Generates an interrupt status when an interrupt cause occurs, generates an interrupt signal, and holds a lower interrupt when there is an upper interrupt, and suppresses the generation of the interrupt signal. In the microprocessor application device, which is configured to cause the microprocessor to perform interrupt processing, when the microprocessor receives the highest interrupt, a mask signal for masking the highest interrupt. The means of commanding the generation and the reception of this highest-level interrupt And a means for checking the status of each circuit in order from the highest priority, and for a circuit having an interrupt generation status, a means for carrying out a predetermined processing routine predetermined for the circuit according to the priority, When a predetermined processing routine for all circuits having an interrupt generation status is completed, a mask signal release command is provided and means for performing processing for interrupt release is provided.
Further, until the mask signal generation command is received and until the cancellation command is received, the generation means for generating the mask signal and the generated mask signal are required for at least the microprocessor to perform the processing for canceling the interrupt. Multiple interrupt regulating means having delay means for delaying by time and gate means for passing the mask signal obtained through the delay means and the interrupt signal of each circuit is provided.

[0027]

In such a structure, when an interrupt signal is generated from a circuit that is daisy-chained to generate an interrupt, this signal is sent to the microprocessor through the gate means of the multiple interrupt control means to request the highest interrupt. Is entered as. When the microprocessor receives the highest interrupt, it issues a mask signal generation command for masking the highest interrupt, and when the highest interrupt is received, the status of each of the above circuits is set to a higher priority. The check is sequentially performed from the order, and for a circuit having an interrupt generation status, a predetermined processing routine predetermined for the circuit is executed according to the priority order.

On the other hand, the multiple interrupt control means receives the mask signal generation command, generates a mask signal, and causes the delay means in the multiple interrupt control means to perform at least the processing of the mask signal by the processor for releasing the interrupt. The time required is delayed and given to the gate means.
Therefore, the interrupt signal input to the gate means is masked by this mask signal, and even if there is a newly generated interrupt signal, it is masked and is not input to the processor. In response to the highest interrupt request, the processor executes the predetermined processing routines for all the circuits with interrupt generation status in order of priority, and when they are all completed, the mask signal is released and the processing for interrupt release (from the interrupt Perform processing for restoration).

Even if the mask signal is released by the multiple interrupt control means, it is delayed by the time required for the processor to perform the processing for releasing the interrupt.
You can stop accepting the highest interrupt. A daisy chainable circuit that generates an interrupt request, for example,
The roles of the Z80 peripheral chips (SIO, PIO, CTC, etc.) are fixed, and when an interrupt cause occurs, these chips output status information, so you can check which interrupt request it is by checking this status. Therefore, by determining the jump destination and the processing routine according to the interrupt request found as a result, it is possible to perform the necessary processing for each interrupt, and also before the processing for ending the interrupt. The status check checks the lower interrupts of the chip to perform interrupt processing, and after the processing of all interrupts that have occurred in the daisy chained chips is completed, the processor is made to perform processing for interrupt completion, It is possible to minimize the delay for processing the pending interrupt.

Therefore, according to the present invention, in the case where only a short margin time can be secured such as frame transmission in the HDLC mode, if the interrupt processing such as the transfer instruction by the DMA must be executed during this period, This can be surely done, and problems such as data loss can be solved.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG.
Is a communication unit 2, a central processing unit (CPU) 3, a ROM 4, a RAM 5 which is a data buffer, an input / output interface (hereinafter referred to as SIO) 6 and 7 for serial communication, and supports for efficiently performing serial transfer. Direct memory access controller (hereinafter DM
8), a driver / receiver 9 for interfacing with a terminal, and the like. And these are mutually connected on the common bus. The driver / receiver 9 transmits the serial data output from the SIO 7 to the data terminal side, receives the data from the data terminal side, and inputs the data to the SIO 7.

The CPU 3 is responsible for overall control,
The program stored in the ROM 4 is executed for control. The communication unit 2 is for exchanging data with the PBX.

SIOs 6 and 7 are serial communication interface LSIs, which convert serial data (serial data) into parallel data (parallel data) and convert parallel data into serial data for output. SIO 6,7
As an example, a family SIO LSI in the Z80 which is an 8-bit microprocessor is used here. The RAM 5 is a memory for temporarily storing data, and the RAM 5 directly accesses the RAM 5 by accessing an address in a designated range by the DMA 8.

The DMA 8 receives information such as an access start address and a range from the CPU, and upon receiving an access start instruction, controls the RAM 5 for direct memory access based on the information. The SIO 6 is for converting the serial data received by the communication unit 2 into parallel data and transmitting the parallel data to the bus, and converting the parallel data on the bus into serial data and transmitting the serial data to the communication unit 2. The SIO 7 is for data transmission / reception, and the SIO 7 converts the serial data received and output by the driver / receiver 9 from the data terminal side into parallel data and sends the parallel data to the bus, and converts the parallel data on the bus into serial data. For transmitting to the driver / receiver 9 and for exchanging data with the data terminal side.

The non-maskable interrupt signal input terminal NMI, which is the highest interrupt in the CPU 3, receives an SIO interrupt signal (/ INT; where / is a negative logic) via the multiple interrupt control circuit 10 for controlling the NMI interrupt. (Indicating active) is input, and when the SIOs 6 and 7 receive and send data, the SIO issues an NMI interrupt to the CPU 3.

Although this apparatus is basically the same as the conventional circuit shown in FIG. 6, a multiple interrupt control circuit 10 for controlling the control of multiple interrupts is provided to this conventional circuit in order to perform an NMI interrupt. The difference is that the CPU 3 side has a function of checking the status of each SIO 6, 7 by an NMI interrupt and specifying which interrupt based on the status, and a mask signal generation control function by receiving an NMI interrupt.

The multiple interrupt control circuit 10 includes a delay circuit 10a for delaying the interrupt mask control signal, as shown in FIG.
An OR gate 10b for logically adding the output of the delay circuit 10a and the interrupt request signal INT output by the SIO 6, 7 to the CPU 3 as a non-maskable interrupt signal (NMI signal), and further mask signal generation control from the CPU 3. It is composed of a mask signal output circuit 10c which controls generation of an interrupt mask control signal by output.

The interrupt mask control signal is a signal generated when the CPU 3 inputs an interrupt signal (NMI signal) to its own non-maskable interrupt terminal INT until the interrupt signal disappears by software processing. In this case, since the NMI signal is "L", the interrupt mask control signal is "H".

In this embodiment, the NMI signal is SIO6.
The interrupt signal of No. 7 is used as it is, and the interrupt mask control signal is used for the CPU from the time the NMI interrupt is requested until the processing of the NMI interrupt is completed.
3 is generated by the mask signal output circuit 10c in response to software processing, and this is delayed by the delay circuit 10a and given to the OR gate 10b.
It will be slightly behind the interrupt signal INT of 7.

When an NMI interrupt is performed by an interrupt request from a Z80 family SIO connected in a daisy chain, the upstream interrupt becomes an upper interrupt, so if an upper interrupt occurs while processing a lower interrupt,
It becomes a multiple interrupt of NMI. Since the NMI interrupt is the highest interrupt, if multiple NMI interrupts occur, it is impossible to return to the NMI interrupt processing interrupted by this interrupt.
It is necessary to perform restriction control of multiple interrupts, and the circuit for that purpose is the multiple interrupt restriction circuit 10.

For example, when the CPU receives an NMI interrupt request during the normal INT interrupt processing, the NMI is forcibly forced.
It will start interrupt processing. If an NMI interrupt further enters during this NMI interrupt processing (NMI multiple interrupt), the CPU cannot return from the processing by this NMI interrupt to the previous NMI interrupt processing that was in the process of processing. Therefore, if an NMI interrupt occurs once,
It is necessary to mask so that the next NMI interrupt request does not come in. The circuit for performing this mask is the OR gate 10b in the multiple interrupt control circuit 10 of FIG.

The reason why the delay circuit 10a is provided in the multiple interrupt control circuit 10 is as follows. That is, the MNI mask target is set by software. Therefore, when the interrupt processing is canceled and the original routine is restarted after mask cancellation,
Z80 CPU instructions such as POP (extract information from stack to register), PUSH (save register information to stack), RETURN (return; transition from interrupt processing routine to execution routine before interrupt) Will need to be performed.

Therefore, if an NMI interrupt occurs during these executions, it cannot be controlled. To prevent this, a mask generation control instruction is issued from the CPU 3 during the interrupt processing period, and a mask signal is issued. It is given to the output circuit 10c and controlled to generate an interrupt mask control signal. After unmasking this, when restarting the original routine when interrupt processing is cancelled, by delaying by the amount of time required to execute the instructions that need to be executed by the Z80 CPU, it is given to the OR gate 10b. The interrupt of is masked by being extended to this period so that the operation of the CPU 3 is not hindered.

That is, in a normal INT interrupt
RETI (Return from interrupt; Interrupt release; Z80 family chip (Z80 peripheral LSI) is designed to detect this instruction code and to know that the interrupt processing routine has ended. Time to execute (shortened) (1 instruction)
Has the same function as masking so that interrupts cannot be entered. Next, the actual operation will be described with reference to FIGS. 3 and 4. Since the basic operation has been described in the related art, the characteristic part of the present invention will be described.

Interrupts of SIO 6 and 7 are generally C
It is usually connected to the interrupt input terminal INT of PU3. In this case, the CPU3 issues an interrupt acknowledge cycle (interrupt enable cycle; both IORQ and M1 of the Z80 CPU are L; IORQ is a signal indicating that the correct I / O address is output to the address bus, and M1 (machine cycle When it is output together with the signal indicating that it is the fetch cycle of the operation code), it indicates that it is the interrupt response cycle), the vector determined for each interrupt type is output, and the INT signal changes from “L” to “L”. Change to H ".

However, when the interrupts of SIO6, 7 are applied to the non-maskable interrupt input terminal NMI of the CPU 3 as in the present device, the interrupt acknowledge cycle is not returned from the CPU 3, so the SIO 6,
7 does not send an interrupt vector. Also, the INT signal does not change from "L" to "H" until the cause of the interruption is eliminated. Therefore, in the present apparatus, when an NMI interrupt is input, the CPU 3 monitors the status of the SIOs 6 and 7 and sets up a processing routine so as to judge the interrupt. An example of a processing routine for that purpose is shown in FIG.

The flowchart in FIG. 5 is as follows.
That is, when an NMI interrupt is input from SIO, the CPU
3 sets the MNI mask (S1), and then checks the interrupt status of each SIO 6,7 (S2). Then, it is checked whether it is the interrupt A (S3), and if it is the interrupt A,
Perform NMI interrupt processing for A interrupt (S
Four).

Next, it is checked whether or not there is another interrupt (S5), if not, the mask is released (S6), the processing routine by the interrupt is exited, and the process returns to the main routine (S7). If there is another interrupt in S5, the process returns to S2 to check the interrupt status (S2). Then, it is checked whether it is an interrupt A (S3).
I interrupt processing is executed (S4).

If it is not the interrupt A, it is checked whether it is the interrupt B (S3b), and if it is the interrupt B, the NMI interrupt processing for the interrupt of B is executed. Interrupt B
If it is not, it is checked whether it is the interrupt C (S3c). If it is the interrupt C, the NMI interrupt processing for the interrupt of C is executed.

After that, S5 is checked, and the above steps are performed thereafter.
Performs operations after S5. Since the roles of the SIOs 6 and 7 are determined, if the jump destination and the processing routine are determined depending on which interrupt is known as a result of the status check, the required processing can be performed for each interrupt. Moreover, since the lower level interrupts of SIO 6 and 7 are checked by the status check before the processing for ending the interrupt and the interrupt processing is executed, the delay with respect to the processing of the pending interrupt can be minimized. become able to. FIG. 3 shows an example in which only one interrupt request occurs without duplication.

The multiple interrupt control circuit 10 changes from SIO to INT.
Since the signal is generated, the INT signal is used as an NMI interrupt request from the OR gate 10b and the NMI of the CPU 3 is requested.
Input to the terminal.

As a result, the CPU 3 accepts the NMI interrupt request, and the predetermined address in the memory area (38h in the Z80 system).
Address; h indicates hexadecimal notation), and the program at this address (processing routine as shown in FIG. 5) is executed. Therefore, the necessary transfer instruction program can be executed for this interrupt, and the transfer instruction can be given the highest priority.

Further, in this case, the multiple interrupt control circuit 10 changes the interrupt mask control signal from "L" to "H", delays this for the time required for canceling the processing of the NMI interrupt, and masks INT. However, this prevents the next NMI interrupt. That is, the next NMI interrupt request is prohibited during the masking period.

Thus, the NMI to be executed by the CPU 3
The interrupt processing routine is as shown in FIG.
SIO during the processing period for the interrupt currently being processed
If there is a newer interrupt, the CPU 3 goes to the status after the completion of the interrupt process during the process, so that the presence or absence of a new interrupt can be determined.

If no new interrupt is generated by the SIO during the above period, the INT signal of the SIO is changed from "L" to "H". Therefore, even after the mask is released, that is, the control signal is "H". The NMI signal is "H" even after changing from "L" to "L".

Next, as shown in FIG. 4, it is assumed that an interrupt request is input from the SIO 6, 7 where the mask is released and RETURN is performed after the presence or absence of a new interrupt is determined. In this case, the software cannot normally find the interrupt request as it is.

However, in the multiple interrupt control circuit 10 of the present invention, since the interrupt mask control signal changes from "H" to "L" as the NMI mask is released, the output of the OR gate 10b changes from "H" to "L". ", So that an NMI interrupt request is input to the CPU 3 by hardware. Then, as a result of this, the CPU 3 enters the above-described processing, so that the necessary interrupt processing can be performed.

S connected in the daisy chain as described above
The interrupt request from the IO is used as an NMI interrupt to the CPU, and a circuit for masking the NMI interrupt is provided so that when the NMI interrupt is received, the NMI interrupt is masked until the processing is completed. When an interrupt is received, the interrupt request status of the SIO is checked to see which one is issuing the interrupt request. And SI that is giving status
Since it is possible to determine the interrupt to be processed depending on which is O, it is possible to enter the necessary interrupt processing by the MNI interrupt. Then, the S with the interrupt request
Of the IOs, a predetermined interrupt process determined by the SIO is sequentially executed from the higher order IO, and after all the interrupt requests are satisfied, the NMI interrupt is released. Therefore, if it is said that the processes of the order of DMA transfer for each SIO are sequentially performed, it is possible to sufficiently implement all of these processes within a short margin time during data transmission such as HDLC.

As described above, in this apparatus, the SIO interrupt is processed by the NMI which is the highest priority interrupt, the mask control is performed so that the NMI does not make multiple interrupts, and the interrupt by the NMI is the upper S.
Check the status in order from IO to know what kind of interrupt it is, execute the necessary processing in order from the higher order, and after all the interrupts generated from each SIO have been processed, Since the processor is made to perform the procedure for ending the process, the CPU can execute the DMA for data transfer even if the interrupt processing time is short.
I can deal with the instructions enough.

Therefore, in the case where only a short margin time can be secured such as frame transmission in the HDLC mode, it becomes possible to reliably carry out interrupt processing such as a transfer instruction which must be executed during this time in accordance with the interrupt request. It becomes possible to solve problems such as missing.

The present invention is not limited to the embodiments described above and shown in the drawings, but can be appropriately modified and implemented without departing from the scope of the invention. For this NMI interrupt, in addition to SIO, the Z80 microprocessor peripheral chip CTC (Counter Timer Circuit) and DM
A (Direct Memory Access) and PIO (Parallel I / O Cont)
You can use the same for interrupts such as roller).

[0062]

As described above in detail, according to the present invention, when a short margin time can be secured, such as in frame transmission in the HDLC mode, an interrupt request that must be executed during this time is issued as an interrupt request. According to the above, it is possible to provide a processor application device that can be surely performed and can solve problems such as data loss.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a multiple interrupt control circuit in FIG.

FIG. 3 is a timing chart for explaining an operation example of the device of the present invention.

FIG. 4 is a timing chart for explaining an operation example of the device of the present invention.

FIG. 5 is a flowchart for explaining an operation example of the device of the present invention.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a block diagram showing a conventional example.

FIG. 8 is a diagram showing an example of a transmission frame of data transmission by HDLC.

[Explanation of symbols]

2 ... Communication unit 3 ... CPU 4 ... ROM 5 ... RAM 6, 7 ... SIO 9 ... Driver /
Receiver 10 ... Multiple interrupt control circuit 10a ... Delay circuit 10b ... OR gate 10c ... Mask signal output circuit.

Claims (1)

[Claims] 1. A circuit having a plurality of circuits for generating an interrupt signal during a period of generation of an interrupt cause, the circuits being daisy-chained so that the interrupt priority becomes higher toward the upstream side. , These circuits generate an interrupt generation status when the cause of an interrupt occurs, generate an interrupt signal, and hold a lower interrupt when there is an upper interrupt and suppress the generation of the interrupt signal. In the microprocessor application device that is made to perform interrupt processing by giving the interrupt signal to the microprocessor, when the microprocessor receives the highest interrupt, the highest interrupt is masked. And the means for instructing the mask signal generation of Then, the status of each circuit is checked in order from the highest priority, and for a circuit having an interrupt generation status, a predetermined processing routine for the circuit is executed in accordance with the priority. , A means for performing a mask signal cancel command and a process for canceling an interrupt when each predetermined processing routine for all circuits having an interrupt occurrence status is completed, and when the mask signal generation command is received, a cancel command is issued. Until receiving, a generating means for generating a mask signal, a delay means for delaying the generated mask signal for at least a time required for the microprocessor to perform processing for releasing the interrupt, and a delay means via the delay means. Means for passing the mask signal obtained as a result and the interrupt signal of each circuit Microprocessor application device, characterized in that which is configured by providing multiple interrupts regulating means having a.