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JPH06163628A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH06163628A
JPH06163628A JP4311635A JP31163592A JPH06163628A JP H06163628 A JPH06163628 A JP H06163628A JP 4311635 A JP4311635 A JP 4311635A JP 31163592 A JP31163592 A JP 31163592A JP H06163628 A JPH06163628 A JP H06163628A
Authority
JP
Japan
Prior art keywords
wiring
integrated circuit
substrate
semiconductor substrate
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4311635A
Other languages
Japanese (ja)
Inventor
Minoru Taguchi
実 田口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP4311635A priority Critical patent/JPH06163628A/en
Publication of JPH06163628A publication Critical patent/JPH06163628A/en
Pending legal-status Critical Current

Links

Classifications

    • H10W72/90
    • H10W72/283
    • H10W72/5522
    • H10W74/00
    • H10W90/756

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To protect a monolithic micro wave integrated circuit front the adverse effect in a resin forming process. CONSTITUTION:On a surface of a semiconductor substrate 1, a wiring 2 and an air bridge wiring 3 are formed, and, directly under the wiring 2, a through hole 4, penetrating up to the rear surface of the substrate 1, is formed. A wiring 5 and a bonding pad 6, electrically connected to the wiring 2 through the through hole 4, are provided on the rear surface. A guard ring 7 and a cap metal 8 that protect the surface of the substrate 1 are provided. The bonding pad 6 an the rear surface is, by way of a banding wire 9, connected to a lead frame 10. The entire semiconductor is resin-sealed up with a plastic package. With this, degradation of high frequency performance, AC performance, yield, characteristics fluctuation, and moisture resistance are prevented, for improved free degree in wiring design.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体集積回路に関
し、特に高周波分野で使用される半導体集積回路に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit used in the high frequency field.

【0002】[0002]

【従来の技術】近年、半導体技術の進歩が著しく、微細
化技術あるいは自己整合技術などのプロセス技術がその
進歩を支えており、高周波分野においてもSiバイポー
ラやGaAs系デバイスのMMIC(モノリシックマイ
クロ波集積回路)における高速化、高機能化が進んでい
る。
2. Description of the Related Art In recent years, semiconductor technology has made remarkable progress, and process technology such as miniaturization technology or self-alignment technology is supporting such progress. Even in the high frequency field, Si bipolar and GaAs-based MMIC (monolithic microwave integration) devices have been developed. Circuits) are becoming faster and more sophisticated.

【0003】この分野での市場は、移動体通信、衛星放
送などの発展と共に急拡大してきており、コストダウン
の要求も強いため、MMICの外囲器を高価なセラミッ
クパッケージからプラスティックパッケージに移行して
いる。
The market in this field is rapidly expanding with the development of mobile communication and satellite broadcasting, and there is a strong demand for cost reduction. Therefore, the MMIC envelope is switched from an expensive ceramic package to a plastic package. ing.

【0004】このプラスティックパッケージによる樹脂
形成によって以下のような問題が発生している。
The following problems occur due to the resin formation by this plastic package.

【0005】まず、GaAs系デバイスのMMICにお
いては、インダクタンス(L)の内蔵が一般的であり、
特に高周波の場合、AC性能を維持するためにエアーブ
リッジ配線を使用しているが、プラスティックパッケー
ジで樹脂形成する際に、インダクタンスが破壊され易
く、かつ樹脂の誘電率が空気よりも大きいため、寄生容
量も増加してしまう。このような原因から、AC性能や
歩留が低下してしまう。
First, in the MMIC of a GaAs-based device, it is common to incorporate an inductance (L),
Especially in the case of high frequency, air bridge wiring is used to maintain AC performance. However, when forming a resin in a plastic package, the inductance is easily destroyed and the dielectric constant of the resin is larger than that of air. Capacity will also increase. Due to such a cause, the AC performance and the yield decrease.

【0006】また、樹脂形成時のストレスによって拡散
抵抗やトランジスタ(FET、バイポーラトランジスタ
など)などの特性変動が発生してしまう。特に変動方向
が全て同一方向に変動するのでなく、アットランダムに
変動するため、ペアー性などが悪化し、DC性能、AC
性能も悪化してまう。
Further, due to the stress at the time of resin formation, characteristic variations of diffusion resistance, transistors (FET, bipolar transistor, etc.) occur. In particular, the fluctuation directions do not all fluctuate in the same direction but fluctuate at random, so that the pairing property deteriorates, and DC performance, AC
Performance will also deteriorate.

【0007】さらに、GaAs系デバイスの場合、半導
体表面を保護する良好な絶縁膜(Siバイポーラにおけ
る熱酸化膜)が形成不可能なため、トップ保護膜を積層
化しても、外囲器をモールド化すると水分が容易にデバ
イス表面に達してしまう。このような耐湿性の低下によ
り、コロージョンや特性変動を生じてしまう。
Further, in the case of a GaAs-based device, a good insulating film (thermal oxide film in Si bipolar) for protecting the semiconductor surface cannot be formed. Therefore, even if the top protective film is laminated, the envelope is molded. Then, moisture easily reaches the device surface. Due to such a decrease in moisture resistance, corrosion and characteristic changes occur.

【0008】[0008]

【発明が解決しようとする課題】このように、従来のM
MICにおいては、プラスティックパッケージによる樹
脂形成によってAC性能や歩留の低下、特性変動の劣
化、及び耐湿性の低下によるコロージョンや特性変動の
発生などの問題があった。
As described above, the conventional M
In the MIC, there are problems such as deterioration of AC performance and yield, deterioration of characteristic variation due to resin formation by a plastic package, and occurrence of corrosion and characteristic variation due to deterioration of moisture resistance.

【0009】そこで、本発明は、この様な従来の事情に
鑑みて成されたものであり、その目的とするところは、
樹脂形成工程による悪影響を受けること無く、高周波性
能、特性変動、及び耐湿性の低下を防ぐことができる半
導体集積回路、特にモノリシックマイクロ波集積回路を
提供することにある。
Therefore, the present invention has been made in view of the above conventional circumstances, and its object is to:
It is an object of the present invention to provide a semiconductor integrated circuit, particularly a monolithic microwave integrated circuit, which can prevent deterioration of high frequency performance, characteristic variation, and moisture resistance without being adversely affected by the resin forming process.

【0010】[0010]

【課題を解決するための手段】上記目的を達成するた
め、本発明は、半導体基板表面上に形成されている集積
回路の配線直下に半導体基板裏面まで通じる貫通口が形
成され、この貫通口を介して前記集積回路の配線と電気
的に接続される配線及びボンディングパッドが半導体基
板裏面に設けられている。
In order to achieve the above object, according to the present invention, a through hole is formed just below the wiring of an integrated circuit formed on the front surface of a semiconductor substrate and communicates with the back surface of the semiconductor substrate. Wirings and bonding pads electrically connected to the wirings of the integrated circuit through are provided on the back surface of the semiconductor substrate.

【0011】さらに、本発明は、半導体基板表面上に形
成されている集積回路上に、この集積回路全面を封止す
る凹型のキャップメタルを設けている。
Further, according to the present invention, a concave cap metal for sealing the entire surface of the integrated circuit is provided on the integrated circuit formed on the surface of the semiconductor substrate.

【0012】[0012]

【作用】上記手段により、本発明は、半導体基板表面の
配線と電気的に接続される配線及びボンディングパッド
を裏面にも設け、さらにエアーブリッジ配線がされてい
る集積回路全面を封止する凹型のキャップメタルを設け
たので、インダクタンスの保護、樹脂形成時のストレス
防止、及び耐湿性の向上に効果的である。
With the above-mentioned means, the present invention provides a wiring and a bonding pad electrically connected to the wiring on the front surface of the semiconductor substrate on the back surface, and further, a concave type for sealing the entire surface of the integrated circuit having the air bridge wiring. Since the cap metal is provided, it is effective for protection of inductance, prevention of stress during resin formation, and improvement of moisture resistance.

【0013】[0013]

【実施例】以下、図面を参照しながら本発明の実施例を
説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0014】図1は、本発明の半導体集積回路の断面構
造図である。
FIG. 1 is a sectional structural view of a semiconductor integrated circuit of the present invention.

【0015】同図に示すように、半導体基板1の表面上
には配線2及びエアーブリッジ配線3がなされており、
配線2の一部分の直下には半導体基板1の裏面まで通じ
る貫通口4が形成されている。
As shown in the figure, the wiring 2 and the air bridge wiring 3 are formed on the surface of the semiconductor substrate 1.
Immediately below a part of the wiring 2, a through hole 4 is formed to reach the back surface of the semiconductor substrate 1.

【0016】そして、この貫通口4を介して、配線2と
電気的に接続される配線5及びボンディングパッド6が
裏面に設けられている。
A wiring 5 and a bonding pad 6 which are electrically connected to the wiring 2 through the through hole 4 are provided on the back surface.

【0017】また、エアーブリッジ配線3を含む半導体
基板1の表面全面を保護するためのガードリング7とキ
ャップメタル8が基板1上に設けられている。
A guard ring 7 and a cap metal 8 for protecting the entire surface of the semiconductor substrate 1 including the air bridge wiring 3 are provided on the substrate 1.

【0018】さらに、裏面に設けられたボンディングパ
ッド6が、ボンディングワイヤ9によってリードフレー
ム10と接続されている。
Further, the bonding pad 6 provided on the back surface is connected to the lead frame 10 by the bonding wire 9.

【0019】このように形成された半導体集積回路全体
が、プラスティックパッケージ11で樹脂封止されてい
る。
The entire semiconductor integrated circuit thus formed is resin-sealed in the plastic package 11.

【0020】次に、本発明の半導体集積回路の製造方法
を図2に示す工程断面図を用いて説明する。
Next, a method of manufacturing a semiconductor integrated circuit according to the present invention will be described with reference to process sectional views shown in FIG.

【0021】まず、半絶縁性GaAs基板1(〜107
Ωcm)の表面上に、GaAsMESFETプロセス、
すなわちイオン注入、アニール、CVDデポ、エッチン
グ、メタル形成などの工程を用いてMMICを形成す
る。これによってAu配線2、及び厚さ2μm、ギャッ
プ3μmからなるエアーブリッジ配線3が形成される
(図2(a))。
First, the semi-insulating GaAs substrate 1 (-10 7
Ωcm) on the surface of the GaAs MESFET process,
That is, the MMIC is formed using steps such as ion implantation, annealing, CVD deposition, etching, and metal formation. As a result, the Au wiring 2 and the air bridge wiring 3 having a thickness of 2 μm and a gap of 3 μm are formed (FIG. 2A).

【0022】次に、Au配線2の一部分の直下の基板1
を、裏面まで貫通するまでエッチング除去して貫通口4
を形成した後、メッキ法を用いてこの貫通口4と基板1
の裏面に、Au配線5及びボンディングパッド6を設け
る(図2(b))。
Next, the substrate 1 immediately below a part of the Au wiring 2
Is removed by etching until it penetrates to the back surface.
After forming the through hole, the through hole 4 and the substrate 1 are formed by using a plating method.
The Au wiring 5 and the bonding pad 6 are provided on the back surface of the (FIG. 2B).

【0023】さらに、MMIC端にエアーブリッジ配線
3の高さよりも高い、絶縁物からなる高さ約10μmの
ガードリング7を形成し、このガードリング7上にキャ
ップメタル8を接着してMMIC表面全面を封止する
(図2(c))。
Further, a guard ring 7 made of an insulating material and having a height of about 10 μm, which is higher than the height of the air bridge wiring 3, is formed at the end of the MMIC, and a cap metal 8 is adhered onto the guard ring 7 to cover the entire surface of the MMIC. Are sealed (FIG. 2C).

【0024】最後に、リードフレーム10とボンディン
グパッド6とをボンディングワイヤ9で接続した後、基
板1全体をプラスティックパッケージ11で樹脂封止す
ることにより、図1で示した半導体集積回路が完成され
る。
Finally, after connecting the lead frame 10 and the bonding pad 6 with the bonding wire 9, the entire substrate 1 is resin-sealed with the plastic package 11 to complete the semiconductor integrated circuit shown in FIG. .

【0025】なお、今回の実施例では、図2(c)で示
したように、ガードリング7とキャップメタル8を用い
てMMIC表面全面を保護したが、これに限らず、凹型
のキャップメタルをMMIC表面接着してMMIC表面
全面を保護してもよいものである。
In this embodiment, as shown in FIG. 2 (c), the entire MMIC surface is protected by using the guard ring 7 and the cap metal 8. However, the present invention is not limited to this, and a concave cap metal may be used. The MMIC surface may be adhered to protect the entire surface of the MMIC.

【0026】[0026]

【発明の効果】以上のように、本発明の半導体集積回路
では、半導体基板表面上に形成されている集積回路上
に、この集積回路全面を封止する凹型のキャップメタル
を設けたので、樹脂形成工程による悪影響を受けること
無く、AC性能や歩留の低下、特性変動、及び耐湿性の
低下を防ぐことができる。
As described above, in the semiconductor integrated circuit of the present invention, since the concave cap metal for sealing the entire surface of the integrated circuit is provided on the integrated circuit formed on the surface of the semiconductor substrate, the resin It is possible to prevent deterioration of AC performance and yield, fluctuation of characteristics, and deterioration of humidity resistance without being adversely affected by the forming process.

【0027】同時に本発明の半導体集積回路では、半導
体基板表面上に形成されている集積回路の配線直下に半
導体基板裏面まで通じる貫通口が形成され、この貫通口
を介して前記集積回路の配線と電気的に接続される配線
及びボンディングパッドが半導体基板裏面に設けられて
いるので、配線設計の自由度が増すと共に、高周波性能
を維持できる。
At the same time, in the semiconductor integrated circuit of the present invention, a through hole is formed immediately below the wiring of the integrated circuit formed on the front surface of the semiconductor substrate and communicates with the back surface of the semiconductor substrate. Since the wiring and the bonding pad to be electrically connected are provided on the back surface of the semiconductor substrate, the degree of freedom in wiring design is increased and high frequency performance can be maintained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体集積回路の構造断面図。FIG. 1 is a structural cross-sectional view of a semiconductor integrated circuit of the present invention.

【図2】本発明の半導体集積回路の製造工程図。FIG. 2 is a manufacturing process diagram of a semiconductor integrated circuit of the present invention.

【符号の説明】[Explanation of symbols]

1 半絶縁性GaAs基板 2 Au配線 3 エアーブリッジ配線 4 貫通口 5 Au配線 6 ボンディングパッド 7 ガードリング 8 キャップメタル 9 ボンディングワイヤ 10 リードフレーム 11 プラスティックパッケージ 1 Semi-insulating GaAs substrate 2 Au wiring 3 Air bridge wiring 4 Through hole 5 Au wiring 6 Bonding pad 7 Guard ring 8 Cap metal 9 Bonding wire 10 Lead frame 11 Plastic package

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板表面上に形成されている集積
回路の配線直下に半導体基板裏面まで通じる貫通口が形
成され、この貫通口を介して前記集積回路の配線と電気
的に接続される配線及びボンディングパッドが半導体基
板裏面に設けられていることを特徴とする半導体集積回
路。
1. A wiring is formed immediately below the wiring of the integrated circuit formed on the front surface of the semiconductor substrate, and a through hole communicating with the back surface of the semiconductor substrate is formed. The wiring electrically connected to the wiring of the integrated circuit through the through hole. And a bonding pad provided on the back surface of the semiconductor substrate.
【請求項2】 半導体基板表面上に形成されている集積
回路上に、この集積回路全面を封止する凹型のキャップ
メタルを設けたことを特徴とする半導体集積回路。
2. A semiconductor integrated circuit characterized in that a concave cap metal for sealing the entire surface of the integrated circuit is provided on the integrated circuit formed on the surface of the semiconductor substrate.
JP4311635A 1992-11-20 1992-11-20 Semiconductor integrated circuit Pending JPH06163628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4311635A JPH06163628A (en) 1992-11-20 1992-11-20 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4311635A JPH06163628A (en) 1992-11-20 1992-11-20 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH06163628A true JPH06163628A (en) 1994-06-10

Family

ID=18019645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4311635A Pending JPH06163628A (en) 1992-11-20 1992-11-20 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH06163628A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0718885A3 (en) * 1994-12-19 1997-05-02 Martin Marietta Corp Interconnection protection structure on semiconductor chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0718885A3 (en) * 1994-12-19 1997-05-02 Martin Marietta Corp Interconnection protection structure on semiconductor chips

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