JPH06163577A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve step-coverages of metallic wirings in contact hole parts of high aspect ratios and obtain a highly integrated device, by connecting its source/drain regions and its metallic wirings respectively through respective polycrystalline silicon layers. CONSTITUTION:N<+>-polysilicon layers 7 containing an N-type impurity of a high concentration are buried in contact holes bored in layers laid on source/ drain diffusion layers 8 of an N-channel MOS transistor. By the respective N<+>-polysilicon layers 7, A wirings 1 and source/drain diffusion layers 8 are electrically connected respectively. Thereby, the steps of the contact hole parts of the N-channel MOS transistor which have high aspect ratios respectively are made small, and faulty wirings such as bench-cuts of the Al wirings 1 are prevented from occurring. Therefore, the step-coverages of the Al wirings 1 are improved so that a very fine and highly integrated semiconductor device can be achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and is particularly suitable for application to a semiconductor device having a CMOS structure, for example.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional semiconductor device having a CMOS structure. In the figure, 1 is an Al wiring, 2 is a silicon oxide film, 3 is a barrier metal such as TiN for preventing alloy spike (a phenomenon in which Al is deposited in a silicon substrate), 4 is a gate electrode, 5 is P ⁺ source / Drain diffusion layer, 6 is N
A well, 8 is an N ⁺ source / drain diffusion layer, and 9 is a P-type silicon substrate.

[0003]

In recent years, for example, CMO
As the memory cell having the S structure has been highly integrated, miniaturization of the N-channel MOS transistor has been promoted. As shown in FIG. 2, the source / drain diffusion layer 8 and the Al wiring 1 on the N-channel MOS transistor side are connected to each other. The aspect ratio of the contact hole portion to be connected is increasing.

Therefore, A at the contact hole
There is a problem that the step coverage of the l-wiring 1 is deteriorated and connection failure such as wiring breakage occurs, and as a result, high integration is difficult.

Therefore, an object of the present invention is to provide a semiconductor device which can improve the step coverage of metal wiring in a contact hole portion having a high aspect ratio and can be highly integrated.

[0006]

In order to solve the above-mentioned problems, according to the present invention, a pair of source / drain regions are formed on a semiconductor substrate, and a gate is formed on the substrate via an insulating layer. In the device, at least one of the pair of source / drain regions and the metal wiring formed on the substrate are connected by polycrystalline silicon.

[0007]

In the semiconductor device of the present invention, since the source / drain regions and the metal wiring are connected by polycrystalline silicon, for example, by filling the contact hole portion with low resistance polycrystalline silicon, the metal in that portion is The step coverage of wiring can be improved, and higher integration can be achieved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIG. In this embodiment, the same components as those of the conventional example described with reference to FIG. 2 are denoted by the same reference numerals and the description thereof will be omitted.

In this embodiment, the contact hole formed on the source / drain diffusion layer 8 of the N-channel MOS transistor is filled with polysilicon 7 containing a high concentration of N-type impurities formed by the CVD method. ing. The Al wiring 1 and the source / drain diffusion layer 8 are electrically connected to each other by the N ⁺ polysilicon 7. As shown in the figure, a barrier metal 3 such as TiN may be provided between the Al wiring 1 and the N ⁺ polysilicon 7 to prevent alloy spikes on the N ⁺ polysilicon 7. In the figure, 2'denotes a silicon oxide film.

With the configuration of this embodiment, an N-channel MOS
Since the step difference in the contact hole portion having a high aspect ratio of the transistor is reduced and wiring failure such as step breakage of the Al wiring 1 is prevented, miniaturization and high integration of the semiconductor device can be achieved.

[0011]

According to the semiconductor device of the present invention, in particular, it is possible to prevent disconnection of metal wiring in a contact hole portion having a high aspect ratio, so that higher integration of the semiconductor device can be achieved. it can.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor device having a CMOS structure according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part of a conventional semiconductor device having a CMOS structure.

[Explanation of symbols]

1 Al wiring 2, 2'silicon oxide film 3 barrier metal 4 gate electrode 5 P ⁺ diffusion layer (source / drain) 6 N well 7 N ⁺ polysilicon 8 N ⁺ diffusion layer (source / drain) 9 P-type silicon substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/90 D 7514-4M 27/092

Claims (1)

[Claims] 1. A semiconductor device in which a pair of source / drain regions is formed on a semiconductor substrate, and a gate is formed on the substrate via an insulating layer, wherein at least one of the pair of source / drain regions and the substrate. A semiconductor device characterized in that it is connected to the metal wiring formed on the substrate by polycrystalline silicon.