JPH06162139A - Layout verificatioin system - Google Patents

Abstract

PURPOSE:To verify the layout of a memory matrix by altering array information on layout constituent elements of the memory matrix, moving the array information around one cell in the constituent element at a start point, and reducing and reconstituting the layout constitution. CONSTITUTION:Processing before verification is performed for the layout of the memory matrix. Namely, the array information on the constituent elements of each memory matrix is altered (or erased) to 1 together with the matrix and moved around the start-point cell to obtain array layouts (a)-(c). Then, the layouts are verified. Consequently, the memory matrixes can be verified on the basis of one piece of array information. For example, when a 4-megabit memory matrix consists of 256 rows and 256 columns, the throughput is proportional to the number of memory cells which is the majority of the memory matrix and then reduced to 1/60,000, thereby enabling the layout verification.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout verification system, and more particularly to a layout verification system for a memory chip or the like containing large-scale repetitive figures.

[0002]

2. Description of the Related Art Layout verification is roughly classified into physical dimension verification (DRC) and circuit connection verification (LVS).
The amount of processing for these verifications increases in a memory or the like that includes a large number of repetitive figures. FIG. 5 shows an example of the memory chip layout. The memory chip is a memory matrix composed of a plurality of memory cells M of a certain size (256 kilobits to 1 megabit for a 4 megabit memory).
And a peripheral part connected to these, as shown in FIG.
(C) shows a basic type, a 2-division type, and a 4-division type, respectively.
The peripheral portion includes a row decoder and a row decoder amplifier X, a column decoder including a switching circuit and a column decoder amplifier Y, a sense amplifier S, a latch circuit L, and connection portions C1 to C4.
Composed of.

Since an example of a row decoder and a row decoder amplifier is different in each row as shown in FIG. 6,
Array expression is not possible. Hereinafter, it is assumed that the row decoder is not included in the constituent elements of the memory matrix. An example of the column decoder, column decoder amplifier, and switching circuit is shown in FIG. Here, although the column decoder amplifier can be expressed as an array independently, it is assumed that the cells of the switching circuit are included in the layout for simplification of description.

Here, the memory cell M, the sense amplifier S, the row decoder X, the column decoder Y, and the latch circuit L generally use a data structure called array information for reducing the data amount. FIG. 8 shows the representation of the array information in the storage device. This array information is obtained by adding the number of repetitions in the row and column directions, which is information peculiar to the array, to the reference information of the basic cell, and the repetition interval, so that a large-scale repeating figure is close to one cell. It can be expressed by the amount of data.
For example, if the memory cells are two-dimensionally arranged in 512 rows and columns, the amount of data is 1 / 250,000 that in the case where the memory cells are arranged normally.

A cell represented by array information, such as a memory cell, usually has one cell and two circuits or more because the layout is symmetrically arranged. This is shown in FIG. 9 as an example of a memory cell of a dynamic memory. FIG. 3A is a layout diagram and FIG. 1B is a circuit diagram. Normally, the memory cell M is 2
The dimensional array, row decoder amplifier X, sense amplifier S, column decoder amplifier Y, and latch circuit L form a one-dimensional array. Further, as shown in FIG. 10, the connection portions C1 to C4 provided at the corners of the memory matrix are arrays including input / output lines to the portions represented by the array information, and are not represented by an array. In this case, the number of repetitions can be regarded as an array having a matrix of 1. However, in FIGS. 5B and 5C, the connecting portion is omitted for simplification of description.
Furthermore, each component does not necessarily have a one-to-one matrix. An example thereof is shown in FIG. Here, one row decoder amplifier X, one latch circuit L, one column decoder amplifier Y, and one sense amplifier S correspond to two memory cells.

[0006]

Conventionally, in a chip including a large-scale repetitive figure such as a memory, the data itself is small because it is expressed in an array, but in layout verification, all figures are symmetric, so the processing amount is large. Increase, making verification virtually impossible. Therefore, conventionally, verification must be performed excluding the memory matrix, which is a problem that the verification is insufficient. It is an object of the present invention to provide a layout verification system that enables layout verification of a memory matrix.

[0007]

SUMMARY OF THE INVENTION The present invention modifies the array information of a layout component of a memory matrix before performing layout verification, and surrounds one cell in the component originating from this array information. And perform layout verification by reducing and reconfiguring the layout configuration of the memory matrix.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a layout diagram of a memory matrix showing a first embodiment of the present invention, in which FIG. 1 (a), (b), (c).
Shows a basic type, a two-divided type, and a four-divided type corresponding to (a), (b), and (c) of FIG. 5, respectively. Further, M is a memory cell, X is a row decoder amplifier, Y is a column decoder amplifier including a switching circuit, S is a sense amplifier, L is a latch circuit, and C1 to C4 are connection parts.

For these layouts, the process before verification is performed in the process shown in FIG. That is, FIG.
For each memory matrix in (c), first,
With the memory cell at the lower left as the starting point, the array information of the constituent elements is changed to 1 (or the array information is erased) and moved around the starting point cell to obtain the layouts of FIGS. 1 (a) to 1 (c). . Then, the layout is verified. Thereby, the verification of the memory matrix can be performed based on the array information of 1. For example, in a 4-megabit memory matrix, when the number of memory cells is 256 in both rows and columns, the amount of processing is proportional to the number of memory cells that represent most of the memory matrix, and is about 1/60000. It is possible to verify the layout of the memory matrix, which was difficult until now.

FIG. 3 shows a layout diagram of the second embodiment.
In this example, one row decoder amplifier X, one latch circuit L, one column decoder amplifier Y, and one sense amplifier S correspond to two memory cells M. Here, the array information of the memory cells is changed in the matrix as compared with the first embodiment.
This has an advantage that it can be applied even if it is not a one-to-two correspondence.

FIG. 4 shows a layout diagram of the third embodiment.
Here, a figure with the minimum width that connects the terminals is generated by cutting the peripheral part before and after the reduction. This is called a terminal connection figure. By generating this terminal connection figure, the electric connection between the memory cell M and the peripheral portion is achieved, so that it is possible to realize the LVS which was impossible in the embodiments of FIGS. 1 and 2.

[0012]

As described above, according to the present invention, the array information of the layout component of the memory matrix is changed before the execution of the layout verification, and the array information of one cell in the component serving as the starting point is changed. Since the layout verification is executed by moving around and reducing and reconfiguring the layout configuration, the processing amount at the time of verifying the memory matrix can be reduced and the layout verification of the memory matrix, which has been difficult in the past, can be performed.

[Brief description of drawings]

FIG. 1 is a layout diagram in a first embodiment of the present invention.

FIG. 2 is a flow chart of the method of the present invention.

FIG. 3 is a layout diagram in a second embodiment of the present invention.

FIG. 4 is a layout diagram of a third embodiment of the present invention.

FIG. 5 is a layout diagram of a basic type, a two-division type, and a four-division type of a memory matrix.

FIG. 6 is a circuit diagram of a row decoder and a row decoder amplifier.

FIG. 7 is a circuit diagram of a column decoder, a column decoder amplifier, and a switching circuit.

FIG. 8 is a format diagram showing array information in a storage device.

FIG. 9 is a layout and circuit diagram of a memory cell.

FIG. 10 is a layout diagram showing an example of a connection unit.

FIG. 11 is a layout diagram showing an example of correspondence of components of a memory matrix.

[Explanation of symbols]

M memory cell X row decoder amplifier (including row decoder) Y column decoder amplifier (including column decoder and switching circuit) S sense amplifier L latch circuit C1 to C4 connection section

Claims (1)

[Claims] 1. Prior to performing layout verification, the array information of a layout component of a memory matrix containing a large number of memory cells is modified, and the array information is moved around a cell in the starting component. Then, the layout verification system is characterized in that the layout structure of the memory matrix is reduced and reconfigured to execute the layout verification.