JPH06161929A - Computer - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a computer that facilitates the change of the BIOS without the work of replacing the ROM. [Configuration] In a system in which FPROM and mask ROM are mixed, the ROM address viewed from the CPU is divided into three, the first area is a bank of FPROM and a plurality of mask ROMs, the second area is a single bank of FPROM, Third
Area is composed of a plurality of FPROM banks, and the first and third FPROM banks are programmed by the second area FPROM program.
Having means for switching a plurality of banks in the area
The starting operation is performed by the FPROM in the area. The third
The area is controlled so that it cannot be electrically erased.
The FPROM can be selected for rewriting by attaching a rewriting key to the external bus. The data in the FPROM is rewritten by reading the data from the external storage device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention stores software for controlling functions unique to a processing apparatus and software for controlling basic functions independent of the processing apparatus in different ROMs, and stores the ROMs according to the functions of the processing apparatus. Regarding the computer that uses the above software properly.

[0002]

2. Description of the Related Art When developing a computer, a BIOS
Was developed, and when a computer with higher functions was developed, a new BIOS for the computer had to be developed, and one computer was equipped with one BIOS.

Further, Japanese Patent Laid-Open No. 4-69742 discloses that
If the installed BIOS is not normal, the correct BIOS program obtained by reading from the secondary storage medium (communication port, floppy disk, etc.) is FPR.
Write to OM. This shows an example of preventing the system from becoming inoperable even if an abnormality occurs in the BIOS program.

[0004]

However, in the above-mentioned method, the development of the BIOS and the development of the hardware have to be performed in parallel, which takes time. Also, when the BIOS is upgraded, the ROM may be changed in the market or manufacturing process.
Therefore, it is necessary to perform the replacement work of No., which causes unnecessary man-hours.

The method disclosed in Japanese Patent Laid-Open No. 4-69742 can prevent the system from being inoperable, but cannot upgrade the version. Furthermore, in a system in which the writing means of the FPROM is incorporated into the system and the writing means of the FPROM is different, a BIOS to be incorporated into the system in advance must be developed.

An object of the present invention is to improve the development efficiency of hardware and facilitate the change of BIOS.

[0007]

A computer according to the present invention comprises a flash PROM rewritable by an electric signal in which a part of BIOS (hereinafter, BIOS # 1) is stored, and another part of the BIOS (hereinafter, BIOS # 2). ) Is stored in the mask ROM which cannot be rewritten by the electric signal and RA
BIOS in which the BIOS is loaded by M transfer means
In a computer having a RAM for execution, a BIOS stored in the FPROM and calculating the contents of the BIOS # 1 to determine whether the computer is suitable for the computer.
If the usage discriminating means and the BIOS # 1 do not match, the flash PR called by the BIOS # 2 from the external storage device to rewrite the BIOS # 1.
OM rewriting means.

In addition, the flash PROM rewriting means is provided with a flash PROM rewriting key which allows the flash PROM rewriting means to recognize the rewriting of the BIOS # 1 in preference to the BIOS usage determining means.

In the computer of the present invention, a flash PROM which is rewritable by an electric signal in which a part of BIOS (hereinafter, BIOS # 1) is stored, and an electric part in which another part of the BIOS (hereinafter, BIOS # 2) is stored. In a computer having a mask ROM that is not rewritable by a signal and a BIOS execution RAM into which the BIOS is loaded by the RAM transfer means, the program execution RAM is divided into three areas and divided into a plurality of banks. Of the BIOS # 1, a first RAM area to which a bank including at least a system booting unit, the RAM transfer unit, and the BIOS use determining unit is allocated, and another bank of the BIOS # 1 are A second RAM area to be allocated and the remaining banks of BIOS # 1;
BIOS # 2 divided into a plurality of banks, and a third RAM area to which all the banks are assigned.

Further, the system starting means is masked so that it cannot be rewritten. Also, the first RAM
A plurality of banks assigned to the area and the third RA
The plurality of banks allocated to the M area are switched by the bank switching means included in the BIOS # 1 allocated to the second RAM area.

Further, the flash PROM rewriting means adds a cache memory control means of the CPU.

Also, one FDC (floppy disk controller) is provided by the flash PROM rewriting means.
By the means, means for controlling five or more FDDs including a RAM drive is added.

[0013]

The present invention stores software (BIOS # 2) for controlling a function peculiar to a processing device in a mask ROM so as to control a function independent of the processing device (BI).
OS # 1) is stored in the FPROM and the BIOS # 2 on the mask ROM is used when only the basic functions of the processor are used. When all the functions are used, the BIOS # 1 and the mask ROM on the FPROM are used. BIOS # 2 can be used.

[0014]

1 is a block diagram of an apparatus used in an embodiment of the present invention. In FIG. 1, a CPU 1, a RAM 2 that executes software, a mask ROM 3 that stores a BIOS # 2, and an FPROM 4 that stores a BIOS # 1.
Also, the FDC 5 of the floppy disk controller (hereinafter FDC) that controls the external storage device is the system bus 1.
Connected by 0. The FDD 6 is a floppy disk drive (hereinafter referred to as FDD) which is controlled by the FDC 5 and accesses a floppy disk which is an external storage device. The FPROM rewriting key 7 is connected to the expansion bus 11 to output a specific signal to the system. The system is supplied with electricity from a power supply 8 via a power supply line 9.

The FPROM 4 has means 4a for controlling all the functions depending on the model, more specifically, it holds the current state even if the system power is turned off during execution of software.
Resume function control means that allows work to continue from the state when the power was turned off at the next power-on, control means that treats the built-in RAM in the same way as a floppy disk, and built-in according to user settings. A BIOS # 1 having means for deciding how to use RAM is stored, and a mask ROM stores a model-independent basic function control means 3a other than the BIOS # 1, specifically, an FDC 5 connected to the system. BIOS # 2 including means for controlling and reading data from a floppy disk via FDD6, and means for initializing FDC5 necessary for that purpose
Is stored. In addition, the mask ROM also stores high-level language subroutines that can be used for all models.

FIG. 2 is a schematic diagram of the BIOS # 1 which corresponds to the model.
It is a flowchart at the time of rewriting to IOS. When the system is powered on, the BIOS usage determining means 4c confirms whether the data in the BIOS # 1 on the FPROM 4 is the BIOS compatible with the system. BIOS # 1
Since the data of is a hexadecimal number, it can be calculated. Utilizing this, the data of the BIOS # 1 is added in byte unit (hereinafter checksum) to obtain the operation result (hereinafter checksum value) (STEP2a). Here, the data of the BIOS # 1 is previously corrected so that the data has a specific value when the checksum value is calculated. This specific value corresponds to the version of BIOS # 1, and it is possible to determine whether or not the BIOS corresponds to each model according to this version (STEP 2b). Therefore, if the checksum value does not match a particular value, the BIOS
It is determined that the data of # 1 is not correct, and the RAM transfer means 4
The BIOS # 2 on the mask ROM 3 is expanded to the RAM 2 by b (STEP 2g). Then, the control is transferred to the RAM 2 (STEP 2h), and the basic control means 3a controls the FD.
The hardware is initialized so that C5 can operate (STEP2i), and FPRO is run from the floppy disk.
Read the system with M rewriting (STEP
2j), control is transferred (system startup) (STEP2
k). BI if the checksum value matches a certain value
It is determined that the data of OS # 1 is correct.

Next, the BIOS on the FPROM 4 is forcibly forced.
It is checked whether or not # 1 can be rewritten (STEP2c). For example, when a new function is added to the BIOS # 1 to upgrade the BIOS, even if the checksum value is correct, the rewriting is forcibly performed. This check method is
FPR which is a board to inform the system to that effect.
It is realized by connecting the OM rewriting key 7 to the expansion bus 11. The notification method can be known by an electric signal,
The software determines whether the signal read from the port has a specific value. Specifically, port 8F2
If the value read from H is 1745H, FPROM
It is determined that the rewrite key 7 is attached. Therefore, it becomes possible to judge whether or not the FPROM rewrite key 7 is present, and when the BIOS # 1 is forcibly rewritten (FP
If the ROM rewrite key 7 is installed), BIO
In the same way as when the data of S # 1 is incorrect (STE
P2g), the system having the FPROM rewriting process is read from the floppy disk, and the control is transferred.
Of course, the system may be read from the memory on the FPROM rewrite key 7.

When the BIOS # 1 of the FPROM is not rewritten, the BI on the FPROM 4 is transferred by the RAM transfer means 4b.
BIOS on the mask ROM 3 independent of OS # 1 and model
# 2 is expanded in RAM2 (STEP2d). afterwards,
The control is transferred to the all-function control means 4a and the basic-function control means 3a developed in the RAM 2 (STEP 2e), various hardware is initialized, and then the system is started (S).
TEP2f).

FIG. 3 is a memory map viewed from the CPU. Banks 0 to 7 are each composed of blocks of 32 KB (kilobytes), and are arranged in the memory space for each bank under software control. The basic function control means 3a is stored in the bank 4, the RAM transfer means 4b and the BIOS use determination means 4c are stored in the bank 2, and the all function control means 4a is stored in the banks 1 and 3, respectively. Also, bank 0
Contains a program for setting the operating environment of the system. Furthermore, banks 5 to 7 are currently unused, but in the future, a BIOS that controls sound functions.
It is possible to store additional system control functions and the like.

When the power is turned on, the execution address of the CPU points to bank 2 of the FPROM, and the program is executed from bank 2. In the bank 2, after the BIOS usage determining means 4c determines whether the checksum value of the BIOS # 1 of the FPROM is correct and whether the FPROM is forcibly rewritten, the system is activated based on the determination results. Of the banks 2 in which this series of processing is stored, 8 KB is protected by the system so that it cannot be electrically erased when the system is connected (I
NTEL MEMORY PRODUCTS 1992
(See P3-114 etc.). This is to prevent the system from becoming inoperable if it is accidentally erased by the system having the FPROM rewriting process described above.

When the BIOS actually operates, it must operate in the space of 96 KB from the CPU address E8000H to FFFFFH. BI on FPROM4
When expanding OS # 1 to RAM, FPROM128K
64KB of banks 1 and 3 of B and 12 of mask ROM
RA of the total KB of 32 KB of bank 4 out of 8 KB
It is expanded in the RAM 2 by the M transfer means 4b.

Mask ROM 3 or FP in the memory space
By arranging the ROM 4, the mask ROM 3 or the F
When the data on the PROM 4 is read and the CPU performs a write operation, the data is written to the RAM 2 for BIOS expansion. Further, when the RAM 2 for expanding the BIOS is arranged in the memory space, the data in the RAM 2 can be read when the CPU performs the read operation in the memory space, but the data cannot be written even when the CPU performs the write operation. To control. In this way, the data on the RAM can be treated as if it were the data on the ROM.

When the BIOS is expanded from the ROM to the RAM, the ROM is arranged in the memory space and the CPU is the RO.
After reading the data of M, the read data is written in the ROM of the same memory space. When the CPU performs the writing operation to the ROM, the data is actually written to the RAM as described above. For this reason, it is optimal to perform the process of switching the bank in bank 1. This is because, if the bank is switched with bank 3, bank 0, bank 4
Although there is no problem in switching each of the banks 7 to 7, if the banks 3 and 2 are switched, the bank 2 will appear in the memory space during processing in the bank 3. Then,
This is because the processing of bank 3 cannot be executed and the processing cannot be continued. The same applies to Bank 0, Bank 2, and Banks 4 to 7. Also,
Since the data of the bank 1 is expanded in the RAM of the same address, it is preferable that the bank 1 also performs the process of switching the memory space between the ROM and the RAM.

FIG. 4 is a flowchart for rewriting the BIOS # 1 on the FPROM 4 with the data from the external storage device. If there is no full-function control means 4a on the FPROM 4, the system determines that the checksum value is incorrect and performs the FPROM rewriting process. BIOS having basic function control means 3a on the mask ROM 3
# 2 is expanded in RAM (STEP4a). And RA
The control is transferred to M (STEP4b), and the hardware is initialized so that the FDC 5 can operate (STEP4b).
c), a system having FPROM writing means (FP
ROM rewriting utility) is read from the floppy disk via FDD6 and expanded to RAM (S
TEP4d). After that, control is transferred to the FPROM rewriting utility (STEP 4e). FPROM
The rewriting utility reads the data to be written on the FPROM from the floppy disk by using the basic function control means 3a (STEP4f), then arranges the FPROM in the memory space (STEP4g) and uses the FPROM writing means to enter the FPROM into the BIOS. Write # 1 (STEP4h).

FIG. 5 shows a high performance C as an application example of the present invention.
It is a flowchart at the time of controlling PU. CPU with cache function to increase operating speed
, The cache function of the CPU remains invalid even when the power is turned on, so that the function of the CPU cannot be fully exerted. Therefore, a process for enabling the cache function of the CPU by software is required. After the power is turned on, the CPU status is acquired. Next, enable the cache while saving the states other than the cache. The state is set in the CPU. In the system of FIG. 1, when only the CPU is replaced with a high-performance CPU, a BIOS having a process for enabling the cache function is required. Therefore, on a system with a changed CPU, use a floppy disk to
By rewriting the BIOS on the PROM to the BIOS having means for controlling the cache function of the CPU, B
The system can easily be made high performance without replacing the IOS ROM.

FIG. 6 shows the processing of the BIOS when a RAM accessible from the I / O port is newly added in the system of FIG. 1 and the RAM is processed as a floppy disk. The advantage of treating the RAM as a floppy disk is that it can be accessed faster than a floppy disk and the system can be made physically smaller.
Also, when the application or OS accesses the RAM, it is the same as accessing the floppy disk as long as the access is performed via the BIOS, so there is no need to change the application or OS even if the RAM is added. . Therefore, conventional applications and O
S can be used as is, and performance can be improved.

Normally, four FDDs can be controlled by one FDC. Therefore, when the OS accesses the FDD via the BIOS, the unit numbers 0 to 3 of the FDD are designated to call the BIOS processing. In Fig. 1, FDD is 1
Since it is a stand, the unit number 0 is specified when accessing the FDD. Other than 0 (1 to 3) is treated as unconnected. Here, when the above-mentioned RAM is newly added to access as a floppy disk, 1 is designated as the unit number. According to this unit number, the BIOS operates the FDC to access the floppy disk when the unit number 0 is specified and is called, and operates the I / O port when the unit number 1 is specified and called. Access the RAM. In this way, when basic functions of the system are left unchanged and new functions are added (RAM that can be used for floppy disk is added), BIO
It is necessary to change S. In this case as well, similar to the above-mentioned CPU change, by rewriting the BIOS on the FPROM using the floppy disk to the BIOS having a means for accessing the RAM as the floppy disk, the system can be easily replaced without replacing the BIOS ROM. The function of can be changed.

[0028]

According to the present invention, the BIOS can be selectively used according to the required function of the system, and the version of the BIOS can be easily upgraded by changing the system.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus used to implement the present invention.

FIG. 2 is a flowchart at system startup according to the present invention.

FIG. 3 is a memory map viewed from a CPU according to the present invention.

FIG. 4 is a schematic diagram of a BIOS using an external storage device according to the present invention.
Flowchart to rewrite.

FIG. 5 is a flowchart of cache control of a CPU according to an application example of the present invention.

FIG. 6 is a flowchart of using a RAM as a floppy disk according to an application example of the present invention.

[Explanation of symbols]

 1: CPU 2: RAM for executing software 3: Mask ROM 4: FPROM 5: FDC 6: FDD 7: FPROM rewrite key 8: Power supply 9: Power supply line 10: System bus 11: Expansion bus

Claims (7)

[Claims] 1. A flash PROM rewritable by an electric signal in which a part (hereinafter referred to as BIOS # 1) of a basic input / output control means (hereinafter referred to as BIOS) and an other part of the BIOS (hereinafter referred to as BIOS # 2) are provided. A mask ROM that cannot be rewritten by the stored electric signal, and a BI that the BIOS is loaded by the RAM transfer means.
In a computer having a RAM for OS execution, BI that is stored in the FPROM and operates the contents of the BIOS # 1 to determine whether the computer is suitable for the BI
When the OS usage determining means and the BIOS # 1 do not match, the BIOS #
2 is called from the external storage device by the BIOS #
And a flash PROM rewriting means for rewriting 1. 2. The computer according to claim 1, further comprising a flash PROM rewriting key for causing the flash PROM rewriting means to recognize the rewriting of the BIOS # 1 in preference to the BIOS usage determining means. 3. A flash PRO which is rewritable by an electric signal in which a part of BIOS (hereinafter, BIOS # 1) is stored.
M, a mask ROM in which other parts of the BIOS (hereinafter, BIOS # 2) are not rewritable by an electric signal stored therein, and a BI in which the BIOS is loaded by the RAM transfer means.
In a computer having a RAM for OS execution, the RAM for program execution is divided into three areas, and in the BIOS # 1 divided into a plurality of banks, at least a system boot means, a RAM transfer means, and A first RAM area to which a bank including the BIOS usage determining means is allocated, and a second RAM area to which another part of the bank of BIOS # 1 is allocated.
Computer, a remaining bank of BIOS # 1, and a third RAM area to which all banks of BIOS # 2 divided into a plurality of banks are allocated. 4. The computer according to claim 3, wherein the system starting means is masked so that it cannot be rewritten. 5. The switching of the plurality of banks assigned to the first RAM area and the plurality of banks assigned to the third RAM area is performed by BIOS # 1 assigned to the second RAM area. The computer according to claim 4, wherein the operation is performed by included bank switching means. 6. The computer according to claim 1, wherein the flash PROM rewriting means adds a cache memory control means of a CPU. 7. The flash PROM rewriting means further includes means for controlling five or more FDDs including a RAM drive by one FDC (floppy disk controller). Computer.