JPH06161615A - Battery backup method for memory in high speed actuation information processor and circuit therefor - Google Patents

Abstract

(57) [Abstract] [Purpose] In a battery backup method for a memory in a high-speed operation information processing device and its circuit, a chip select circuit is configured by reducing the current consumption of the battery and selecting a circuit element capable of high-speed processing. The degree of freedom in selecting circuit elements to be used is increased. [Structure] In a power supply circuit of a memory used in an information processing apparatus, a main power supply circuit 2 of the information processing apparatus is connected to each memory element forming the memory, for example, a memory element 5 via a first diode 10. , The backup battery 7 of the memory element 5 is connected to the memory element 5 via the second diode 8 so that a predetermined fixed voltage is supplied to the chip select terminal 5a of the memory element 5 when the main power supply is cut off. . In addition, in the battery backup circuit of the memory element 5 in the high-speed operation information processing device, the circuit configuration is configured to execute the above method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery backup method for an information processing device memory and its circuit, and
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery backup method of a memory in a high-speed operation information processing apparatus which is optimal for an information processing function executed at high speed, and a circuit thereof.

[0002]

2. Description of the Related Art In an information processing apparatus in which an information processing function (hereinafter abbreviated as CPU) such as a microcomputer and a memory are combined, a volatile memory and a non-volatile memory are used as the above-mentioned memory. There is. The above-mentioned volatile memory may employ a means for backing up by a battery provided as a power source different from the above-mentioned power source so that the recorded information is not erased even after the power source is cut off. In addition, in the information processing apparatus in which the memory includes a plurality of memory elements, each memory is provided with a chip select terminal in order to select a memory element to be accessed from a plurality of connected memory elements. The select terminal is connected to a chip select circuit that is commanded and controlled by the main information processing CPU or the like. When the memory is accessed from the CPU, the memory element designated by the chip select signal output from the chip select circuit according to the address signal input from the CPU causes the memory element designated to write or read.
A mode operation (command input circuit not shown) is executed by an input address signal and data signal.

An example of the above-mentioned conventional circuit will be described with reference to FIG. FIG. 2 is a block circuit diagram showing an example of a battery battery backup circuit in a conventional information processing apparatus.
In FIG. 2, illustration of element elements and circuits provided in this information processing apparatus, which are not directly related to the present invention, is omitted.
Further, each signal line formed by a plurality of signal lines is shown by one line, and a memory constituted by a plurality of memory devices is also shown as a representative of one volatile memory device requiring battery backup for convenience of description. (It is called a memory element). In FIG. 2, reference numeral 1 is a CPU, which is supplied with a predetermined voltage from the main power supply circuit 2, for example, 5V. C
The address signal line 3 and the data signal line 4 are connected from the PU 1 to the memory element 5. As described above, the memory device 5
Is a memory element that is backed up by a battery when the power is cut off, and this memory element 5 represents one of a plurality of memory elements that constitutes one memory as a whole. Further, the chip select circuit 6 for outputting a chip select signal designating a memory element to be accessed according to the address signal output from the CPU 1 is CP.
It is provided between U1 and the memory element 5. Further, the memory device 5 and the chip select circuit 6 are provided with a second power supply battery 7 for backing up the operation of the memory device 5 from the main power supply circuit 2 via the first diode 9 when the power supply is cut off. , And each of them is connected via a diode 8. Therefore, when connecting the main power supply circuit 2,
The current supplied from does not flow to the battery 7. When the main power supply circuit 2 is cut off, the current supplied from the battery 7 does not flow back to the main power supply circuit 2 by the first diode 9 connected in series. Further, when the main power supply circuit 2 is cut off, a predetermined signal (voltage) output from the chip select circuit 6 that operates by the voltage supplied from the battery 7 is input to the chip select terminal of the memory element 5 and the battery 7
The memory element 5 continues recording without erasing the recording data by the voltage supplied from the memory device.

[0004]

By the way, in the case of backing up the memory device, in order to minimize the current consumption of the memory device, reduce the consumption of the backup battery and prolong the possible operating time of the battery, It is necessary to hold the chip select terminal at a voltage lower than the power supply voltage (hereinafter abbreviated as Vcc) by 0.2 V or more. In order to increase the operating speed of the CPU and operate the chip select circuit at high speed, an element such as an IC with a high operating speed such as a PLD (programmable logic device) or a bipolar IC is used for the chip select circuit element. There is a need to. However, such a device having a high operation speed consumes a large amount of current, and the backupable time of the backup battery is significantly shortened. On the other hand, there is a problem that a CMOS IC, which consumes less current, has a slow operation speed and a long access time. In addition, the PLD described above
In such ICs, when the power is turned off, the select signal output terminal voltage becomes (Vcc-0.2) volt or less, so that the memory chip select terminal input voltage becomes (Vcc-0.2) volt or less. Therefore, the current consumption of the memory does not decrease. As a countermeasure against this, as shown in FIG. 2, the circuit is configured such that the backup battery is used as the power source for the chip select circuit as well as the memory element.

Therefore, there have been the following problems (problems). An IC as a circuit element with low current consumption that can be backed up by a battery and is used in a chip select circuit has a longer information processing time than the above-described PLD or the like, which has a high operating speed. Therefore, the memory access time of the CPU is lengthened. However, even if a CPU with a high processing speed is used, the high speed performance cannot be exhibited. Therefore, the time required to access the memory from the CPU is limited by the operating speed of the circuit elements used in the chip select circuit. A high-speed circuit element such as a PLD used in the chip select circuit consumes a large amount of current, and the life of the backup battery is shorter than that when supplying current to only the memory element. Therefore, it is not suitable for battery backup. Since it is necessary to use ICs having high operating speed and low current consumption for the circuit elements used in the chip select circuit, circuit design such as selection of circuit elements such as ICs usable in the chip select circuit is limited.

In order to solve the above problems, it is an object of a memory battery backup method and its circuit in a high-speed operation information processing apparatus according to the present invention to satisfy the following conditions. A battery backup is not required for the chip select circuit, and the current consumption of the circuit elements used in the chip select circuit is not limited so that the circuit element capable of high-speed processing can be selected. The degree of freedom of selection of the circuit elements forming the is increased. The memory device is the only circuit device to be backed up by the battery for battery backup. When the power supply voltage is cut off, the chip select terminal of the memory element is set to (Vcc-a) volt or more. The a volt described here is a voltage determined by the memory element, and when targeting the memory element described in the related art, 0.
It is 2 volts.

[0007]

In order to solve the above problems, in the battery backup method of the memory in the high speed operation information processing apparatus according to the present invention, this information is stored in the power supply circuit of the memory used in the information processing apparatus. The main power source of the processing device is connected to the memory via the first diode, and the backup battery of the memory is connected to the memory via the second diode to prevent the information processing device from operating. When the main power supply is cut off, a predetermined fixed voltage is supplied to the chip select terminal of the memory. In addition, in the battery backup circuit of the memory in the high-speed operation information processing device, the circuit configuration is configured to execute the above method.

[0008]

Since the battery backup method for the memory and the circuit thereof in the high speed operation information processing apparatus of the present invention are constructed as described above, the following operations will appear. Only the memory is targeted for battery backup, and the chip select terminal voltage of the memory element can be set to a predetermined value or higher. Therefore, the current consumption of the memory when the main power supply of the information processing apparatus is cut off is reduced. Since the current consumption of the memory is reduced when the main power is cut off, the backup battery is consumed less and the battery life is extended during battery backup. Since it is no longer necessary to limit the current consumption of the circuit elements used in the chip select circuit, the degree of freedom in selecting the circuit elements forming the chip select circuit is increased. The access time is shortened by selecting the circuit elements forming the chip select circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to FIG. FIG. 1 is a block circuit diagram showing a battery backup circuit of a memory, showing the function of element circuits, for explaining a battery backup method of a memory and its circuit in a high-speed operation information processing apparatus according to the present invention. In the prior art, the same or similar circuit elements as those shown in FIG. 2 are designated by the same reference numerals. In addition, illustrations of element elements, circuits, and signal lines not directly related to the present invention are omitted, and each signal line formed by a plurality of signal lines is shown by one line and is constituted by a plurality of memory elements. The memory function is also represented by one volatile memory element. In FIG. 1, reference numeral 1 denotes a CPU (information processing function of a microcomputer or the like), which is supplied with a predetermined voltage Vcc, for example 5V, from a main power supply circuit 2. Address signal lines 3 and data signal lines 4 from the CPU 1 are connected to the memory element 5. The main power supply circuit 2 is connected to the power supply terminal of the memory element 5 via the first diode 10. The memory device 5 is a CMOS S
It is a memory such as a RAM that can be backed up by a battery, and is a memory element that can reduce current consumption by holding the chip select terminal voltage at a predetermined voltage or higher. As described above, in FIG. 1, as in the case of FIG. 2, one of the plurality of memory elements is shown as a representative. Further, a chip select circuit 6 for outputting a chip select signal designating a memory element to be accessed according to an address signal output from the CPU 1 is provided between the CPU 1 and the memory element 5. Chip select circuit 6
A contact circuit 11a of a relay 11 to be described later is connected in series between the chip select signal output terminal 6a and the chip select terminal 5a of the memory element 5. The chip select circuit 6 is a CPU that executes high-speed information processing such as PLD.
1 is composed of circuit elements having a processing speed required, and a main power supply circuit 2 is connected.

A power supply battery 7 for backing up the operation of the memory element 5 when the voltage supply from the main power supply circuit 2 is cut off is connected to the memory element 5 through a second diode 8. G indicates a ground line.
The relay 11 is connected between the main power supply circuit 2 and the ground line G, and the contact circuit 11a of the relay 11 is connected as described above.
Is the chip select output terminal 6a of the chip select circuit 6.
And a chip select terminal 5a of the memory element 5 are connected. Further, the chip select terminal 5a circuit of the memory element 5 and the power supply terminal circuit portion of the memory element 5, that is, the first diode 10, the second diode 8 and the power supply terminal of the memory element 5 are connected. Between the circuit part
A fixed resistor 12 having a predetermined resistance value is connected.

In the above circuit, when the main power supply circuit 2 is energized and the CPU is operating, the voltage Vcc transmitted by the main power supply circuit 2 is supplied to the memory element 5 via the first diode 10. It Further, since a current flows through the relay 11, the contact circuit 11a of the relay 11 is closed. Therefore, the chip select signal output terminal 6a of the chip select circuit 6 is connected to the chip select terminal 5a of the memory element 5. When the CPU 1 accesses the memory element 5 to write data (read / write signal line is not shown), the address signal transmitted by the address signal line 3 output from the CPU 1 causes The chip select signal output by the chip select circuit 6 is
Since the resistance value of the fixed resistor 12 is set appropriately, it is input to the chip select terminal 5a of the memory element 5 without attenuation. Therefore, the data output to the data signal line 4 is written in the designated address of the memory element 5 selected by the chip select signal output by the chip select circuit 6. When reading the memory recording data, the data at the designated address of the memory element 5 is read by the CPU as in the above. In this case, even if the voltage Vcc of the main power supply circuit 2 is higher than the voltage of the battery 7, the battery 7 is not supplied with power from the main power supply circuit 2 by the second diode 8.

In the above circuit, when the voltage transmission from the main power supply circuit 2 is cut off, the CPU completes a predetermined process before the voltage becomes a predetermined value or less. Since the voltage of the main power supply circuit 2 disappears, the voltage of the battery 7 is supplied to the memory element 5 via the second diode 8. Battery 7
Is not supplied to the main power supply circuit 2 by the action of the first diode 10. Further, since the voltage of the main power supply circuit 2 disappears, the voltage applied to the relay 11 disappears.
Therefore, the contact circuit 11a of the relay 11 is opened, and the voltage of the battery 7 is supplied to the chip select terminal 5a of the memory element 5 via the fixed resistor 12. Since the resistance value of the fixed resistor 12 is set appropriately, the fixed resistor 12 is connected to the chip select terminal 5a of the memory element 5.
Via a predetermined voltage, for example (Vcc-0.
2) More than a volt is supplied. Therefore, the memory element 5 continues to hold the storage data at the consumption of a predetermined current value.

The above description shows the basic method and configuration for realizing the technical idea of the present invention, and can be variously applied and modified. For example, when the current supply from the main power supply circuit 2 is stopped, the contact circuit 11a of the relay 11 is opened and the fixed resistor 12 supplies the battery voltage to the chip select terminal 5a of the memory element 5.
The memory element 5 has a voltage suitable for executing the function of holding the memory data with a small current consumption, for example (Vcc-0.
2) Any circuit may be used as long as it can supply more than a volt. Although the relay is described as a relay having a mechanical structure, if the above-mentioned predetermined characteristics are obtained, a contactless relay element such as a semiconductor gate element is used. Is also good. In addition, if the above-mentioned functions are satisfied, it is needless to say that a circuit having appropriate functional elements may be configured corresponding to the circuit related to the CPU and the memory.

[0014]

Since the present invention is constructed as described above, it has the following excellent effects. It is no longer necessary to limit the current consumption of the circuit elements used in the chip select circuit. Therefore, it was possible to increase the degree of freedom in selecting the elements that make up the chip select circuit. Since the battery is the only circuit element to be backed up by the memory element, the battery consumption is reduced and the battery life can be extended. Since the chip select terminal of the memory element can be set to a predetermined fixed voltage, for example, (Vcc-0.2) volt or more when the power is cut off, the current consumption of the memory when the power of the memory is cut off can be reduced. It can have a long life.

[Brief description of drawings]

FIG. 1 is a schematic block diagram for explaining an embodiment of a battery battery backup method and its circuit in a high-speed operation information processing apparatus according to the present invention.

FIG. 2 is a schematic configuration block diagram showing an example of a battery battery backup method in a conventional information processing apparatus.

[Explanation of symbols]

 1: CPU (information processing function for information processing device) 2: main power supply circuit 3; address signal line 5: memory element 6: chip select circuit 7: battery 8, 10: diode 11: relay 12: fixed resistor

Claims (2)

[Claims] 1. A power supply circuit of a memory used in an information processing apparatus that requires high-speed operation, wherein a main power supply circuit of the information processing apparatus is connected to the memory via a first diode, The memory backup battery is connected to the memory via the second diode, and a predetermined fixed voltage is supplied to the chip select terminal of the memory when the main power is cut off when the information processing apparatus is not operating. A method for backing up a battery of a memory in a high-speed operation information processing device, characterized in that. 2. A power supply circuit for a memory used in an information processing apparatus that requires high-speed operation, wherein a main power supply circuit of the information processing apparatus and a first diode are connected in series to each other. Connected to a terminal, connected to a power supply terminal of the memory from a backup battery of the memory through a second diode, and a chip select terminal of the memory when power is cut off from the main power supply circuit of the information processing apparatus. A battery backup circuit for a memory in a high-speed operation information processing apparatus, wherein a relay function for switching an input circuit from a chip select circuit to a voltage supply circuit of a predetermined value is provided.