JPH06169260A - Serial-parallel conversion circuit - Google Patents

Abstract

PURPOSE:To ensure a sufficient setup time even against high speed data and to surely execute serial-parallel conversion by allowing the serial parallel conversion circuit to latch data of an FF of a parallel circuit at a leading time of a clock. CONSTITUTION:A control signal C is at an L level at a 2nd clock CP2 and a selector 31 for a 1st bit selects an output P1, that is, 1st data D as an output Y1. A D flip-flop F21 latches the output Y1 at a leading of a clock CP3 and since the signal C for the period is at an H level, an output 01 of the D flip-flop F21, that is, data D1 are obtained at the output Y1. The operation is similarly repeated and odd number data such as data D1, D3... are outputted as the output 01 of the D flip-flop F21 in a 1/2 frequency division timing of the clock CP. Furthermore, a D flip-flop F12 for a 2nd bit, a selector 21 and a D flip-flop F22 are operated similarly to above, resulting that evennumber data such as data D2, D4... are outputted in a 1/2 frequency division timing of the clock CP. Finally parallel data (D0, D1), (D2, D3)... are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial-parallel conversion circuit,
In particular, it relates to a serial-parallel conversion circuit used for serial-parallel code conversion of high-speed data.

[0002]

2. Description of the Related Art For convenience of description, a conventional serial-parallel conversion circuit has a serial configuration in which 2-bit serial code data D is input as shown in FIG. Two-stage D flip-flop F1 connected
1, a shift register 1 composed of F12 and a parallel circuit 2 composed of two D flip-flops F21 and F22 which receive outputs of the D flip-flops F11 and F12 as inputs and output outputs O1 and O2, respectively. Was there.

Next, the operation of the conventional serial-parallel conversion circuit will be described.

The shift register 1 is a 2-bit shift register, and the D flip-flops F11 and F12 operate with the clock CP as a shift pulse. Further, the D flip-flops F21 and F22 of the parallel circuit 2 are driven by an external control signal C obtained by dividing the clock CP by two and latch data and output data.

Generally, when the data D is low speed, for example, 20 MHz or less, the clock C is used as the control signal C.
A signal that rises in synchronization with the falling edge of P is used.
On the other hand, since the data D is transmitted in synchronization with the rising edge of the clock CP, the control signal C rises at the center of the data D. In this case, since the length of one cycle of the data D is relatively long, the D flip-flops F21, F22
Has a sufficient margin for the setup time, and can fetch (latch) desired data even if the timing of the control signal C is slightly deviated.

However, when the data D has a high speed of, for example, 50 MHz or more, the length of the data D for one cycle is shortened, so that the D flip-flops F21 and F22 have no leeway in the setup time. Data cannot be latched accurately.

Therefore, when the data D is high speed,
In order to secure the above setup time as long as possible, a signal rising in synchronization with the rising edge of the clock CP is used as the control signal C. Regarding the operation in this case,
Description will be made with reference to the time chart of the conventional serial-parallel conversion circuit shown in FIG.

First, the serial data D (D0, D1, D2) transmitted in synchronization with the rising edge of the clock CP.
...) is input to the shift register 1. The D flip-flop F11 of the shift register 1 latches the data immediately before it in synchronization with the rising edge of the clock CP. D
The output P1 of the flip-flop F11 receives the input data D as 1
It is delayed by the clock. Similarly, the output P1 is latched by the D flip-flop F12, further delayed by one clock, and becomes the output P2. That is, the relationship between the outputs P1 and P2 at the same time is that the output P2 is the data one clock before the output P1. Next, the D flip-flops F21, F of the parallel circuit 2 are controlled by the control signal C.
22 and outputs P immediately before the rising edge of the control signal C.
1 and P2 are respectively latched and outputs O1 and O2 are output. As described above, the control signal C is a signal obtained by dividing the clock CP by two, and therefore has a cycle twice that. Therefore, the outputs O1 and O2 obtained by latching the outputs P1 and P2 every other clock are paralleled (D0. , D1), (D2, D3) ...
It was to output.

Here, consider a case where a delay d occurs in the control signal C. As shown in FIG. 8, the delay d of the control signal C is determined by the D flip-flops F11 and F12 of the shift register 1.
If the delay is larger than the delay p of the outputs P1 and P2 of the above, the data outputs O1 and O2 latched by the D flip-flops F21 and F22 and output are indefinite. Delay d and delay p
When the difference t from the above is longer than the specified setup time of the D flip-flops F21 and F22, the data D2 next to the originally latched data D1 is latched, and the expected parallel encoded data output cannot be obtained. It was a thing.

[0010]

In the conventional serial-parallel conversion circuit described above, when the delay of the timing of the control signal is larger than the output delay of the D flip-flop of the shift register, the D flip-flop of the parallel circuit is used. Since the parallel data output that is latched and output is indefinite, there is a drawback that the expected parallel encoded data output cannot be obtained.

[0011]

In the serial-parallel conversion circuit of the present invention, N-bit serially encoded data is input to the first circuit and the first clock is used as a shift pulse, and one cycle of the first clock is used. An N-bit shift register composed of N first flip-flops for outputting delayed data delayed by an amount, and N for serially converting the serial encoded data in response to input data driven by the first clock. Controlled by a parallel output circuit having N second flip-flops for supplying output data of each bit of bit parallel encoded data, and a second clock generated by dividing the first clock by N One of the delay data of the N first flip-flops and the output data of the corresponding N second flip-flops is selected. It is constituted by a N selected circuit to the input data of the N second flip-flop.

[0012]

1 is a block diagram showing a first embodiment of a serial-parallel conversion circuit of the present invention. As shown in FIG. 1, the serial-parallel conversion circuit according to the present embodiment has the same structure as that of the conventional one for convenience of description.
It has a bit configuration and the same D flip-flop F as the conventional one.
In addition to the shift register 1 composed of 11 and F12 and the parallel circuit 2 composed of D flip-flops F21 and F22, the D flip-flops F21 and F2 are controlled by the control signal C.
D flip-flop F11,
The output P1, P2 of F12 or the D flip-flop F21,
The control circuit 3 includes selectors 31 and 32 for selecting either one of the output signals O1 and O2 of the F22.

Next, the operation of this embodiment will be described.
D flip-flops F11 and F12 of the shift register 1
Operates with the clock CP as a shift pulse, and the D flip-flops F21 and F22 of the parallel circuit 2 operate with the clock CP.
Driven by. In addition, the selector 13 of the control circuit 3,
The control signal C for controlling 32 is generated by dividing the clock CP by two.

FIG. 2 is a time chart of the circuit of this embodiment shown in FIG. First, the operation of the shift register 1 is as described in the conventional example, and the output P2 of the D flip-flop F12 at the same time is the D flip-flop F.
It is delayed from the output P1 of 11 by one clock. next,
Inputs A of the selectors 31 and 32 of the control circuit 3 have outputs O1 and O2, respectively, and inputs B have outputs P1 and P2.
However, the control signal C is input to each input S. The selectors 31 and 32 respectively select the outputs O1 and O2 when the control signal C is "H" and the outputs P1 and P2 when the control signal C is "L", and supply the outputs Y1 and Y2.

In FIG. 2, focusing on the second clock CP (hereinafter referred to as clock CP2), the control signal C is "L".
Therefore, the selector 31 of the first bit selects the output P1, that is, the first data D (hereinafter referred to as data D1) and outputs the output Y.
Supply as 1 (arrow a). The output Y1 is latched by the D flip-flop F21 at the rising edge of the clock CP3 (arrow b), and at the same time, the control signal C during this period is output.
Is "H", the output O1 of the D flip-flop F21, that is, the data D1 appears at the output Y1 (arrow c). The data D1 is latched by the D flip-flop F21 at the rising edge of the clock CP4 (arrow d), and at the same time, the control signal C is "L" in this period, so the selector 31 selects the output P1, that is, the data D3 and outputs it. Supply as Y1 (arrow e). After that, the same operation is repeated, and as a result, the output O1 of the D flip-flop F21 is output.
The odd-numbered data such as data D1, D3, ... Is output at the timing of dividing the clock CP by two.

The second bit D flip-flop F
12, the selector 32, and the D flip-flop F22 also perform the same operation. As a result, the output O2 of the D flip-flop F22 is the data D2, D4 ,. Is output with. Finally, the same parallel data (D0, D1), (D2, D3) ... Is output as in the conventional example.

In this embodiment, since the D flip-flops F21 and F22 of the parallel circuit 2 are driven by the clock CP,
A setup time T equivalent to one cycle of the clock CP can be secured.

In FIG. 3, as in the conventional example, the delay d of the control signal C is the D flip-flop F11 of the shift register 1,
It is a time chart which shows operation | movement when it is larger than the delay p of output P1 of P12, P2. Due to the delay difference t between the delay d and the delay p, the output Y1 of the selector 31 is the original data D.
Although there is a possibility of outputting the data D2 next to 1, the influence is avoided because the D flip-flops F21 and F22 latch the output Y1 at the rising edge of the clock CP.

FIG. 4 is a block diagram showing a second embodiment of the present invention. The present embodiment is a configuration example of a 4-bit serial-parallel conversion circuit. The difference of this embodiment from the above-mentioned first embodiment is that instead of the 2-bit shift register 1, a 4-stage D is used.
A control circuit including a 4-bit shift register 4 including flip-flops F11 to F14, a parallel circuit 5 including four D flip-flops F21 to F24 in place of the parallel circuit 2, and selectors 31 to 34 in place of the control circuit 3. 6
And to prepare.

D flip-flop F of the shift register 4
11 to F14 operate using the clock CP as a shift pulse, and the D flip-flops F21 to F24 of the parallel circuit 5 are driven by the clock CP. However, the control signal C for controlling the selectors 31 to 34 of the control circuit 6 is generated by dividing the clock CP by 4 and the frequency is 1 / the frequency of the clock CP.
4 and the signal has a duty ratio of 3/4. Therefore, the control signal C has a period of four clocks, which is a "L" period for one clock and an "H" period for three clocks. Each of the selectors 31 to 32 receives the control signal C
Outputs O1 to O4 are selected when H ", and outputs P1 to P4 are selected when the control signal C is" L ", and outputs Y1 to Y4 are supplied.

The operation of this embodiment is the same as that of the first embodiment except that 2 bits become 4 bits. FIG. 5 is an operation time chart of this embodiment.

First, the operation of the shift register 4 is as described in the first embodiment. The output P2 of the D flip-flop F12 and the D flip-flop F at the same time.
13 output P3, D flip-flop F14 output P4
Are delayed from the output P1 of the D flip-flop F11 by 1, 2 and 3 clocks, respectively. Therefore, with respect to the input data D of the D flip-flop F1 at a certain time, as the outputs P1, P2, P3 and P4, data of 1, 2, 3 and 4 clocks before are supplied respectively.

In FIG. 5, first pay attention to the clock CP4, that the output of the control circuit 6 is the outputs Y1 to Y4 of the selectors 31 to 34, and that the output of the shift register 4 is D.
The outputs P1 to P4 of the flip-flops F11 to F14, and the output of the parallel circuit 5 is the D flip-flop F21.
.About.F24 outputs O1 to O4 are the same as the first embodiment.

As a result, the output O1 is the data D3, D7,
The output O2 is data D2, D6, ..., the output O3 is data D1, D5, ..., and the output O4 is data D0, D4 ,. Is output. Finally, 4-bit parallel data (D0, D1, D2, D3), (D
4, D5, D6, D7) ... Are output.

[0025]

As described above, since the serial-parallel conversion circuit of the present invention latches the data of the flip-flop of the parallel circuit at the rising edge of the clock, a sufficient setup time can be obtained even for high speed data. There is an effect that it can be secured and the serial-parallel conversion can be executed surely.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a serial-parallel conversion circuit of the present invention.

FIG. 2 is a time chart showing an example of the operation of the serial-parallel conversion circuit of this embodiment.

FIG. 3 is a time chart considering a delay time in the circuit of the present embodiment.

FIG. 4 is a block diagram showing a second embodiment of the serial-parallel conversion circuit of the present invention.

FIG. 5 is a time chart showing an example of the operation of the serial-parallel conversion circuit of this embodiment.

FIG. 6 is a block diagram showing an example of a conventional serial-parallel conversion circuit.

FIG. 7 is a time chart showing an example of the operation of a conventional serial-parallel conversion circuit.

FIG. 8 is a time chart considering a delay time in a conventional circuit.

[Explanation of symbols]

1,4 Shift register 2,5 Parallel circuit 3,6 Control circuit 31-34 Selector F11-F14, F21-F24 D flip-flop

Claims (2)

[Claims] 1. N first serial data, which are input as N-bit serially encoded data and output delay data delayed by one cycle of the first clock as a shift pulse, respectively. N-bit shift register composed of flip-flops, and output data of each bit of N-bit parallel encoded data which is driven by the first clock and parallel-converts the serial encoded data in response to input data. And a parallel output circuit having N second flip-flops for supplying each of the delays of the N first flip-flops controlled by a second clock generated by dividing the first clock by N. Either one of the data and the corresponding output data of the N second flip-flops is selected to input each of the N second flip-flops. Serial-parallel conversion circuit, characterized in that it comprises a N selected circuit to data. 2. The serial-parallel conversion circuit according to claim 1, wherein the first and second flip-flops are D-type flip-flops.