JPH06169061A - Input/output protecting device - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the size of the input / output protection device, improve electrostatic discharge withstand capability, and prevent the cost from increasing significantly. A metal layer 16 is provided above the isolation layer 6 and covers the vicinity of the isolation layer 6 on the substrate surface between the contact portion of the protection resistor 4 and the isolation layer 6. Is electrically connected to the insulation layer 6 and is embedded in the insulating film 8a. The metal layer 16 prevents an electric field from being generated on the surface of the substrate between the protection resistor 4 and the isolation layer 6 due to a surge generated in the metal wiring 10 and prevents electrostatic breakdown.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output protection device having an improved electrostatic breakdown resistance, such as a CMOS.
The present invention relates to a device used as an input protection device for a semiconductor device or as a protection device for a terminal to which a high voltage higher than a power supply voltage is applied.

[0002]

2. Description of the Related Art An example of a conventional input protection resistor is shown in FIG. The protective resistor 4 is formed as a P-type diffusion layer on the surface of the N-type silicon substrate 2, and an isolation layer 6 of an N-type diffusion layer is formed around the protective resistor 4 on the surface of the substrate so as to surround the protective resistor 4. Has been done. A field oxide film 8 is formed so as to cover the surface of the substrate, and a metal wiring 10 connected to a pad is connected to the protective resistor 4 through a contact hole provided in the field oxide film 8. Reference numeral 12 is a contact that connects the resistor 4 and the metal wiring 10.

In this input protection resistor, the electrostatic breakdown voltage differs depending on whether the input pin or the output pin is positively biased or negatively biased with respect to the power supply pin or the ground pin. The resistance to electrostatic breakdown when the protection resistor 4 is reversely biased with respect to the substrate 2 is the smallest. At this time, the electrostatic breakdown resistance is determined by the reverse bias surge current withstand voltage of this junction because the diffusion layer forming the protection resistor 4 is reverse biased with respect to the substrate 2. In particular, an inversion layer is likely to be formed on the substrate surface due to the potential of the metal wiring 10. In fact, the breakdown occurs on the substrate surface between the contact portion of the protection resistor 4 and the isolation 6, and in order to improve the electrostatic breakdown resistance, it is necessary to have a structure for avoiding the electric field concentration on the substrate surface. One of the countermeasures is to lengthen the distance of the substrate surface between the contact portion of the protection resistor 4 and the isolation 6, and this can be improved to some extent. This leads to the problem of increased cost due to the increased spacing.

Therefore, in order to obtain a protection resistor which is small in size and has a high electrostatic breakdown resistance, a junction having a breakdown voltage smaller than the surface discharge voltage is formed inside the substrate to allow a current to flow in the bulk, and electrostatic discharge. An input protection device has been proposed to improve the breakdown resistance (Japanese Patent Publication No. 64-1094).
See Japanese Patent Publication No. 4).

[0005]

The input protection device proposed in the cited example has a drawback that the process period is long and the layout area is large because it is necessary to add a diffusion layer. As a result, the cost is increased. SUMMARY OF THE INVENTION It is an object of the present invention to provide an input / output protection device which has a simple structure that can be downsized and has improved electrostatic breakdown resistance, and which does not cause a significant increase in cost.

[0006]

In the input / output protection device of the present invention, the periphery of the input protection resistor of the first conductivity type diffusion layer is surrounded by the isolation layer of the second conductivity type diffusion layer on the surface of the substrate. At least a part of the substrate surface between the isolation layer and the input protection resistor is covered with a conductor layer. In a preferred aspect, the isolation layer and the conductor layer are electrically connected. In another preferred aspect, the isolation layer and the conductor layer are electrically insulated, and the conductor layer is fixed at a constant potential.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment. The same parts as those in FIG. 3 are designated by the same reference numerals. A protective resistor 4 made of a P-type diffusion layer is formed on the surface of the N-type silicon substrate 2, and an isolation layer 6 made of an N-type diffusion layer is formed around the protective resistor 4. The structure up to this point is the same as in FIG. An insulating film 8a is formed on the substrate 2, a metal wiring 10 connected to a pad is formed on the insulating film 8a, and the insulating film 8a is formed to connect the metal wiring 10 and the protective resistor 4.
A contact hole is formed in a, and the metal wiring 10 and the protective resistor 4 are connected through the metal layer 14 in the contact hole.

A metal layer 16 is provided above the isolation layer 6 and covers the vicinity of the isolation layer 6 on the substrate surface between the contact portion of the protection resistor 4 and the isolation layer 6. Is electrically connected to the insulation layer 6 and is embedded in the insulating film 8a. The metal layer 16 does not cover the entire region of the substrate surface inside the isolation layer 6, but mainly covers the substrate surface around the contact portion of the protective resistor 4. However, the metal layer 16 may cover the entire substrate surface inside the isolation layer 6.

The metal layers 14 and 16 are, for example, aluminum or an aluminum alloy containing a slight amount of silicon in aluminum. The metal layers 14 and 16 can be replaced with a low resistance polycrystalline silicon layer. Figure 1
In the embodiment, the metal layer 16 prevents an electric field from being generated on the substrate surface between the protection resistor 4 and the isolation layer 6 due to a surge generated in the metal wiring 10 from the input pad, thereby preventing electrostatic breakdown. .

Next, a method of manufacturing the embodiment shown in FIG. 1 will be described. After forming the protective resistor 4 and the isolation layer 6 on the silicon substrate 2, the surface of the substrate is covered with a field oxide film. In the field oxide film, contact holes are formed in the region where the contact 14 is formed and the region on the isolation layer 6. A metal layer is deposited and patterned by photolithography and etching to form a contact metal layer 14 and a metal layer 16.

Next, a contact hole is formed on the contact 14 in the insulating film, which has a large amount of insulating film on the entire surface by the CVD method. After that, a metal layer is deposited on the entire surface, the metal wiring 10 is formed by photolithography and etching, and the metal wiring 10 and the protective resistor 4 are connected via the metal layer 14. Although the metal layer 16 is electrically connected to the isolation layer 6 in the embodiment of FIG. 1, the metal layer 6 and the isolation layer 16 may be insulated.

FIG. 2 shows a second embodiment. Compared with the embodiment of FIG. 1, the metal layer 16 embedded in the insulating layer 8a is insulated from the isolation layer 6, and the isolation layer 16 is integrally formed with the wiring 1.
It is fixed to a fixed potential, for example, a power supply potential via 8. The embodiment of FIG. 2 has the same effect as that of the embodiment of FIG. 1, and when a positive surge is applied to the metal wiring 10, the diffusion layer of the protection resistor 4 is the source, the metal wiring 16 is the gate,
A parasitic field MOS transistor having the P-type isolation layer 18 existing in the vicinity as a drain is turned on to release the electric charge. This has the function of protecting the internal circuit from damage. In the examples, the part expressed as the substrate 2 includes the case where it is an epitaxial layer.

[0013]

According to the present invention, since the conductor layer is formed on the isolation layer surrounding the protection resistor so as to cover at least a part of the substrate surface between the isolation layer and the protection resistor. The electric field can be prevented from concentrating on the substrate surface between the isolation layer and the protection resistor, increasing the electrostatic breakdown resistance, and even if the distance between the isolation layer and the protection resistor is shortened Since the breakage resistance can be maintained large, it is possible to reduce the size of the entire protection device, which in turn can reduce the cost. The input / output protection device of the present invention can also be used as a terminal to which a voltage higher than the power supply voltage is applied, and in that case, surface leakage from the protection resistor to the isolation layer can be suppressed.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment, (A) is a schematic plan view, and (B) is a sectional view taken along line XX in (A).

2A and 2B are views showing a second embodiment, FIG. 2A is a schematic plan view, and FIG. 2B is a sectional view taken along line YY of FIG.

3A and 3B are diagrams showing a conventional input protection device, in which FIG. 3A is a schematic plan view and FIG. 3B is a sectional view taken along line ZZ of FIG.

[Explanation of symbols]

4 protection resistance 6 isolation layer 8a insulating film 10 metal wiring 14 metal layer for contact 16 metal layer covering the upper part of the substrate near the isolation layer

[Procedure amendment]

[Submission date] April 7, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

In this input protection resistor, the electrostatic breakdown voltage differs depending on whether the input pin or the output pin is positively biased or negatively biased with respect to the power supply pin or the ground pin. The resistance to electrostatic breakdown when the protection resistor 4 is reversely biased with respect to the substrate 2 is the smallest. The electrostatic breakdown withstand capability at this time is determined by the reverse bias surge current withstand capability of this junction because the diffusion layer forming the protection resistor 4 is reverse biased with respect to the substrate 2. In particular, an inversion layer is likely to be formed on the substrate surface due to the potential of the metal wiring 10. In fact, the breakdown occurs on the substrate surface between the contact portion of the protection resistor 4 and the isolation 6, and in order to improve the electrostatic breakdown resistance, it is necessary to have a structure for avoiding the electric field concentration on the substrate surface. One of the measures is to increase the distance of the substrate surface between the contact portion of the protective resistor 4 and the isolation 6, and this can be improved to some extent. This leads to the problem of increased cost due to the increased spacing.

[Procedure amendment]

[Submission date] August 9, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (3)

[Claims] 1. An input protection resistor formed by a diffusion layer of a first conductivity type is surrounded by an isolation layer formed by a diffusion layer of a second conductivity type on a surface of a substrate, and the input protection resistor between the isolation layer and the input protection resistor is formed. An input / output protection device in which at least a part of the substrate surface is covered with a conductor layer. 2. The input / output protection device according to claim 1, wherein the isolation layer and the conductor layer are electrically connected. 3. The input / output protection device according to claim 1, wherein the isolation layer and the conductor layer are electrically insulated, and the conductor layer is fixed at a constant potential.