JPH06164653A - Data transfer device - Google Patents

Abstract

(57) [Abstract] An object of the present invention is, in a data transfer device, to perform highly efficient and high-speed data transfer with a relatively small number of signal lines even if relatively long data is transmitted without distinguishing and transmitting a clock signal and a data signal. The purpose is to [Structure] When there are 256 patterns of 8-bit data, the continuous data does not have the same pattern when divided into 3 bits.
³ -1) x (2 ³ -1) x (2 ³ -1) "in the 8-bit / 9-bit conversion table 13 having the 9-bit data pattern, and one set of the 9-bit data pattern is converted from the 9-bit shift register 14 to the three signal lines 16a.
16c, 3 bits are transferred 3 times at a time, the data change of the 3 bit pattern is taken in by the 9 bit shift register at the receiving side as a timing, and the data is replaced and decoded again with the 8 bit data pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device for transferring data at high speed using signal lines.

[0002]

2. Description of the Related Art Data transfer is generally carried out over a long distance, and the wiring cost occupies the largest proportion of the communication cost. Therefore, it is often the case that the number of wirings is small, but the cost is still low even if the cost is increased. Conventionally, the following method has been adopted as a data transfer device for transferring data using one or two signal lines.

The first method is called an asynchronous method, and this transmission method adds a start bit to the beginning of each character to be transmitted and a stop bit to the end, and
Bit synchronization is performed for each character, and data can be transferred via a single signal line.

That is, when data is transmitted in the asynchronous mode, the start bit is sent from the transmitting side to the receiving side so that the transmission start of the data bit of the transmitting side and the sampling start of the data bit of the receiving side are started. To be combined. In this case, the sending clock of the data bit on the transmitting side and the sampling clock on the receiving side (for example, a clock having a cycle 16 times the transmission rate) need to be adjusted to the same frequency.

In order to transmit 8-bit data, the start bit is 1 bit, the data bit is 8 bits,
A total of 10 clocks with 1 stop bit is required.

As described above, when sending out a character having an n-bit length, two bits of a start bit and a stop bit are added before and after that, and the time for transmitting one character is substantially the same as the actual character. It will be longer than when sending. Therefore, although the effective transmission speed becomes slower, only one signal line is required.

The second method is a synchronous non-confirmation method in which two signal lines, a data line and a control line, are used and a data signal and a clock signal are simultaneously output. For example, one signal line is for data signal transmission. In addition, the other one signal line is used for sending a clock signal.

In this case, the receiving side attempts to receive the data by sampling the data signal in accordance with the given clock. It takes 8 clocks to transfer the 8-bit data by this synchronous non-confirmation method. You will need it.

[0009]

However, in such a conventional data transfer apparatus, in the start-stop synchronization method according to the first method, only one signal line is required, but the clocks on the transmitting side and the receiving side are synchronized. Since data bits cannot be transmitted accurately unless they are correctly aligned, it is necessary to have highly accurate clocks on both the transmitting side and the receiving side.

Further, in the synchronization non-confirmation method according to the second method, although a clock is not required on the receiving side, one signal line is used as a control signal line dedicated to the clock, and about two lines are used. There is a problem that efficiency is deteriorated when data is transferred using a signal line.

That is, in order to transfer data at high speed with one signal line, it is sufficient to increase the frequency of the transfer clock in the asynchronous method, but there is an upper limit of the frequency due to the characteristics of the signal line. In order to transfer data faster than this upper limit, it is necessary to use two signal lines. Thus, when two signal lines are used, if the synchronous non-confirmation method according to the second method is used, one signal line is used exclusively for the clock. Even if the above is provided, as is clear from the above-mentioned example, only speed improvement of about 10: 8 is achieved. However, if the number of data signal lines is further increased, the ratio of the clock signal to the entire signal decreases, so that the transfer efficiency is improved accordingly.

[0012] As described above, the start-stop synchronization method has a great advantage that the cost for transmission is low because only one signal line is required, but it is difficult to increase the transmission speed. At present, even if the number of signal lines is two, the transmission speed cannot be improved so much. It is considered that this is because the conventional data transfer method using the clock signal and the data signal is approaching the limit in principle.

The present invention has been made in view of the above problems,
An object of the present invention is to provide a data transfer device capable of performing high-efficiency and high-speed data transfer without separately transmitting a clock signal and a data signal.

[0014]

That is, the data transfer apparatus according to the present invention uses (M × N−) as the transferred data.
X) [1.ltoreq.X <M] bit data is converted to M.times.N bit data in which consecutive M bit data does not form the same bit pattern, and M.times.N bit obtained by this data converting device. Transmitting means for transmitting data by dividing the data by the M bit data N times, and receiving for receiving M bit data sequentially divided and transmitted by the transmitting means as M × N bit data by extracting each bit pattern change. Means and decoding means for decoding the M × N bit data received by the receiving means into the (M × N−X) bit data, and for transferring, for example, 8 bit data, 8-bit data is converted corresponding to 9-bit data consisting of 3 bits + 3 bits + 3 bits, and the above 3 bits are transferred three times through three signal lines to 1 To transfer data in pairs,
In this case, the 8-bit / 9-bit conversion table is set in advance so that the sequentially transferred 3-bit data is changed by at least 1 bit, and the 3-bit data is detected as a 9-bit shift register. And is decoded from the 9-bit to 8-bit through the conversion table.

[0015]

Operation: In other words, an 8-bit (1 byte) data pattern is 2 ⁸ = 256 types exist, but this is 3 bits + 3
Assuming that the data is divided into 2 bits + 2 bits and transferred, the combination is 256 = 2 ³ × 2 ³ × 2 ² Becomes

On the other hand, assuming that a 9-bit data pattern is divided into 3 bits + 3 bits + 3 bits and transferred, the combination is 512 = 2 ^3. × 2 ³ × 2 ³ Becomes

Here, except for the same pattern in which the sequentially transferred 3-bit data are duplicated, the combination is (2 ³ -1) x (2 ³ -1) x (2 ³ -1) = 343 types exist.

Therefore, the 256-bit 8-bit data pattern is replaced in the 343 9-bit data pattern in which continuous data does not become the same pattern when the 3-bit data pattern is divided. , A set of the 9-bit data pattern is transferred 3 times by 3 bits through 3 signal lines, and the data change of the 3-bit pattern is taken as a timing by the 9-bit shift register at the receiving side, and the 8-bit data pattern is again taken. If the replacement decoding is performed, the data signal can be efficiently transferred with a small number of signal lines without requiring an independent clock signal for the data signal.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a transmission side device of an 8-bit data transfer device, in which 8 bits as transferred data.
The bit data is latched by the latch circuit 11, and the conversion destination address of the conversion table 13 is designated by the address circuit 12 according to the content of the 8-bit data latched by the latch circuit 11.

The 8-bit / 9-bit conversion table 13 is
All combinations of 8-bit data given as transferred data (256 patterns = 2 ⁸ ) Corresponding to), in this case, when the 9-bit data is divided into 3 bits + 3 bits + 3 bits, the continuous 3-bit data does not have the same data pattern in 343 ways. "= (2 ³ -1) x (2 ³ −
1) × (2 ³ −1) ”, which is associated with the 9-bit data. The 9-bit data obtained by this conversion table 13 is the 9-bit shift register 14
Is output to.

The 9-bit shift register 14 takes in 9-bit data in order to divide it into the above 3 bits + 3 bits + 3 bits and divides and outputs it in three times according to the timing signal from the timing signal generating circuit 15. The 3-bit data sequentially output from the bit shift register 14 is transferred from the AND gates AND1 to AND3 to the receiving side via the three signal lines 16a to 16c.

The timing signal generation circuit 15 generates a timing signal and a data latch signal three times for the 9-bit shift register 14, and the latch circuit 11 and the address circuit 12 respond to the data latch signal. A timing signal is supplied to specify the next data, and 8-bit data as the transferred data is latched and the conversion table 13 is addressed to 9-bit data conversion. Therefore, at the timing when the latch signal is given to the shift register 14, an idle cycle in which no data transfer is performed becomes three AND gate AND
Timing signals are simultaneously supplied to 1 to AND3 three times during each transfer idle cycle, and 9-bit data divided into 3 bits is output.

In this case, since no timing signal is supplied to the AND gates AND1 to AND3 in the transfer idle cycle of the 9-bit data, all three signal lines are set to "0".

FIG. 2 is a circuit diagram showing the configuration of the receiving side device of the 8-bit data transfer device. The 3-bit data sent from the transmitting side device through the three signal lines 16a to 16c is 9 bits. It is given to the shift register 21.

The 9-bit shift register 21 has a level change detection circuit 22 corresponding to the data change of the 3-bit data sent through the three signal lines 16a to 16c.
Input the shift timing signal output from the
Bit data is sequentially input as 0, 3, 6th bit + 1, 4, 4, 7th bit + 2, 5, 8th bit and fetched as 9-bit data. Since the signal lines 16a to 16c of the book are all set to "0", the reset signal R of the 9-bit shift register 21 is supplied via the NOR gate NOR.

The 9-bit data fetched by the 9-bit shift register 21 is the timing signal generating circuit 2.
3 bits are given to the address circuit 24 in synchronization with the timing signal corresponding to the transfer idle cycle from
The conversion destination address of the 8-bit conversion table 25 is designated.

The 9-bit / 8-bit conversion table 25 is
The conversion table has a conversion table that is completely opposite to the 8-bit / 9-bit conversion table 13 in the transmission side device, and converts and decodes the 9-bit data obtained by the 9-bit shift register 21 into 8-bit data. 25
The 8-bit data decoded via is latched in the latch circuit 26 according to the timing signal generated from the timing signal generation circuit 23 at the same time as the timing signal to the address circuit 24, and output as reception data.

FIG. 3 shows the configuration of the 9-bit shift register 14 in the transmission side device of the 8-bit data transfer device. The 9-bit shift register 14 is set in the 9-bit shift register 14 through the 8-bit / 9-bit conversion table 13. Since the data D0 to D8 are shifted according to the timing signal from the timing signal generating circuit 15, their outputs are D0, D3, D6 → D1, D4, D7 → D2, D5, D.
It changes to 8 and the signal line 16
a to 16c are output and transferred to the receiving side device.

That is, in the 8-bit data transfer device having the above structure, when the 8-bit data as the transferred data is latched by the latch circuit 11 of the transmission side device, the address circuit 12 causes the 8-bit / 9-bit conversion table 13 to be stored. The conversion destination address is designated, and the conversion table 13
The 9-bit data obtained by is given to the 9-bit shift register 14.

Then, the 9-bit shift register 14
The 9-bit data set to is divided into 3 times by 3 bits and output to the signal lines 16a to 16c through the AND gates AND1 to AND3.

[0032] In this case, the data pattern of 8 bits existing 256, it no 343 kinds of data to the continuous case of dividing into three times for 3 bits above the same pattern "= (2 ³ -1) x (2 ³ -1) x (2 ³
−1) ”is replaced from the 9-bit data pattern, the 3-bit data sequentially transferred to the signal lines 16a to 16c have different bit patterns before and after that, and the receiving side device detects the level change. When the level change of the signal lines 16a to 16c obtained by the circuit 22 is detected,
By setting the shift timing of the bit shift register 21, the 9-bit data transferred from the transmitting side device can be surely taken in without transmitting / receiving a specific clock signal.

Then, when 9-bit data is obtained in the 9-bit shift register 21 of the receiving side device, the 9-bit / 8-bit conversion table 25 is addressed corresponding to the 9-bit data, and is passed through the latch circuit 26. 8-bit data is decoded and output.

Therefore, according to the 8-bit data transfer device having the above-mentioned structure, when the 8-bit data pattern of 256 patterns is divided into 3 bits, the continuous data does not have the same pattern of 343 patterns. "= (2 ³ -1) x (2 ³ -1) x (2 ³ -1) "9
The conversion is performed in the 8-bit / 9-bit conversion table 13 having the bit data pattern, and one set of the 9-bit data pattern is transferred from the 9-bit shift register 14 through the three signal lines 16a to 16c three times at a time for every three bits. In the receiving side, the data change of the 3-bit pattern is taken as a timing by the 9-bit shift register, and the decoding is performed again by substituting the 8-bit data pattern. Therefore, the clock signal independent of the data signal is not required, Even long data can be efficiently transferred with a small number of signal lines.

[0035]

As described above, according to the present invention, consecutive (M × N−X) [1 ≦ X <M] bit data as transferred data does not have the same bit pattern. Data converting means for converting into M × N bit data, transmitting means for transmitting the M × N bit data obtained by the data converting means N times each of the M bit data, and transmitting, and sequentially dividing by this transmitting means. The receiving means for extracting the transmitted M-bit data for each change of the bit pattern and receiving it as M × N-bit data, and the M × N-bit data received by this receiving means are described in the above (M
XN-X) Decoding means for decoding into bit data is provided, so that it is possible to achieve high efficiency and high speed with relatively few data lines and relatively few data lines without separately transmitting the clock signal and the data signal. Data can be transferred.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a transmission side device of an 8-bit data transfer device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a receiving side device of the 8-bit data transfer device.

FIG. 3 is a diagram showing a configuration of a 9-bit shift register in a transmission side device of the 8-bit data transfer device.

[Explanation of symbols]

11 ... Transmitting side latch circuit, 12 ... Transmitting side address circuit,
13 ... 8-bit / 9-bit conversion table, 14 ... Transmission side 9-bit shift register, 15 ... Transmission side timing signal generation circuit, 16a to 16c ... Signal line, 21 ... Reception side 9-bit shift register, 22 ... Level change detection circuit , 23
... reception side timing signal generation circuit, 24 ... reception side address circuit, 25 ... 9-bit / 8-bit conversion table, 26
... Reception side latch circuit.

Claims (1)

[Claims] 1. (M × N−X) as transferred data
Data conversion means for converting [1 ≦ X <M] bit data into M × N bit data in which consecutive M bit data do not form the same bit pattern, and M × N bit data obtained by this data conversion means. Transmitting means for dividing the M-bit data by N times for transmission, and receiving means for extracting the M-bit data sequentially divided and transmitted by the transmitting means for each change of the bit pattern and receiving it as M × N-bit data. A data transfer device comprising: decoding means for decoding the M × N bit data received by the receiving means into the (M × N−X) bit data.